1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * SPL 17 */ 18 19 #define CONFIG_SPL_FRAMEWORK 20 #define CONFIG_SPL_LIBGENERIC_SUPPORT 21 #define CONFIG_SPL_SERIAL_SUPPORT 22 #define CONFIG_SPL_NOR_SUPPORT 23 #define CONFIG_SPL_TEXT_BASE 0xffff0000 24 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 25 #define CONFIG_SPL_STACK 0x00020000 26 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 27 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 28 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 29 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 30 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" 31 #define CONFIG_SPL_BOARD_INIT 32 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 33 #define CONFIG_SYS_UBOOT_START 0x00800000 34 #define CONFIG_SYS_TEXT_BASE 0x00800000 35 36 /* 37 * Version number information 38 */ 39 40 #define CONFIG_IDENT_STRING " EDMiniV2" 41 42 /* 43 * High Level Configuration Options (easy to change) 44 */ 45 46 #define CONFIG_MARVELL 1 47 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 48 #define CONFIG_88F5182 1 /* SOC Name */ 49 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 50 51 #include <asm/arch/orion5x.h> 52 /* 53 * CLKs configurations 54 */ 55 56 /* 57 * Board-specific values for Orion5x MPP low level init: 58 * - MPPs 12 to 15 are SATA LEDs (mode 5) 59 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 60 * MPP16 to MPP19, mode 0 for others 61 */ 62 63 #define ORION5X_MPP0_7 0x00000003 64 #define ORION5X_MPP8_15 0x55550000 65 #define ORION5X_MPP16_23 0x00005555 66 67 /* 68 * Board-specific values for Orion5x GPIO low level init: 69 * - GPIO3 is input (RTC interrupt) 70 * - GPIO16 is Power LED control (0 = on, 1 = off) 71 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 72 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 73 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 74 * - GPIO22 is SATA disk power status () 75 * - GPIO23 is supply status for SATA disk () 76 * - GPIO24 is supply control for board (write 1 to power off) 77 * Last GPIO is 25, further bits are supposed to be 0. 78 * Enable mask has ones for INPUT, 0 for OUTPUT. 79 * Default is LED ON, board ON :) 80 */ 81 82 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 83 #define ORION5X_GPIO_OUT_VALUE 0x00000000 84 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 85 86 /* 87 * NS16550 Configuration 88 */ 89 90 #define CONFIG_SYS_NS16550_SERIAL 91 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 92 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 93 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 94 95 /* 96 * Serial Port configuration 97 * The following definitions let you select what serial you want to use 98 * for your console driver. 99 */ 100 101 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 102 #define CONFIG_BAUDRATE 115200 103 #define CONFIG_SYS_BAUDRATE_TABLE \ 104 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 105 106 /* 107 * FLASH configuration 108 */ 109 110 #define CONFIG_SYS_FLASH_CFI 111 #define CONFIG_FLASH_CFI_DRIVER 112 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 113 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 114 #define CONFIG_SYS_FLASH_BASE 0xfff80000 115 116 /* auto boot */ 117 118 /* 119 * For booting Linux, the board info and command line data 120 * have to be in the first 8 MB of memory, since this is 121 * the maximum mapped by the Linux kernel during initialization. 122 */ 123 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 124 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 125 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 126 127 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 129 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 130 /* 131 * Commands configuration 132 */ 133 #define CONFIG_CMD_IDE 134 135 /* 136 * Network 137 */ 138 139 #ifdef CONFIG_CMD_NET 140 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 141 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 142 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 143 #define CONFIG_PHY_BASE_ADR 0x8 144 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 145 #define CONFIG_NETCONSOLE /* include NetConsole support */ 146 #define CONFIG_MII /* expose smi ove miiphy interface */ 147 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 148 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 149 #endif 150 151 /* 152 * IDE 153 */ 154 #ifdef CONFIG_CMD_IDE 155 #define __io 156 #define CONFIG_IDE_PREINIT 157 #define CONFIG_DOS_PARTITION 158 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 159 #define CONFIG_MVSATA_IDE 160 #define CONFIG_MVSATA_IDE_USE_PORT1 161 /* Needs byte-swapping for ATA data register */ 162 #define CONFIG_IDE_SWAP_IO 163 /* Data, registers and alternate blocks are at the same offset */ 164 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 165 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 166 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 167 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 168 #define CONFIG_SYS_ATA_STRIDE 4 169 /* Controller supports 48-bits LBA addressing */ 170 #define CONFIG_LBA48 171 /* A single bus, a single device */ 172 #define CONFIG_SYS_IDE_MAXBUS 1 173 #define CONFIG_SYS_IDE_MAXDEVICE 1 174 /* ATA registers base is at SATA controller base */ 175 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 176 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 177 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 178 /* end of IDE defines */ 179 #endif /* CMD_IDE */ 180 181 /* 182 * Common USB/EHCI configuration 183 */ 184 #ifdef CONFIG_CMD_USB 185 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 186 #define CONFIG_USB_EHCI_MARVELL 187 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 188 #define CONFIG_DOS_PARTITION 189 #define CONFIG_ISO_PARTITION 190 #define CONFIG_SUPPORT_VFAT 191 #endif /* CONFIG_CMD_USB */ 192 193 /* 194 * I2C related stuff 195 */ 196 #ifdef CONFIG_CMD_I2C 197 #define CONFIG_SYS_I2C 198 #define CONFIG_SYS_I2C_MVTWSI 199 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 200 #define CONFIG_SYS_I2C_SLAVE 0x0 201 #define CONFIG_SYS_I2C_SPEED 100000 202 #endif 203 204 /* 205 * Environment variables configurations 206 */ 207 #define CONFIG_ENV_IS_IN_FLASH 1 208 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 209 #define CONFIG_ENV_SIZE 0x2000 210 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 211 212 /* 213 * Size of malloc() pool 214 */ 215 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 216 217 /* 218 * Other required minimal configurations 219 */ 220 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 221 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 222 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 223 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 224 #define CONFIG_NR_DRAM_BANKS 1 225 226 #define CONFIG_SYS_LOAD_ADDR 0x00800000 227 #define CONFIG_SYS_MEMTEST_START 0x00400000 228 #define CONFIG_SYS_MEMTEST_END 0x007fffff 229 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 230 #define CONFIG_SYS_MAXARGS 16 231 232 /* Enable command line editing */ 233 #define CONFIG_CMDLINE_EDITING 234 235 /* provide extensive help */ 236 #define CONFIG_SYS_LONGHELP 237 238 /* additions for new relocation code, must be added to all boards */ 239 #define CONFIG_SYS_SDRAM_BASE 0 240 #define CONFIG_SYS_INIT_SP_ADDR \ 241 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 242 243 #endif /* _CONFIG_EDMINIV2_H */ 244