1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_SERIAL_SUPPORT 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_FSL_LAW /* Use common FSL init code */ 49 #define CONFIG_SYS_TEXT_BASE 0x00201000 50 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 51 #define CONFIG_SPL_PAD_TO 0x40000 52 #define CONFIG_SPL_MAX_SIZE 0x28000 53 #define RESET_VECTOR_OFFSET 0x27FFC 54 #define BOOT_PAGE_OFFSET 0x27000 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_SKIP_RELOCATE 57 #define CONFIG_SPL_COMMON_INIT_DDR 58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #define CONFIG_SYS_NO_FLASH 60 #endif 61 62 #ifdef CONFIG_NAND 63 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 65 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 66 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 68 #define CONFIG_SPL_NAND_BOOT 69 #endif 70 71 #ifdef CONFIG_SPIFLASH 72 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 73 #define CONFIG_SPL_SPI_SUPPORT 74 #define CONFIG_SPL_SPI_FLASH_SUPPORT 75 #define CONFIG_SPL_SPI_FLASH_MINIMAL 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 81 #ifndef CONFIG_SPL_BUILD 82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 83 #endif 84 #define CONFIG_SPL_SPI_BOOT 85 #endif 86 87 #ifdef CONFIG_SDCARD 88 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 89 #define CONFIG_SPL_MMC_MINIMAL 90 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 91 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 92 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 93 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 95 #ifndef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #endif 98 #define CONFIG_SPL_MMC_BOOT 99 #endif 100 101 #endif /* CONFIG_RAMBOOT_PBL */ 102 103 #define CONFIG_SRIO_PCIE_BOOT_MASTER 104 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 105 /* Set 1M boot space */ 106 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 108 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 109 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 110 #define CONFIG_SYS_NO_FLASH 111 #endif 112 113 #ifndef CONFIG_SYS_TEXT_BASE 114 #define CONFIG_SYS_TEXT_BASE 0xeff40000 115 #endif 116 117 #ifndef CONFIG_RESET_VECTOR_ADDRESS 118 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 119 #endif 120 121 /* 122 * These can be toggled for performance analysis, otherwise use default. 123 */ 124 #define CONFIG_SYS_CACHE_STASHING 125 #define CONFIG_BTB /* toggle branch predition */ 126 #define CONFIG_DDR_ECC 127 #ifdef CONFIG_DDR_ECC 128 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #endif 131 132 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 133 #define CONFIG_SYS_MEMTEST_END 0x00400000 134 #define CONFIG_SYS_ALT_MEMTEST 135 136 #ifndef CONFIG_SYS_NO_FLASH 137 #define CONFIG_FLASH_CFI_DRIVER 138 #define CONFIG_SYS_FLASH_CFI 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 140 #endif 141 142 #if defined(CONFIG_SPIFLASH) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_ENV_IS_IN_SPI_FLASH 145 #define CONFIG_ENV_SPI_BUS 0 146 #define CONFIG_ENV_SPI_CS 0 147 #define CONFIG_ENV_SPI_MAX_HZ 10000000 148 #define CONFIG_ENV_SPI_MODE 0 149 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 150 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 151 #define CONFIG_ENV_SECT_SIZE 0x10000 152 #elif defined(CONFIG_SDCARD) 153 #define CONFIG_SYS_EXTRA_ENV_RELOC 154 #define CONFIG_ENV_IS_IN_MMC 155 #define CONFIG_SYS_MMC_ENV_DEV 0 156 #define CONFIG_ENV_SIZE 0x2000 157 #define CONFIG_ENV_OFFSET (512 * 0x800) 158 #elif defined(CONFIG_NAND) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_NAND 161 #define CONFIG_ENV_SIZE 0x2000 162 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 163 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 164 #define CONFIG_ENV_IS_IN_REMOTE 165 #define CONFIG_ENV_ADDR 0xffe20000 166 #define CONFIG_ENV_SIZE 0x2000 167 #elif defined(CONFIG_ENV_IS_NOWHERE) 168 #define CONFIG_ENV_SIZE 0x2000 169 #else 170 #define CONFIG_ENV_IS_IN_FLASH 171 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 172 #define CONFIG_ENV_SIZE 0x2000 173 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 174 #endif 175 176 #ifndef __ASSEMBLY__ 177 unsigned long get_board_sys_clk(void); 178 unsigned long get_board_ddr_clk(void); 179 #endif 180 181 #define CONFIG_SYS_CLK_FREQ 66660000 182 #define CONFIG_DDR_CLK_FREQ 133330000 183 184 /* 185 * Config the L3 Cache as L3 SRAM 186 */ 187 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 188 #define CONFIG_SYS_L3_SIZE (512 << 10) 189 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 190 #ifdef CONFIG_RAMBOOT_PBL 191 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 192 #endif 193 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 194 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 195 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 196 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 197 198 #define CONFIG_SYS_DCSRBAR 0xf0000000 199 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 200 201 /* EEPROM */ 202 #define CONFIG_ID_EEPROM 203 #define CONFIG_SYS_I2C_EEPROM_NXID 204 #define CONFIG_SYS_EEPROM_BUS_NUM 0 205 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 206 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 207 208 /* 209 * DDR Setup 210 */ 211 #define CONFIG_VERY_BIG_RAM 212 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 213 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 214 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 215 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 216 #define CONFIG_DDR_SPD 217 #define CONFIG_SYS_FSL_DDR3 218 #undef CONFIG_FSL_DDR_INTERACTIVE 219 #define CONFIG_SYS_SPD_BUS_NUM 0 220 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 221 #define SPD_EEPROM_ADDRESS1 0x51 222 #define SPD_EEPROM_ADDRESS2 0x52 223 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 224 #define CTRL_INTLV_PREFERED cacheline 225 226 /* 227 * IFC Definitions 228 */ 229 #define CONFIG_SYS_FLASH_BASE 0xe8000000 230 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 231 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 232 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 233 CSPR_PORT_SIZE_16 | \ 234 CSPR_MSEL_NOR | \ 235 CSPR_V) 236 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 237 238 /* NOR Flash Timing Params */ 239 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 240 241 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 242 FTIM0_NOR_TEADC(0x5) | \ 243 FTIM0_NOR_TEAHC(0x5)) 244 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 245 FTIM1_NOR_TRAD_NOR(0x1A) |\ 246 FTIM1_NOR_TSEQRAD_NOR(0x13)) 247 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 248 FTIM2_NOR_TCH(0x4) | \ 249 FTIM2_NOR_TWPH(0x0E) | \ 250 FTIM2_NOR_TWP(0x1c)) 251 #define CONFIG_SYS_NOR_FTIM3 0x0 252 253 #define CONFIG_SYS_FLASH_QUIET_TEST 254 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 255 256 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 257 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 258 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 259 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 260 #define CONFIG_SYS_FLASH_EMPTY_INFO 261 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 262 263 /* CPLD on IFC */ 264 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 265 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 266 #define CONFIG_SYS_CSPR2_EXT (0xf) 267 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 268 | CSPR_PORT_SIZE_8 \ 269 | CSPR_MSEL_GPCM \ 270 | CSPR_V) 271 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 272 #define CONFIG_SYS_CSOR2 0x0 273 274 /* CPLD Timing parameters for IFC CS2 */ 275 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 276 FTIM0_GPCM_TEADC(0x0e) | \ 277 FTIM0_GPCM_TEAHC(0x0e)) 278 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 279 FTIM1_GPCM_TRAD(0x1f)) 280 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 281 FTIM2_GPCM_TCH(0x8) | \ 282 FTIM2_GPCM_TWP(0x1f)) 283 #define CONFIG_SYS_CS2_FTIM3 0x0 284 285 /* NAND Flash on IFC */ 286 #define CONFIG_NAND_FSL_IFC 287 #define CONFIG_SYS_NAND_BASE 0xff800000 288 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 289 290 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 291 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 292 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 293 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 294 | CSPR_V) 295 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 296 297 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 298 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 299 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 300 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 301 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 302 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 303 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 304 305 #define CONFIG_SYS_NAND_ONFI_DETECTION 306 307 /* ONFI NAND Flash mode0 Timing Params */ 308 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 309 FTIM0_NAND_TWP(0x18) | \ 310 FTIM0_NAND_TWCHT(0x07) | \ 311 FTIM0_NAND_TWH(0x0a)) 312 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 313 FTIM1_NAND_TWBE(0x39) | \ 314 FTIM1_NAND_TRR(0x0e) | \ 315 FTIM1_NAND_TRP(0x18)) 316 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 317 FTIM2_NAND_TREH(0x0a) | \ 318 FTIM2_NAND_TWHRE(0x1e)) 319 #define CONFIG_SYS_NAND_FTIM3 0x0 320 321 #define CONFIG_SYS_NAND_DDR_LAW 11 322 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 323 #define CONFIG_SYS_MAX_NAND_DEVICE 1 324 #define CONFIG_CMD_NAND 325 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 326 327 #if defined(CONFIG_NAND) 328 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 329 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 330 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 331 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 332 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 333 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 334 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 335 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 336 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 337 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 338 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 339 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 340 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 341 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 342 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 343 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 344 #else 345 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 346 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 347 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 348 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 349 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 350 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 351 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 352 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 353 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 354 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 355 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 356 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 357 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 358 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 359 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 360 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 361 #endif 362 363 #if defined(CONFIG_RAMBOOT_PBL) 364 #define CONFIG_SYS_RAMBOOT 365 #endif 366 367 #ifdef CONFIG_SPL_BUILD 368 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 369 #else 370 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 371 #endif 372 373 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 374 #define CONFIG_MISC_INIT_R 375 #define CONFIG_HWCONFIG 376 377 /* define to use L1 as initial stack */ 378 #define CONFIG_L1_INIT_RAM 379 #define CONFIG_SYS_INIT_RAM_LOCK 380 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 383 /* The assembler doesn't like typecast */ 384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 385 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 386 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 387 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 388 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 389 GENERATED_GBL_DATA_SIZE) 390 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 391 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 392 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 393 394 /* 395 * Serial Port 396 */ 397 #define CONFIG_CONS_INDEX 1 398 #define CONFIG_SYS_NS16550_SERIAL 399 #define CONFIG_SYS_NS16550_REG_SIZE 1 400 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 401 #define CONFIG_SYS_BAUDRATE_TABLE \ 402 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 403 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 404 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 405 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 406 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 407 408 /* 409 * I2C 410 */ 411 #define CONFIG_SYS_I2C 412 #define CONFIG_SYS_I2C_FSL 413 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 414 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 415 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 417 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 418 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 419 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 420 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 421 #define CONFIG_SYS_FSL_I2C_SPEED 100000 422 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 423 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 424 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 425 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 426 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 427 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 428 #define I2C_MUX_CH_DEFAULT 0x8 429 430 #define I2C_MUX_CH_VOL_MONITOR 0xa 431 432 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 433 #ifndef CONFIG_SPL_BUILD 434 #define CONFIG_VID 435 #endif 436 #define CONFIG_VOL_MONITOR_IR36021_SET 437 #define CONFIG_VOL_MONITOR_IR36021_READ 438 /* The lowest and highest voltage allowed for T208xRDB */ 439 #define VDD_MV_MIN 819 440 #define VDD_MV_MAX 1212 441 442 /* 443 * RapidIO 444 */ 445 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 446 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 447 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 448 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 449 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 450 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 451 /* 452 * for slave u-boot IMAGE instored in master memory space, 453 * PHYS must be aligned based on the SIZE 454 */ 455 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 456 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 457 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 458 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 459 /* 460 * for slave UCODE and ENV instored in master memory space, 461 * PHYS must be aligned based on the SIZE 462 */ 463 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 464 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 465 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 466 467 /* slave core release by master*/ 468 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 469 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 470 471 /* 472 * SRIO_PCIE_BOOT - SLAVE 473 */ 474 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 475 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 476 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 477 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 478 #endif 479 480 /* 481 * eSPI - Enhanced SPI 482 */ 483 #ifdef CONFIG_SPI_FLASH 484 #define CONFIG_SPI_FLASH_BAR 485 #define CONFIG_SF_DEFAULT_SPEED 10000000 486 #define CONFIG_SF_DEFAULT_MODE 0 487 #endif 488 489 /* 490 * General PCI 491 * Memory space is mapped 1-1, but I/O space must start from 0. 492 */ 493 #define CONFIG_PCI /* Enable PCI/PCIE */ 494 #define CONFIG_PCIE1 /* PCIE controller 1 */ 495 #define CONFIG_PCIE2 /* PCIE controller 2 */ 496 #define CONFIG_PCIE3 /* PCIE controller 3 */ 497 #define CONFIG_PCIE4 /* PCIE controller 4 */ 498 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 499 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 500 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 501 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 502 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 503 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 504 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 505 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 506 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 507 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 508 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 509 510 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 511 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 512 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 513 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 514 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 515 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 516 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 517 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 518 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 519 520 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 521 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 522 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 523 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 524 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 525 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 526 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 527 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 528 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 529 530 /* controller 4, Base address 203000 */ 531 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 532 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 533 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 534 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 535 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 536 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 537 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 538 539 #ifdef CONFIG_PCI 540 #define CONFIG_PCI_INDIRECT_BRIDGE 541 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 542 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 543 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 544 #define CONFIG_DOS_PARTITION 545 #endif 546 547 /* Qman/Bman */ 548 #ifndef CONFIG_NOBQFMAN 549 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 550 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 551 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 552 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 553 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 554 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 555 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 556 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 557 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 558 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 559 CONFIG_SYS_BMAN_CENA_SIZE) 560 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 561 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 562 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 563 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 564 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 565 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 566 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 567 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 568 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 569 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 570 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 571 CONFIG_SYS_QMAN_CENA_SIZE) 572 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 573 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 574 575 #define CONFIG_SYS_DPAA_FMAN 576 #define CONFIG_SYS_DPAA_PME 577 #define CONFIG_SYS_PMAN 578 #define CONFIG_SYS_DPAA_DCE 579 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 580 #define CONFIG_SYS_INTERLAKEN 581 582 /* Default address of microcode for the Linux Fman driver */ 583 #if defined(CONFIG_SPIFLASH) 584 /* 585 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 586 * env, so we got 0x110000. 587 */ 588 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 589 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 590 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 591 #define CONFIG_CORTINA_FW_ADDR 0x120000 592 593 #elif defined(CONFIG_SDCARD) 594 /* 595 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 596 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 597 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 598 */ 599 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 600 #define CONFIG_SYS_CORTINA_FW_IN_MMC 601 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 602 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 603 604 #elif defined(CONFIG_NAND) 605 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 606 #define CONFIG_SYS_CORTINA_FW_IN_NAND 607 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 608 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 609 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 610 /* 611 * Slave has no ucode locally, it can fetch this from remote. When implementing 612 * in two corenet boards, slave's ucode could be stored in master's memory 613 * space, the address can be mapped from slave TLB->slave LAW-> 614 * slave SRIO or PCIE outbound window->master inbound window-> 615 * master LAW->the ucode address in master's memory space. 616 */ 617 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 618 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 619 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 620 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 621 #else 622 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 623 #define CONFIG_SYS_CORTINA_FW_IN_NOR 624 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 625 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 626 #endif 627 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 628 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 629 #endif /* CONFIG_NOBQFMAN */ 630 631 #ifdef CONFIG_SYS_DPAA_FMAN 632 #define CONFIG_FMAN_ENET 633 #define CONFIG_PHYLIB_10G 634 #define CONFIG_PHY_AQUANTIA 635 #define CONFIG_PHY_CORTINA 636 #define CONFIG_PHY_REALTEK 637 #define CONFIG_CORTINA_FW_LENGTH 0x40000 638 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 639 #define RGMII_PHY2_ADDR 0x02 640 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 641 #define CORTINA_PHY_ADDR2 0x0d 642 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 643 #define FM1_10GEC4_PHY_ADDR 0x01 644 #endif 645 646 #ifdef CONFIG_FMAN_ENET 647 #define CONFIG_MII /* MII PHY management */ 648 #define CONFIG_ETHPRIME "FM1@DTSEC3" 649 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 650 #endif 651 652 /* 653 * SATA 654 */ 655 #ifdef CONFIG_FSL_SATA_V2 656 #define CONFIG_LIBATA 657 #define CONFIG_FSL_SATA 658 #define CONFIG_SYS_SATA_MAX_DEVICE 2 659 #define CONFIG_SATA1 660 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 661 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 662 #define CONFIG_SATA2 663 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 664 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 665 #define CONFIG_LBA48 666 #define CONFIG_CMD_SATA 667 #define CONFIG_DOS_PARTITION 668 #endif 669 670 /* 671 * USB 672 */ 673 #ifdef CONFIG_USB_EHCI 674 #define CONFIG_USB_EHCI_FSL 675 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 676 #define CONFIG_HAS_FSL_DR_USB 677 #endif 678 679 /* 680 * SDHC 681 */ 682 #ifdef CONFIG_MMC 683 #define CONFIG_FSL_ESDHC 684 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 685 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 686 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 687 #define CONFIG_GENERIC_MMC 688 #define CONFIG_DOS_PARTITION 689 #endif 690 691 /* 692 * Dynamic MTD Partition support with mtdparts 693 */ 694 #ifndef CONFIG_SYS_NO_FLASH 695 #define CONFIG_MTD_DEVICE 696 #define CONFIG_MTD_PARTITIONS 697 #define CONFIG_CMD_MTDPARTS 698 #define CONFIG_FLASH_CFI_MTD 699 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 700 "spi0=spife110000.1" 701 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 702 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 703 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 704 "1m(uboot),5m(kernel),128k(dtb),-(user)" 705 #endif 706 707 /* 708 * Environment 709 */ 710 711 /* 712 * Command line configuration. 713 */ 714 #define CONFIG_CMD_ERRATA 715 #define CONFIG_CMD_REGINFO 716 717 #ifdef CONFIG_PCI 718 #define CONFIG_CMD_PCI 719 #endif 720 721 /* Hash command with SHA acceleration supported in hardware */ 722 #ifdef CONFIG_FSL_CAAM 723 #define CONFIG_CMD_HASH 724 #define CONFIG_SHA_HW_ACCEL 725 #endif 726 727 /* 728 * Miscellaneous configurable options 729 */ 730 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 731 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 732 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 733 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 734 #ifdef CONFIG_CMD_KGDB 735 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 736 #else 737 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 738 #endif 739 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 740 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 741 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 742 743 /* 744 * For booting Linux, the board info and command line data 745 * have to be in the first 64 MB of memory, since this is 746 * the maximum mapped by the Linux kernel during initialization. 747 */ 748 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 749 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 750 751 #ifdef CONFIG_CMD_KGDB 752 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 753 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 754 #endif 755 756 /* 757 * Environment Configuration 758 */ 759 #define CONFIG_ROOTPATH "/opt/nfsroot" 760 #define CONFIG_BOOTFILE "uImage" 761 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 762 763 /* default location for tftp and bootm */ 764 #define CONFIG_LOADADDR 1000000 765 #define CONFIG_BAUDRATE 115200 766 #define __USB_PHY_TYPE utmi 767 768 #define CONFIG_EXTRA_ENV_SETTINGS \ 769 "hwconfig=fsl_ddr:" \ 770 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 771 "bank_intlv=auto;" \ 772 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 773 "netdev=eth0\0" \ 774 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 775 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 776 "tftpflash=tftpboot $loadaddr $uboot && " \ 777 "protect off $ubootaddr +$filesize && " \ 778 "erase $ubootaddr +$filesize && " \ 779 "cp.b $loadaddr $ubootaddr $filesize && " \ 780 "protect on $ubootaddr +$filesize && " \ 781 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 782 "consoledev=ttyS0\0" \ 783 "ramdiskaddr=2000000\0" \ 784 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 785 "fdtaddr=1e00000\0" \ 786 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 787 "bdev=sda3\0" 788 789 /* 790 * For emulation this causes u-boot to jump to the start of the 791 * proof point app code automatically 792 */ 793 #define CONFIG_PROOF_POINTS \ 794 "setenv bootargs root=/dev/$bdev rw " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "cpu 1 release 0x29000000 - - -;" \ 797 "cpu 2 release 0x29000000 - - -;" \ 798 "cpu 3 release 0x29000000 - - -;" \ 799 "cpu 4 release 0x29000000 - - -;" \ 800 "cpu 5 release 0x29000000 - - -;" \ 801 "cpu 6 release 0x29000000 - - -;" \ 802 "cpu 7 release 0x29000000 - - -;" \ 803 "go 0x29000000" 804 805 #define CONFIG_HVBOOT \ 806 "setenv bootargs config-addr=0x60000000; " \ 807 "bootm 0x01000000 - 0x00f00000" 808 809 #define CONFIG_ALU \ 810 "setenv bootargs root=/dev/$bdev rw " \ 811 "console=$consoledev,$baudrate $othbootargs;" \ 812 "cpu 1 release 0x01000000 - - -;" \ 813 "cpu 2 release 0x01000000 - - -;" \ 814 "cpu 3 release 0x01000000 - - -;" \ 815 "cpu 4 release 0x01000000 - - -;" \ 816 "cpu 5 release 0x01000000 - - -;" \ 817 "cpu 6 release 0x01000000 - - -;" \ 818 "cpu 7 release 0x01000000 - - -;" \ 819 "go 0x01000000" 820 821 #define CONFIG_LINUX \ 822 "setenv bootargs root=/dev/ram rw " \ 823 "console=$consoledev,$baudrate $othbootargs;" \ 824 "setenv ramdiskaddr 0x02000000;" \ 825 "setenv fdtaddr 0x00c00000;" \ 826 "setenv loadaddr 0x1000000;" \ 827 "bootm $loadaddr $ramdiskaddr $fdtaddr" 828 829 #define CONFIG_HDBOOT \ 830 "setenv bootargs root=/dev/$bdev rw " \ 831 "console=$consoledev,$baudrate $othbootargs;" \ 832 "tftp $loadaddr $bootfile;" \ 833 "tftp $fdtaddr $fdtfile;" \ 834 "bootm $loadaddr - $fdtaddr" 835 836 #define CONFIG_NFSBOOTCOMMAND \ 837 "setenv bootargs root=/dev/nfs rw " \ 838 "nfsroot=$serverip:$rootpath " \ 839 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 840 "console=$consoledev,$baudrate $othbootargs;" \ 841 "tftp $loadaddr $bootfile;" \ 842 "tftp $fdtaddr $fdtfile;" \ 843 "bootm $loadaddr - $fdtaddr" 844 845 #define CONFIG_RAMBOOTCOMMAND \ 846 "setenv bootargs root=/dev/ram rw " \ 847 "console=$consoledev,$baudrate $othbootargs;" \ 848 "tftp $ramdiskaddr $ramdiskfile;" \ 849 "tftp $loadaddr $bootfile;" \ 850 "tftp $fdtaddr $fdtfile;" \ 851 "bootm $loadaddr $ramdiskaddr $fdtaddr" 852 853 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 854 855 #include <asm/fsl_secure_boot.h> 856 857 #endif /* __T2080RDB_H */ 858