xref: /rk3399_rockchip-uboot/include/configs/cgtqmx6eval.h (revision 77d2f7f5070c7def29d433096f4cee57eeddbd23)
1 /*
2  *
3  * Congatec Conga-QEVAl board configuration file.
4  *
5  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6  * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8  * Leo Sartre, <lsartre@adeneo-embedded.com>
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
15 
16 #include "mx6_common.h"
17 
18 #define CONFIG_MACH_TYPE	4122
19 
20 #ifdef CONFIG_SPL
21 #define CONFIG_SPL_MMC_SUPPORT
22 #define CONFIG_SPL_SPI_SUPPORT
23 #define CONFIG_SPL_SPI_FLASH_SUPPORT
24 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
25 #define CONFIG_SPL_SPI_LOAD
26 #include "imx6_spl.h"
27 #endif
28 
29 /* Size of malloc() pool */
30 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
31 
32 #define CONFIG_BOARD_EARLY_INIT_F
33 #define CONFIG_BOARD_LATE_INIT
34 #define CONFIG_MISC_INIT_R
35 
36 #define CONFIG_MXC_UART
37 #define CONFIG_MXC_UART_BASE	       UART2_BASE
38 
39 /* MMC Configs */
40 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
41 
42 /* SPI NOR */
43 #define CONFIG_SPI_FLASH
44 #define CONFIG_SPI_FLASH_STMICRO
45 #define CONFIG_SPI_FLASH_SST
46 #define CONFIG_MXC_SPI
47 #define CONFIG_SF_DEFAULT_BUS		0
48 #define CONFIG_SF_DEFAULT_SPEED		20000000
49 #define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
50 
51 /* Miscellaneous commands */
52 #define CONFIG_CMD_BMODE
53 
54 /* Thermal support */
55 #define CONFIG_IMX_THERMAL
56 
57 /* I2C Configs */
58 #define CONFIG_SYS_I2C
59 #define CONFIG_SYS_I2C_MXC
60 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
61 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
62 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
63 #define CONFIG_SYS_I2C_SPEED		  100000
64 
65 /* PMIC */
66 #define CONFIG_POWER
67 #define CONFIG_POWER_I2C
68 #define CONFIG_POWER_PFUZE100
69 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
70 
71 /* USB Configs */
72 #define CONFIG_USB_EHCI
73 #define CONFIG_USB_EHCI_MX6
74 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
75 #define CONFIG_USB_HOST_ETHER
76 #define CONFIG_USB_ETHER_ASIX
77 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
78 #define CONFIG_MXC_USB_FLAGS	0
79 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
80 #define CONFIG_USB_KEYBOARD
81 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
82 
83 #define CONFIG_USBD_HS
84 
85 #define CONFIG_USB_FUNCTION_MASS_STORAGE
86 
87 /* USB Device Firmware Update support */
88 #define CONFIG_USB_FUNCTION_DFU
89 #define CONFIG_DFU_MMC
90 #define CONFIG_DFU_SF
91 
92 #define CONFIG_USB_FUNCTION_FASTBOOT
93 #define CONFIG_CMD_FASTBOOT
94 #define CONFIG_ANDROID_BOOT_IMAGE
95 #define CONFIG_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
96 #define CONFIG_FASTBOOT_BUF_SIZE   0x07000000
97 
98 /* Framebuffer */
99 #define CONFIG_VIDEO
100 #define CONFIG_VIDEO_IPUV3
101 #define CONFIG_CFB_CONSOLE
102 #define CONFIG_VGA_AS_SINGLE_DEVICE
103 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
104 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
105 #define CONFIG_VIDEO_BMP_RLE8
106 #define CONFIG_SPLASH_SCREEN
107 #define CONFIG_SPLASH_SCREEN_ALIGN
108 #define CONFIG_BMP_16BPP
109 #define CONFIG_VIDEO_LOGO
110 #define CONFIG_VIDEO_BMP_LOGO
111 #ifdef CONFIG_MX6DL
112 #define CONFIG_IPUV3_CLK 198000000
113 #else
114 #define CONFIG_IPUV3_CLK 264000000
115 #endif
116 #define CONFIG_IMX_HDMI
117 
118 /* SATA */
119 #define CONFIG_CMD_SATA
120 #define CONFIG_DWC_AHSATA
121 #define CONFIG_SYS_SATA_MAX_DEVICE	1
122 #define CONFIG_DWC_AHSATA_PORT_ID	0
123 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
124 #define CONFIG_LBA48
125 #define CONFIG_LIBATA
126 
127 /* Ethernet */
128 #define CONFIG_FEC_MXC
129 #define CONFIG_MII
130 #define IMX_FEC_BASE			ENET_BASE_ADDR
131 #define CONFIG_FEC_XCV_TYPE		RGMII
132 #define CONFIG_ETHPRIME			"FEC"
133 #define CONFIG_FEC_MXC_PHYADDR		6
134 #define CONFIG_PHYLIB
135 #define CONFIG_PHY_ATHEROS
136 
137 /* Command definition */
138 
139 #define CONFIG_MXC_UART_BASE	UART2_BASE
140 #define CONFIG_CONSOLE_DEV	"ttymxc1"
141 #define CONFIG_MMCROOT		"/dev/mmcblk0p2"
142 #define CONFIG_SYS_MMC_ENV_DEV		0
143 
144 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
145 #define CONFIG_EXTRA_ENV_SETTINGS \
146 	"script=boot.scr\0" \
147 	"image=zImage\0" \
148 	"fdtfile=undefined\0" \
149 	"fdt_addr_r=0x18000000\0" \
150 	"boot_fdt=try\0" \
151 	"ip_dyn=yes\0" \
152 	"console=" CONFIG_CONSOLE_DEV "\0" \
153 	"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
154 	"dfu_alt_info_spl=spl raw 0x400\0" \
155 	"dfu_alt_info_img=u-boot raw 0x10000\0" \
156 	"dfu_alt_info=spl raw 0x400\0" \
157 	"bootm_size=0x10000000\0" \
158 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
159 	"mmcpart=1\0" \
160 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
161 	"update_sd_firmware=" \
162 		"if test ${ip_dyn} = yes; then " \
163 			"setenv get_cmd dhcp; " \
164 		"else " \
165 			"setenv get_cmd tftp; " \
166 		"fi; " \
167 		"if mmc dev ${mmcdev}; then "	\
168 			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
169 				"setexpr fw_sz ${filesize} / 0x200; " \
170 				"setexpr fw_sz ${fw_sz} + 1; "	\
171 				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
172 			"fi; "	\
173 		"fi\0" \
174 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
175 		"root=${mmcroot}\0" \
176 	"loadbootscript=" \
177 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
178 	"bootscript=echo Running bootscript from mmc ...; " \
179 		"source\0" \
180 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
181 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
182 	"mmcboot=echo Booting from mmc ...; " \
183 		"run mmcargs; " \
184 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
185 			"if run loadfdt; then " \
186 				"bootz ${loadaddr} - ${fdt_addr_r}; " \
187 			"else " \
188 				"if test ${boot_fdt} = try; then " \
189 					"bootz; " \
190 				"else " \
191 					"echo WARN: Cannot load the DT; " \
192 				"fi; " \
193 			"fi; " \
194 		"else " \
195 			"bootz; " \
196 		"fi;\0" \
197 	"findfdt="\
198 		"if test $board_rev = MX6Q ; then " \
199 			"setenv fdtfile imx6q-qmx6.dtb; fi; " \
200 		"if test $board_rev = MX6DL ; then " \
201 			"setenv fdtfile imx6dl-qmx6.dtb; fi; " \
202 		"if test $fdtfile = undefined; then " \
203 			"echo WARNING: Could not determine dtb to use; fi; \0" \
204 	"netargs=setenv bootargs console=${console},${baudrate} " \
205 		"root=/dev/nfs " \
206 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
207 	"netboot=echo Booting from net ...; " \
208 		"run netargs; " \
209 		"if test ${ip_dyn} = yes; then " \
210 			"setenv get_cmd dhcp; " \
211 		"else " \
212 			"setenv get_cmd tftp; " \
213 		"fi; " \
214 		"${get_cmd} ${image}; " \
215 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
216 			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
217 				"bootz ${loadaddr} - ${fdt_addr_r}; " \
218 			"else " \
219 				"if test ${boot_fdt} = try; then " \
220 					"bootz; " \
221 				"else " \
222 					"echo WARN: Cannot load the DT; " \
223 				"fi; " \
224 			"fi; " \
225 		"else " \
226 			"bootz; " \
227 		"fi;\0" \
228 	"spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
229 
230 #define CONFIG_BOOTCOMMAND \
231 	"run spilock;"	    \
232 	"run findfdt; "	\
233 	"mmc dev ${mmcdev};" \
234 	"if mmc rescan; then " \
235 		"if run loadbootscript; then " \
236 		"run bootscript; " \
237 		"else " \
238 			"if run loadimage; then " \
239 				"run mmcboot; " \
240 			"else run netboot; " \
241 			"fi; " \
242 		"fi; " \
243 	"else run netboot; fi"
244 
245 #define CONFIG_SYS_MEMTEST_START       0x10000000
246 #define CONFIG_SYS_MEMTEST_END	       0x10010000
247 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
248 
249 /* Physical Memory Map */
250 #define CONFIG_NR_DRAM_BANKS	       1
251 #define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
252 
253 #define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
254 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
255 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
256 
257 #define CONFIG_SYS_INIT_SP_OFFSET \
258 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
259 #define CONFIG_SYS_INIT_SP_ADDR \
260 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
261 
262 /* Environment organization */
263 #if defined (CONFIG_ENV_IS_IN_MMC)
264 #define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
265 #define CONFIG_SYS_MMC_ENV_DEV		0
266 #endif
267 
268 #define CONFIG_ENV_SIZE			(8 * 1024)
269 
270 #define CONFIG_ENV_IS_IN_SPI_FLASH
271 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
272 #define CONFIG_ENV_OFFSET		(768 * 1024)
273 #define CONFIG_ENV_SECT_SIZE		(64 * 1024)
274 #define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
275 #define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
276 #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
277 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
278 #endif
279 
280 #endif			       /* __CONFIG_CGTQMX6EVAL_H */
281