1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #include <asm/config_mpc85xx.h> 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 21 #ifndef CONFIG_SECURE_BOOT 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #else 24 #define CONFIG_SYS_FSL_PBL_PBI \ 25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 26 #endif 27 28 #ifdef CONFIG_T1040RDB 29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 30 #endif 31 #ifdef CONFIG_T1042RDB_PI 32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 33 #endif 34 #ifdef CONFIG_T1042RDB 35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 36 #endif 37 #ifdef CONFIG_T1040D4RDB 38 #define CONFIG_SYS_FSL_PBL_RCW \ 39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 40 #endif 41 #ifdef CONFIG_T1042D4RDB 42 #define CONFIG_SYS_FSL_PBL_RCW \ 43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 44 #endif 45 46 #define CONFIG_SPL_SERIAL_SUPPORT 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 #define CONFIG_SYS_TEXT_BASE 0x30001000 51 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 52 #define CONFIG_SPL_PAD_TO 0x40000 53 #define CONFIG_SPL_MAX_SIZE 0x28000 54 #ifdef CONFIG_SPL_BUILD 55 #define CONFIG_SPL_SKIP_RELOCATE 56 #define CONFIG_SPL_COMMON_INIT_DDR 57 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 58 #define CONFIG_SYS_NO_FLASH 59 #endif 60 #define RESET_VECTOR_OFFSET 0x27FFC 61 #define BOOT_PAGE_OFFSET 0x27000 62 63 #ifdef CONFIG_NAND 64 #ifdef CONFIG_SECURE_BOOT 65 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 66 /* 67 * HDR would be appended at end of image and copied to DDR along 68 * with U-Boot image. 69 */ 70 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 71 CONFIG_U_BOOT_HDR_SIZE) 72 #else 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 74 #endif 75 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 76 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 77 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 78 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 79 #define CONFIG_SPL_NAND_BOOT 80 #endif 81 82 #ifdef CONFIG_SPIFLASH 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 84 #define CONFIG_SPL_SPI_SUPPORT 85 #define CONFIG_SPL_SPI_FLASH_SUPPORT 86 #define CONFIG_SPL_SPI_FLASH_MINIMAL 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 91 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 92 #ifndef CONFIG_SPL_BUILD 93 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 94 #endif 95 #define CONFIG_SPL_SPI_BOOT 96 #endif 97 98 #ifdef CONFIG_SDCARD 99 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 100 #define CONFIG_SPL_MMC_MINIMAL 101 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 102 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 103 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 104 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 105 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 106 #ifndef CONFIG_SPL_BUILD 107 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 108 #endif 109 #define CONFIG_SPL_MMC_BOOT 110 #endif 111 112 #endif 113 114 /* High Level Configuration Options */ 115 #define CONFIG_BOOKE 116 #define CONFIG_E500MC /* BOOKE e500mc family */ 117 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 118 #define CONFIG_MP /* support multiple processors */ 119 120 /* support deep sleep */ 121 #define CONFIG_DEEP_SLEEP 122 #if defined(CONFIG_DEEP_SLEEP) 123 #define CONFIG_BOARD_EARLY_INIT_F 124 #define CONFIG_SILENT_CONSOLE 125 #endif 126 127 #ifndef CONFIG_SYS_TEXT_BASE 128 #define CONFIG_SYS_TEXT_BASE 0xeff40000 129 #endif 130 131 #ifndef CONFIG_RESET_VECTOR_ADDRESS 132 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 133 #endif 134 135 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 136 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 137 #define CONFIG_FSL_IFC /* Enable IFC Support */ 138 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 139 #define CONFIG_PCI /* Enable PCI/PCIE */ 140 #define CONFIG_PCI_INDIRECT_BRIDGE 141 #define CONFIG_PCIE1 /* PCIE controller 1 */ 142 #define CONFIG_PCIE2 /* PCIE controller 2 */ 143 #define CONFIG_PCIE3 /* PCIE controller 3 */ 144 #define CONFIG_PCIE4 /* PCIE controller 4 */ 145 146 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 147 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 148 149 #define CONFIG_FSL_LAW /* Use common FSL init code */ 150 151 #define CONFIG_ENV_OVERWRITE 152 153 #ifndef CONFIG_SYS_NO_FLASH 154 #define CONFIG_FLASH_CFI_DRIVER 155 #define CONFIG_SYS_FLASH_CFI 156 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 157 #endif 158 159 #if defined(CONFIG_SPIFLASH) 160 #define CONFIG_SYS_EXTRA_ENV_RELOC 161 #define CONFIG_ENV_IS_IN_SPI_FLASH 162 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 163 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 164 #define CONFIG_ENV_SECT_SIZE 0x10000 165 #elif defined(CONFIG_SDCARD) 166 #define CONFIG_SYS_EXTRA_ENV_RELOC 167 #define CONFIG_ENV_IS_IN_MMC 168 #define CONFIG_SYS_MMC_ENV_DEV 0 169 #define CONFIG_ENV_SIZE 0x2000 170 #define CONFIG_ENV_OFFSET (512 * 0x800) 171 #elif defined(CONFIG_NAND) 172 #ifdef CONFIG_SECURE_BOOT 173 #define CONFIG_RAMBOOT_NAND 174 #define CONFIG_BOOTSCRIPT_COPY_RAM 175 #endif 176 #define CONFIG_SYS_EXTRA_ENV_RELOC 177 #define CONFIG_ENV_IS_IN_NAND 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 180 #else 181 #define CONFIG_ENV_IS_IN_FLASH 182 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 183 #define CONFIG_ENV_SIZE 0x2000 184 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 185 #endif 186 187 #define CONFIG_SYS_CLK_FREQ 100000000 188 #define CONFIG_DDR_CLK_FREQ 66666666 189 190 /* 191 * These can be toggled for performance analysis, otherwise use default. 192 */ 193 #define CONFIG_SYS_CACHE_STASHING 194 #define CONFIG_BACKSIDE_L2_CACHE 195 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 196 #define CONFIG_BTB /* toggle branch predition */ 197 #define CONFIG_DDR_ECC 198 #ifdef CONFIG_DDR_ECC 199 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 200 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 201 #endif 202 203 #define CONFIG_ENABLE_36BIT_PHYS 204 205 #define CONFIG_ADDR_MAP 206 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 207 208 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 209 #define CONFIG_SYS_MEMTEST_END 0x00400000 210 #define CONFIG_SYS_ALT_MEMTEST 211 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 212 213 /* 214 * Config the L3 Cache as L3 SRAM 215 */ 216 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 217 /* 218 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 219 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 220 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 221 */ 222 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 223 #define CONFIG_SYS_L3_SIZE 256 << 10 224 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 225 #ifdef CONFIG_RAMBOOT_PBL 226 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 227 #endif 228 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 229 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 230 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 231 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 232 233 #define CONFIG_SYS_DCSRBAR 0xf0000000 234 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 235 236 /* 237 * DDR Setup 238 */ 239 #define CONFIG_VERY_BIG_RAM 240 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 241 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 242 243 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 244 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 245 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 246 247 #define CONFIG_DDR_SPD 248 #ifndef CONFIG_SYS_FSL_DDR4 249 #define CONFIG_SYS_FSL_DDR3 250 #endif 251 252 #define CONFIG_SYS_SPD_BUS_NUM 0 253 #define SPD_EEPROM_ADDRESS 0x51 254 255 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 256 257 /* 258 * IFC Definitions 259 */ 260 #define CONFIG_SYS_FLASH_BASE 0xe8000000 261 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 262 263 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 264 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 265 CSPR_PORT_SIZE_16 | \ 266 CSPR_MSEL_NOR | \ 267 CSPR_V) 268 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 269 270 /* 271 * TDM Definition 272 */ 273 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 274 275 /* NOR Flash Timing Params */ 276 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 277 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 278 FTIM0_NOR_TEADC(0x5) | \ 279 FTIM0_NOR_TEAHC(0x5)) 280 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 281 FTIM1_NOR_TRAD_NOR(0x1A) |\ 282 FTIM1_NOR_TSEQRAD_NOR(0x13)) 283 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 284 FTIM2_NOR_TCH(0x4) | \ 285 FTIM2_NOR_TWPH(0x0E) | \ 286 FTIM2_NOR_TWP(0x1c)) 287 #define CONFIG_SYS_NOR_FTIM3 0x0 288 289 #define CONFIG_SYS_FLASH_QUIET_TEST 290 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 291 292 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 293 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 294 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 295 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 296 297 #define CONFIG_SYS_FLASH_EMPTY_INFO 298 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 299 300 /* CPLD on IFC */ 301 #define CPLD_LBMAP_MASK 0x3F 302 #define CPLD_BANK_SEL_MASK 0x07 303 #define CPLD_BANK_OVERRIDE 0x40 304 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 305 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 306 #define CPLD_LBMAP_RESET 0xFF 307 #define CPLD_LBMAP_SHIFT 0x03 308 309 #if defined(CONFIG_T1042RDB_PI) 310 #define CPLD_DIU_SEL_DFP 0x80 311 #elif defined(CONFIG_T1042D4RDB) 312 #define CPLD_DIU_SEL_DFP 0xc0 313 #endif 314 315 #if defined(CONFIG_T1040D4RDB) 316 #define CPLD_INT_MASK_ALL 0xFF 317 #define CPLD_INT_MASK_THERM 0x80 318 #define CPLD_INT_MASK_DVI_DFP 0x40 319 #define CPLD_INT_MASK_QSGMII1 0x20 320 #define CPLD_INT_MASK_QSGMII2 0x10 321 #define CPLD_INT_MASK_SGMI1 0x08 322 #define CPLD_INT_MASK_SGMI2 0x04 323 #define CPLD_INT_MASK_TDMR1 0x02 324 #define CPLD_INT_MASK_TDMR2 0x01 325 #endif 326 327 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 328 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 329 #define CONFIG_SYS_CSPR2_EXT (0xf) 330 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 331 | CSPR_PORT_SIZE_8 \ 332 | CSPR_MSEL_GPCM \ 333 | CSPR_V) 334 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 335 #define CONFIG_SYS_CSOR2 0x0 336 /* CPLD Timing parameters for IFC CS2 */ 337 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 338 FTIM0_GPCM_TEADC(0x0e) | \ 339 FTIM0_GPCM_TEAHC(0x0e)) 340 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 341 FTIM1_GPCM_TRAD(0x1f)) 342 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 343 FTIM2_GPCM_TCH(0x8) | \ 344 FTIM2_GPCM_TWP(0x1f)) 345 #define CONFIG_SYS_CS2_FTIM3 0x0 346 347 /* NAND Flash on IFC */ 348 #define CONFIG_NAND_FSL_IFC 349 #define CONFIG_SYS_NAND_BASE 0xff800000 350 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 351 352 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 353 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 354 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 355 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 356 | CSPR_V) 357 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 358 359 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 360 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 361 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 362 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 363 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 364 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 365 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 366 367 #define CONFIG_SYS_NAND_ONFI_DETECTION 368 369 /* ONFI NAND Flash mode0 Timing Params */ 370 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 371 FTIM0_NAND_TWP(0x18) | \ 372 FTIM0_NAND_TWCHT(0x07) | \ 373 FTIM0_NAND_TWH(0x0a)) 374 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 375 FTIM1_NAND_TWBE(0x39) | \ 376 FTIM1_NAND_TRR(0x0e) | \ 377 FTIM1_NAND_TRP(0x18)) 378 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 379 FTIM2_NAND_TREH(0x0a) | \ 380 FTIM2_NAND_TWHRE(0x1e)) 381 #define CONFIG_SYS_NAND_FTIM3 0x0 382 383 #define CONFIG_SYS_NAND_DDR_LAW 11 384 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 385 #define CONFIG_SYS_MAX_NAND_DEVICE 1 386 #define CONFIG_CMD_NAND 387 388 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 389 390 #if defined(CONFIG_NAND) 391 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 392 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 393 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 394 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 395 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 396 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 397 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 398 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 399 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 400 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 401 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 402 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 403 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 404 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 405 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 406 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 407 #else 408 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 409 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 410 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 411 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 412 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 413 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 414 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 415 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 416 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 417 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 418 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 419 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 420 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 421 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 422 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 423 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 424 #endif 425 426 #ifdef CONFIG_SPL_BUILD 427 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 428 #else 429 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 430 #endif 431 432 #if defined(CONFIG_RAMBOOT_PBL) 433 #define CONFIG_SYS_RAMBOOT 434 #endif 435 436 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 437 #if defined(CONFIG_NAND) 438 #define CONFIG_A008044_WORKAROUND 439 #endif 440 #endif 441 442 #define CONFIG_BOARD_EARLY_INIT_R 443 #define CONFIG_MISC_INIT_R 444 445 #define CONFIG_HWCONFIG 446 447 /* define to use L1 as initial stack */ 448 #define CONFIG_L1_INIT_RAM 449 #define CONFIG_SYS_INIT_RAM_LOCK 450 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 453 /* The assembler doesn't like typecast */ 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 455 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 456 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 457 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 458 459 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 460 GENERATED_GBL_DATA_SIZE) 461 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 462 463 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 464 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 465 466 /* Serial Port - controlled on board with jumper J8 467 * open - index 2 468 * shorted - index 1 469 */ 470 #define CONFIG_CONS_INDEX 1 471 #define CONFIG_SYS_NS16550_SERIAL 472 #define CONFIG_SYS_NS16550_REG_SIZE 1 473 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 474 475 #define CONFIG_SYS_BAUDRATE_TABLE \ 476 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 477 478 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 479 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 480 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 481 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 482 #ifndef CONFIG_SPL_BUILD 483 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 484 #endif 485 486 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 487 /* Video */ 488 #define CONFIG_FSL_DIU_FB 489 490 #ifdef CONFIG_FSL_DIU_FB 491 #define CONFIG_FSL_DIU_CH7301 492 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 493 #define CONFIG_VIDEO 494 #define CONFIG_CMD_BMP 495 #define CONFIG_CFB_CONSOLE 496 #define CONFIG_CFB_CONSOLE_ANSI 497 #define CONFIG_VIDEO_SW_CURSOR 498 #define CONFIG_VGA_AS_SINGLE_DEVICE 499 #define CONFIG_VIDEO_LOGO 500 #define CONFIG_VIDEO_BMP_LOGO 501 #endif 502 #endif 503 504 /* I2C */ 505 #define CONFIG_SYS_I2C 506 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 507 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 508 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 509 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 510 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 511 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 512 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 513 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 514 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 515 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 516 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 517 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 518 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 519 520 /* I2C bus multiplexer */ 521 #define I2C_MUX_PCA_ADDR 0x70 522 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 523 #define I2C_MUX_CH_DEFAULT 0x8 524 #endif 525 526 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 527 /* LDI/DVI Encoder for display */ 528 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 529 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 530 531 /* 532 * RTC configuration 533 */ 534 #define RTC 535 #define CONFIG_RTC_DS1337 1 536 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 537 538 /*DVI encoder*/ 539 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 540 #endif 541 542 /* 543 * eSPI - Enhanced SPI 544 */ 545 #define CONFIG_SPI_FLASH_BAR 546 #define CONFIG_SF_DEFAULT_SPEED 10000000 547 #define CONFIG_SF_DEFAULT_MODE 0 548 #define CONFIG_ENV_SPI_BUS 0 549 #define CONFIG_ENV_SPI_CS 0 550 #define CONFIG_ENV_SPI_MAX_HZ 10000000 551 #define CONFIG_ENV_SPI_MODE 0 552 553 /* 554 * General PCI 555 * Memory space is mapped 1-1, but I/O space must start from 0. 556 */ 557 558 #ifdef CONFIG_PCI 559 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 560 #ifdef CONFIG_PCIE1 561 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 562 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 563 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 564 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 565 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 566 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 567 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 568 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 569 #endif 570 571 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 572 #ifdef CONFIG_PCIE2 573 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 574 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 575 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 576 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 577 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 578 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 579 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 580 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 581 #endif 582 583 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 584 #ifdef CONFIG_PCIE3 585 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 586 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 587 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 588 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 589 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 590 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 591 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 592 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 593 #endif 594 595 /* controller 4, Base address 203000 */ 596 #ifdef CONFIG_PCIE4 597 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 598 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 599 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 600 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 601 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 602 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 603 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 604 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 605 #endif 606 607 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 608 609 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 610 #define CONFIG_DOS_PARTITION 611 #endif /* CONFIG_PCI */ 612 613 /* SATA */ 614 #define CONFIG_FSL_SATA_V2 615 #ifdef CONFIG_FSL_SATA_V2 616 #define CONFIG_LIBATA 617 #define CONFIG_FSL_SATA 618 619 #define CONFIG_SYS_SATA_MAX_DEVICE 1 620 #define CONFIG_SATA1 621 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 622 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 623 624 #define CONFIG_LBA48 625 #define CONFIG_CMD_SATA 626 #define CONFIG_DOS_PARTITION 627 #endif 628 629 /* 630 * USB 631 */ 632 #define CONFIG_HAS_FSL_DR_USB 633 634 #ifdef CONFIG_HAS_FSL_DR_USB 635 #define CONFIG_USB_EHCI 636 637 #ifdef CONFIG_USB_EHCI 638 #define CONFIG_USB_EHCI_FSL 639 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 640 #endif 641 #endif 642 643 #define CONFIG_MMC 644 645 #ifdef CONFIG_MMC 646 #define CONFIG_FSL_ESDHC 647 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 648 #define CONFIG_GENERIC_MMC 649 #define CONFIG_DOS_PARTITION 650 #endif 651 652 /* Qman/Bman */ 653 #ifndef CONFIG_NOBQFMAN 654 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 655 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 656 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 657 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 658 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 659 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 660 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 661 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 662 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 663 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 664 CONFIG_SYS_BMAN_CENA_SIZE) 665 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 666 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 667 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 668 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 669 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 670 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 671 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 672 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 673 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 674 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 675 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 676 CONFIG_SYS_QMAN_CENA_SIZE) 677 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 678 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 679 680 #define CONFIG_SYS_DPAA_FMAN 681 #define CONFIG_SYS_DPAA_PME 682 683 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 684 #define CONFIG_QE 685 #define CONFIG_U_QE 686 #endif 687 688 /* Default address of microcode for the Linux Fman driver */ 689 #if defined(CONFIG_SPIFLASH) 690 /* 691 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 692 * env, so we got 0x110000. 693 */ 694 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 695 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 696 #elif defined(CONFIG_SDCARD) 697 /* 698 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 699 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 700 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 701 */ 702 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 703 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 704 #elif defined(CONFIG_NAND) 705 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 706 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 707 #else 708 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 709 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 710 #endif 711 712 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 713 #if defined(CONFIG_SPIFLASH) 714 #define CONFIG_SYS_QE_FW_ADDR 0x130000 715 #elif defined(CONFIG_SDCARD) 716 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 717 #elif defined(CONFIG_NAND) 718 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 719 #else 720 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 721 #endif 722 #endif 723 724 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 725 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 726 #endif /* CONFIG_NOBQFMAN */ 727 728 #ifdef CONFIG_SYS_DPAA_FMAN 729 #define CONFIG_FMAN_ENET 730 #define CONFIG_PHY_VITESSE 731 #define CONFIG_PHY_REALTEK 732 #endif 733 734 #ifdef CONFIG_FMAN_ENET 735 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 736 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 737 #elif defined(CONFIG_T1040D4RDB) 738 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 739 #elif defined(CONFIG_T1042D4RDB) 740 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 741 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 742 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 743 #endif 744 745 #ifdef CONFIG_T104XD4RDB 746 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 747 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 748 #else 749 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 750 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 751 #endif 752 753 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 754 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 755 #define CONFIG_VSC9953 756 #define CONFIG_CMD_ETHSW 757 #ifdef CONFIG_T1040RDB 758 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 759 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 760 #else 761 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 762 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 763 #endif 764 #endif 765 766 #define CONFIG_MII /* MII PHY management */ 767 #define CONFIG_ETHPRIME "FM1@DTSEC4" 768 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 769 #endif 770 771 /* 772 * Environment 773 */ 774 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 775 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 776 777 /* 778 * Command line configuration. 779 */ 780 #ifdef CONFIG_T1042RDB_PI 781 #define CONFIG_CMD_DATE 782 #endif 783 #define CONFIG_CMD_ERRATA 784 #define CONFIG_CMD_IRQ 785 #define CONFIG_CMD_REGINFO 786 787 #ifdef CONFIG_PCI 788 #define CONFIG_CMD_PCI 789 #endif 790 791 /* Hash command with SHA acceleration supported in hardware */ 792 #ifdef CONFIG_FSL_CAAM 793 #define CONFIG_CMD_HASH 794 #define CONFIG_SHA_HW_ACCEL 795 #endif 796 797 /* 798 * Miscellaneous configurable options 799 */ 800 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 801 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 802 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 803 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 804 #ifdef CONFIG_CMD_KGDB 805 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 806 #else 807 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 808 #endif 809 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 810 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 811 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 812 813 /* 814 * For booting Linux, the board info and command line data 815 * have to be in the first 64 MB of memory, since this is 816 * the maximum mapped by the Linux kernel during initialization. 817 */ 818 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 819 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 820 821 #ifdef CONFIG_CMD_KGDB 822 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 823 #endif 824 825 /* 826 * Dynamic MTD Partition support with mtdparts 827 */ 828 #ifndef CONFIG_SYS_NO_FLASH 829 #define CONFIG_MTD_DEVICE 830 #define CONFIG_MTD_PARTITIONS 831 #define CONFIG_CMD_MTDPARTS 832 #define CONFIG_FLASH_CFI_MTD 833 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 834 "spi0=spife110000.0" 835 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 836 "128k(dtb),96m(fs),-(user);"\ 837 "fff800000.flash:2m(uboot),9m(kernel),"\ 838 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 839 "2m(uboot),9m(kernel),128k(dtb),-(user)" 840 #endif 841 842 /* 843 * Environment Configuration 844 */ 845 #define CONFIG_ROOTPATH "/opt/nfsroot" 846 #define CONFIG_BOOTFILE "uImage" 847 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 848 849 /* default location for tftp and bootm */ 850 #define CONFIG_LOADADDR 1000000 851 852 853 #define CONFIG_BAUDRATE 115200 854 855 #define __USB_PHY_TYPE utmi 856 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 857 858 #ifdef CONFIG_T1040RDB 859 #define FDTFILE "t1040rdb/t1040rdb.dtb" 860 #elif defined(CONFIG_T1042RDB_PI) 861 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 862 #elif defined(CONFIG_T1042RDB) 863 #define FDTFILE "t1042rdb/t1042rdb.dtb" 864 #elif defined(CONFIG_T1040D4RDB) 865 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 866 #elif defined(CONFIG_T1042D4RDB) 867 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 868 #endif 869 870 #ifdef CONFIG_FSL_DIU_FB 871 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 872 #else 873 #define DIU_ENVIRONMENT 874 #endif 875 876 #define CONFIG_EXTRA_ENV_SETTINGS \ 877 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 878 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 879 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 880 "netdev=eth0\0" \ 881 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 882 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 883 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 884 "tftpflash=tftpboot $loadaddr $uboot && " \ 885 "protect off $ubootaddr +$filesize && " \ 886 "erase $ubootaddr +$filesize && " \ 887 "cp.b $loadaddr $ubootaddr $filesize && " \ 888 "protect on $ubootaddr +$filesize && " \ 889 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 890 "consoledev=ttyS0\0" \ 891 "ramdiskaddr=2000000\0" \ 892 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 893 "fdtaddr=1e00000\0" \ 894 "fdtfile=" __stringify(FDTFILE) "\0" \ 895 "bdev=sda3\0" 896 897 #define CONFIG_LINUX \ 898 "setenv bootargs root=/dev/ram rw " \ 899 "console=$consoledev,$baudrate $othbootargs;" \ 900 "setenv ramdiskaddr 0x02000000;" \ 901 "setenv fdtaddr 0x00c00000;" \ 902 "setenv loadaddr 0x1000000;" \ 903 "bootm $loadaddr $ramdiskaddr $fdtaddr" 904 905 #define CONFIG_HDBOOT \ 906 "setenv bootargs root=/dev/$bdev rw " \ 907 "console=$consoledev,$baudrate $othbootargs;" \ 908 "tftp $loadaddr $bootfile;" \ 909 "tftp $fdtaddr $fdtfile;" \ 910 "bootm $loadaddr - $fdtaddr" 911 912 #define CONFIG_NFSBOOTCOMMAND \ 913 "setenv bootargs root=/dev/nfs rw " \ 914 "nfsroot=$serverip:$rootpath " \ 915 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 916 "console=$consoledev,$baudrate $othbootargs;" \ 917 "tftp $loadaddr $bootfile;" \ 918 "tftp $fdtaddr $fdtfile;" \ 919 "bootm $loadaddr - $fdtaddr" 920 921 #define CONFIG_RAMBOOTCOMMAND \ 922 "setenv bootargs root=/dev/ram rw " \ 923 "console=$consoledev,$baudrate $othbootargs;" \ 924 "tftp $ramdiskaddr $ramdiskfile;" \ 925 "tftp $loadaddr $bootfile;" \ 926 "tftp $fdtaddr $fdtfile;" \ 927 "bootm $loadaddr $ramdiskaddr $fdtaddr" 928 929 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 930 931 #include <asm/fsl_secure_boot.h> 932 933 #endif /* __CONFIG_H */ 934