1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_DEEP_SLEEP 36 #if defined(CONFIG_DEEP_SLEEP) 37 #define CONFIG_SILENT_CONSOLE 38 #define CONFIG_BOARD_EARLY_INIT_F 39 #endif 40 41 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 #define CONFIG_SYS_TEXT_BASE 0x00201000 52 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 53 #define CONFIG_SPL_PAD_TO 0x40000 54 #define CONFIG_SPL_MAX_SIZE 0x28000 55 #define RESET_VECTOR_OFFSET 0x27FFC 56 #define BOOT_PAGE_OFFSET 0x27000 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_SKIP_RELOCATE 59 #define CONFIG_SPL_COMMON_INIT_DDR 60 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 61 #define CONFIG_SYS_NO_FLASH 62 #endif 63 64 #ifdef CONFIG_NAND 65 #define CONFIG_SPL_NAND_SUPPORT 66 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 67 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 68 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 69 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 71 #define CONFIG_SPL_NAND_BOOT 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 76 #define CONFIG_SPL_SPI_SUPPORT 77 #define CONFIG_SPL_SPI_FLASH_SUPPORT 78 #define CONFIG_SPL_SPI_FLASH_MINIMAL 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 84 #ifndef CONFIG_SPL_BUILD 85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 86 #endif 87 #define CONFIG_SPL_SPI_BOOT 88 #endif 89 90 #ifdef CONFIG_SDCARD 91 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 92 #define CONFIG_SPL_MMC_MINIMAL 93 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 94 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 95 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 96 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 97 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 98 #ifndef CONFIG_SPL_BUILD 99 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 100 #endif 101 #define CONFIG_SPL_MMC_BOOT 102 #endif 103 104 #endif /* CONFIG_RAMBOOT_PBL */ 105 106 #ifndef CONFIG_SYS_TEXT_BASE 107 #define CONFIG_SYS_TEXT_BASE 0xeff40000 108 #endif 109 110 #ifndef CONFIG_RESET_VECTOR_ADDRESS 111 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 112 #endif 113 114 #ifndef CONFIG_SYS_NO_FLASH 115 #define CONFIG_FLASH_CFI_DRIVER 116 #define CONFIG_SYS_FLASH_CFI 117 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 118 #endif 119 120 /* PCIe Boot - Master */ 121 #define CONFIG_SRIO_PCIE_BOOT_MASTER 122 /* 123 * for slave u-boot IMAGE instored in master memory space, 124 * PHYS must be aligned based on the SIZE 125 */ 126 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 128 #ifdef CONFIG_PHYS_64BIT 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 131 #else 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 134 #endif 135 /* 136 * for slave UCODE and ENV instored in master memory space, 137 * PHYS must be aligned based on the SIZE 138 */ 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 142 #else 143 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 145 #endif 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 147 /* slave core release by master*/ 148 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 149 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 150 151 /* PCIe Boot - Slave */ 152 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 153 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 154 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 155 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 156 /* Set 1M boot space for PCIe boot */ 157 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 159 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 160 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 161 #define CONFIG_SYS_NO_FLASH 162 #endif 163 164 #if defined(CONFIG_SPIFLASH) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_SPI_FLASH 167 #define CONFIG_ENV_SPI_BUS 0 168 #define CONFIG_ENV_SPI_CS 0 169 #define CONFIG_ENV_SPI_MAX_HZ 10000000 170 #define CONFIG_ENV_SPI_MODE 0 171 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 172 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 173 #define CONFIG_ENV_SECT_SIZE 0x10000 174 #elif defined(CONFIG_SDCARD) 175 #define CONFIG_SYS_EXTRA_ENV_RELOC 176 #define CONFIG_ENV_IS_IN_MMC 177 #define CONFIG_SYS_MMC_ENV_DEV 0 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_OFFSET (512 * 0x800) 180 #elif defined(CONFIG_NAND) 181 #define CONFIG_SYS_EXTRA_ENV_RELOC 182 #define CONFIG_ENV_IS_IN_NAND 183 #define CONFIG_ENV_SIZE 0x2000 184 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 185 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 186 #define CONFIG_ENV_IS_IN_REMOTE 187 #define CONFIG_ENV_ADDR 0xffe20000 188 #define CONFIG_ENV_SIZE 0x2000 189 #elif defined(CONFIG_ENV_IS_NOWHERE) 190 #define CONFIG_ENV_SIZE 0x2000 191 #else 192 #define CONFIG_ENV_IS_IN_FLASH 193 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 194 #define CONFIG_ENV_SIZE 0x2000 195 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 196 #endif 197 198 #ifndef __ASSEMBLY__ 199 unsigned long get_board_sys_clk(void); 200 unsigned long get_board_ddr_clk(void); 201 #endif 202 203 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 204 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 205 206 /* 207 * These can be toggled for performance analysis, otherwise use default. 208 */ 209 #define CONFIG_SYS_CACHE_STASHING 210 #define CONFIG_BACKSIDE_L2_CACHE 211 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 212 #define CONFIG_BTB /* toggle branch predition */ 213 #define CONFIG_DDR_ECC 214 #ifdef CONFIG_DDR_ECC 215 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 216 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 217 #endif 218 219 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 220 #define CONFIG_SYS_MEMTEST_END 0x00400000 221 #define CONFIG_SYS_ALT_MEMTEST 222 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 223 224 /* 225 * Config the L3 Cache as L3 SRAM 226 */ 227 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 228 #define CONFIG_SYS_L3_SIZE (256 << 10) 229 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 230 #ifdef CONFIG_RAMBOOT_PBL 231 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 232 #endif 233 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 234 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 235 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 236 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 237 238 #ifdef CONFIG_PHYS_64BIT 239 #define CONFIG_SYS_DCSRBAR 0xf0000000 240 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 241 #endif 242 243 /* EEPROM */ 244 #define CONFIG_ID_EEPROM 245 #define CONFIG_SYS_I2C_EEPROM_NXID 246 #define CONFIG_SYS_EEPROM_BUS_NUM 0 247 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 248 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 251 252 /* 253 * DDR Setup 254 */ 255 #define CONFIG_VERY_BIG_RAM 256 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 257 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 258 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 259 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 260 #define CONFIG_DDR_SPD 261 #ifndef CONFIG_SYS_FSL_DDR4 262 #define CONFIG_SYS_FSL_DDR3 263 #endif 264 265 #define CONFIG_SYS_SPD_BUS_NUM 0 266 #define SPD_EEPROM_ADDRESS 0x51 267 268 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 269 270 /* 271 * IFC Definitions 272 */ 273 #define CONFIG_SYS_FLASH_BASE 0xe0000000 274 #ifdef CONFIG_PHYS_64BIT 275 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 276 #else 277 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 278 #endif 279 280 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 281 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 282 + 0x8000000) | \ 283 CSPR_PORT_SIZE_16 | \ 284 CSPR_MSEL_NOR | \ 285 CSPR_V) 286 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 287 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 288 CSPR_PORT_SIZE_16 | \ 289 CSPR_MSEL_NOR | \ 290 CSPR_V) 291 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 292 /* NOR Flash Timing Params */ 293 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 294 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 295 FTIM0_NOR_TEADC(0x5) | \ 296 FTIM0_NOR_TEAHC(0x5)) 297 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 298 FTIM1_NOR_TRAD_NOR(0x1A) |\ 299 FTIM1_NOR_TSEQRAD_NOR(0x13)) 300 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 301 FTIM2_NOR_TCH(0x4) | \ 302 FTIM2_NOR_TWPH(0x0E) | \ 303 FTIM2_NOR_TWP(0x1c)) 304 #define CONFIG_SYS_NOR_FTIM3 0x0 305 306 #define CONFIG_SYS_FLASH_QUIET_TEST 307 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 308 309 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 310 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 311 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 312 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 313 314 #define CONFIG_SYS_FLASH_EMPTY_INFO 315 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 316 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 317 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 318 #define QIXIS_BASE 0xffdf0000 319 #ifdef CONFIG_PHYS_64BIT 320 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 321 #else 322 #define QIXIS_BASE_PHYS QIXIS_BASE 323 #endif 324 #define QIXIS_LBMAP_SWITCH 0x06 325 #define QIXIS_LBMAP_MASK 0x0f 326 #define QIXIS_LBMAP_SHIFT 0 327 #define QIXIS_LBMAP_DFLTBANK 0x00 328 #define QIXIS_LBMAP_ALTBANK 0x04 329 #define QIXIS_RST_CTL_RESET 0x31 330 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 331 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 332 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 333 #define QIXIS_RST_FORCE_MEM 0x01 334 335 #define CONFIG_SYS_CSPR3_EXT (0xf) 336 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 337 | CSPR_PORT_SIZE_8 \ 338 | CSPR_MSEL_GPCM \ 339 | CSPR_V) 340 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 341 #define CONFIG_SYS_CSOR3 0x0 342 /* QIXIS Timing parameters for IFC CS3 */ 343 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 344 FTIM0_GPCM_TEADC(0x0e) | \ 345 FTIM0_GPCM_TEAHC(0x0e)) 346 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 347 FTIM1_GPCM_TRAD(0x3f)) 348 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 349 FTIM2_GPCM_TCH(0x8) | \ 350 FTIM2_GPCM_TWP(0x1f)) 351 #define CONFIG_SYS_CS3_FTIM3 0x0 352 353 #define CONFIG_NAND_FSL_IFC 354 #define CONFIG_SYS_NAND_BASE 0xff800000 355 #ifdef CONFIG_PHYS_64BIT 356 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 357 #else 358 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 359 #endif 360 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 361 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 362 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 363 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 364 | CSPR_V) 365 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 366 367 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 368 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 369 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 370 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 371 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 372 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 373 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 374 375 #define CONFIG_SYS_NAND_ONFI_DETECTION 376 377 /* ONFI NAND Flash mode0 Timing Params */ 378 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 379 FTIM0_NAND_TWP(0x18) | \ 380 FTIM0_NAND_TWCHT(0x07) | \ 381 FTIM0_NAND_TWH(0x0a)) 382 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 383 FTIM1_NAND_TWBE(0x39) | \ 384 FTIM1_NAND_TRR(0x0e) | \ 385 FTIM1_NAND_TRP(0x18)) 386 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 387 FTIM2_NAND_TREH(0x0a) | \ 388 FTIM2_NAND_TWHRE(0x1e)) 389 #define CONFIG_SYS_NAND_FTIM3 0x0 390 391 #define CONFIG_SYS_NAND_DDR_LAW 11 392 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 393 #define CONFIG_SYS_MAX_NAND_DEVICE 1 394 #define CONFIG_CMD_NAND 395 396 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 397 398 #if defined(CONFIG_NAND) 399 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 407 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 408 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 409 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 410 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 411 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 412 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 413 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 414 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 415 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 416 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 417 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 418 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 419 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 420 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 421 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 422 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 423 #else 424 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 425 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 426 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 427 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 428 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 429 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 430 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 431 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 432 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 433 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 434 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 435 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 436 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 437 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 438 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 439 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 440 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 441 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 442 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 443 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 444 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 445 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 446 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 447 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 448 #endif 449 450 #ifdef CONFIG_SPL_BUILD 451 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 452 #else 453 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 454 #endif 455 456 #if defined(CONFIG_RAMBOOT_PBL) 457 #define CONFIG_SYS_RAMBOOT 458 #endif 459 460 #define CONFIG_BOARD_EARLY_INIT_R 461 #define CONFIG_MISC_INIT_R 462 463 #define CONFIG_HWCONFIG 464 465 /* define to use L1 as initial stack */ 466 #define CONFIG_L1_INIT_RAM 467 #define CONFIG_SYS_INIT_RAM_LOCK 468 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 472 /* The assembler doesn't like typecast */ 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 474 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 475 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 476 #else 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 480 #endif 481 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 482 483 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 484 GENERATED_GBL_DATA_SIZE) 485 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 486 487 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 488 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 489 490 /* Serial Port */ 491 #define CONFIG_CONS_INDEX 1 492 #define CONFIG_SYS_NS16550_SERIAL 493 #define CONFIG_SYS_NS16550_REG_SIZE 1 494 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 495 496 #define CONFIG_SYS_BAUDRATE_TABLE \ 497 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 498 499 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 500 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 501 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 502 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 503 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 504 505 /* Video */ 506 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 507 #define CONFIG_FSL_DIU_FB 508 #ifdef CONFIG_FSL_DIU_FB 509 #define CONFIG_FSL_DIU_CH7301 510 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 511 #define CONFIG_VIDEO 512 #define CONFIG_CMD_BMP 513 #define CONFIG_CFB_CONSOLE 514 #define CONFIG_VIDEO_SW_CURSOR 515 #define CONFIG_VGA_AS_SINGLE_DEVICE 516 #define CONFIG_VIDEO_LOGO 517 #define CONFIG_VIDEO_BMP_LOGO 518 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 519 /* 520 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 521 * disable empty flash sector detection, which is I/O-intensive. 522 */ 523 #undef CONFIG_SYS_FLASH_EMPTY_INFO 524 #endif 525 #endif 526 527 /* I2C */ 528 #define CONFIG_SYS_I2C 529 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 530 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 531 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 532 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 533 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 534 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 535 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 536 537 #define I2C_MUX_PCA_ADDR 0x77 538 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 539 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 540 #define I2C_RETIMER_ADDR 0x18 541 542 /* I2C bus multiplexer */ 543 #define I2C_MUX_CH_DEFAULT 0x8 544 #define I2C_MUX_CH_DIU 0xC 545 #define I2C_MUX_CH5 0xD 546 #define I2C_MUX_CH7 0xF 547 548 /* LDI/DVI Encoder for display */ 549 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 550 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 551 552 /* 553 * RTC configuration 554 */ 555 #define RTC 556 #define CONFIG_RTC_DS3231 1 557 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 558 559 /* 560 * eSPI - Enhanced SPI 561 */ 562 #ifndef CONFIG_SPL_BUILD 563 #endif 564 #define CONFIG_SPI_FLASH_BAR 565 #define CONFIG_SF_DEFAULT_SPEED 10000000 566 #define CONFIG_SF_DEFAULT_MODE 0 567 568 /* 569 * General PCIe 570 * Memory space is mapped 1-1, but I/O space must start from 0. 571 */ 572 #define CONFIG_PCI /* Enable PCI/PCIE */ 573 #define CONFIG_PCIE1 /* PCIE controller 1 */ 574 #define CONFIG_PCIE2 /* PCIE controller 2 */ 575 #define CONFIG_PCIE3 /* PCIE controller 3 */ 576 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 577 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 578 #define CONFIG_PCI_INDIRECT_BRIDGE 579 580 #ifdef CONFIG_PCI 581 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 582 #ifdef CONFIG_PCIE1 583 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 584 #ifdef CONFIG_PHYS_64BIT 585 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 586 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 587 #else 588 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 589 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 590 #endif 591 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 592 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 593 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 594 #ifdef CONFIG_PHYS_64BIT 595 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 596 #else 597 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 598 #endif 599 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 600 #endif 601 602 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 603 #ifdef CONFIG_PCIE2 604 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 605 #ifdef CONFIG_PHYS_64BIT 606 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 607 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 608 #else 609 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 610 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 611 #endif 612 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 613 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 614 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 615 #ifdef CONFIG_PHYS_64BIT 616 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 617 #else 618 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 619 #endif 620 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 621 #endif 622 623 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 624 #ifdef CONFIG_PCIE3 625 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 626 #ifdef CONFIG_PHYS_64BIT 627 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 628 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 629 #else 630 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 631 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 632 #endif 633 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 634 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 635 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 636 #ifdef CONFIG_PHYS_64BIT 637 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 638 #else 639 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 640 #endif 641 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 642 #endif 643 644 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 645 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 646 #define CONFIG_DOS_PARTITION 647 #endif /* CONFIG_PCI */ 648 649 /* 650 *SATA 651 */ 652 #define CONFIG_FSL_SATA_V2 653 #ifdef CONFIG_FSL_SATA_V2 654 #define CONFIG_LIBATA 655 #define CONFIG_FSL_SATA 656 #define CONFIG_SYS_SATA_MAX_DEVICE 1 657 #define CONFIG_SATA1 658 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 659 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 660 #define CONFIG_LBA48 661 #define CONFIG_CMD_SATA 662 #define CONFIG_DOS_PARTITION 663 #endif 664 665 /* 666 * USB 667 */ 668 #define CONFIG_HAS_FSL_DR_USB 669 670 #ifdef CONFIG_HAS_FSL_DR_USB 671 #define CONFIG_USB_EHCI 672 #define CONFIG_USB_EHCI_FSL 673 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 674 #endif 675 676 /* 677 * SDHC 678 */ 679 #define CONFIG_MMC 680 #ifdef CONFIG_MMC 681 #define CONFIG_FSL_ESDHC 682 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 683 #define CONFIG_GENERIC_MMC 684 #define CONFIG_DOS_PARTITION 685 #endif 686 687 /* Qman/Bman */ 688 #ifndef CONFIG_NOBQFMAN 689 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 690 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 691 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 692 #ifdef CONFIG_PHYS_64BIT 693 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 694 #else 695 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 696 #endif 697 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 698 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 699 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 700 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 701 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 702 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 703 CONFIG_SYS_BMAN_CENA_SIZE) 704 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 705 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 706 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 707 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 708 #ifdef CONFIG_PHYS_64BIT 709 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 710 #else 711 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 712 #endif 713 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 714 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 715 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 716 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 717 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 718 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 719 CONFIG_SYS_QMAN_CENA_SIZE) 720 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 721 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 722 723 #define CONFIG_SYS_DPAA_FMAN 724 725 #define CONFIG_QE 726 #define CONFIG_U_QE 727 /* Default address of microcode for the Linux FMan driver */ 728 #if defined(CONFIG_SPIFLASH) 729 /* 730 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 731 * env, so we got 0x110000. 732 */ 733 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 734 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 735 #define CONFIG_SYS_QE_FW_ADDR 0x130000 736 #elif defined(CONFIG_SDCARD) 737 /* 738 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 739 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 740 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 741 */ 742 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 743 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 744 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 745 #elif defined(CONFIG_NAND) 746 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 747 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 748 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 749 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 750 /* 751 * Slave has no ucode locally, it can fetch this from remote. When implementing 752 * in two corenet boards, slave's ucode could be stored in master's memory 753 * space, the address can be mapped from slave TLB->slave LAW-> 754 * slave SRIO or PCIE outbound window->master inbound window-> 755 * master LAW->the ucode address in master's memory space. 756 */ 757 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 758 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 759 #else 760 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 761 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 762 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 763 #endif 764 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 765 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 766 #endif /* CONFIG_NOBQFMAN */ 767 768 #ifdef CONFIG_SYS_DPAA_FMAN 769 #define CONFIG_FMAN_ENET 770 #define CONFIG_PHYLIB_10G 771 #define CONFIG_PHY_VITESSE 772 #define CONFIG_PHY_REALTEK 773 #define CONFIG_PHY_TERANETICS 774 #define RGMII_PHY1_ADDR 0x1 775 #define RGMII_PHY2_ADDR 0x2 776 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 777 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 778 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 779 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 780 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 781 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 782 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 783 #endif 784 785 #ifdef CONFIG_FMAN_ENET 786 #define CONFIG_MII /* MII PHY management */ 787 #define CONFIG_ETHPRIME "FM1@DTSEC4" 788 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 789 #endif 790 791 /* 792 * Dynamic MTD Partition support with mtdparts 793 */ 794 #ifndef CONFIG_SYS_NO_FLASH 795 #define CONFIG_MTD_DEVICE 796 #define CONFIG_MTD_PARTITIONS 797 #define CONFIG_CMD_MTDPARTS 798 #define CONFIG_FLASH_CFI_MTD 799 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 800 "spi0=spife110000.0" 801 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 802 "128k(dtb),96m(fs),-(user);"\ 803 "fff800000.flash:2m(uboot),9m(kernel),"\ 804 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 805 "2m(uboot),9m(kernel),128k(dtb),-(user)" 806 #endif 807 808 /* 809 * Environment 810 */ 811 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 812 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 813 814 /* 815 * Command line configuration. 816 */ 817 #define CONFIG_CMD_DATE 818 #define CONFIG_CMD_EEPROM 819 #define CONFIG_CMD_ERRATA 820 #define CONFIG_CMD_IRQ 821 #define CONFIG_CMD_REGINFO 822 823 #ifdef CONFIG_PCI 824 #define CONFIG_CMD_PCI 825 #endif 826 827 /* 828 * Miscellaneous configurable options 829 */ 830 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 831 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 832 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 833 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 834 #ifdef CONFIG_CMD_KGDB 835 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 836 #else 837 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 838 #endif 839 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 840 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 841 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 842 843 /* 844 * For booting Linux, the board info and command line data 845 * have to be in the first 64 MB of memory, since this is 846 * the maximum mapped by the Linux kernel during initialization. 847 */ 848 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 849 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 850 851 #ifdef CONFIG_CMD_KGDB 852 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 853 #endif 854 855 /* 856 * Environment Configuration 857 */ 858 #define CONFIG_ROOTPATH "/opt/nfsroot" 859 #define CONFIG_BOOTFILE "uImage" 860 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 861 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 862 #define CONFIG_BAUDRATE 115200 863 #define __USB_PHY_TYPE utmi 864 865 #define CONFIG_EXTRA_ENV_SETTINGS \ 866 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 867 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 868 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 869 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 870 "fdtfile=t1024qds/t1024qds.dtb\0" \ 871 "netdev=eth0\0" \ 872 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 873 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 874 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 875 "tftpflash=tftpboot $loadaddr $uboot && " \ 876 "protect off $ubootaddr +$filesize && " \ 877 "erase $ubootaddr +$filesize && " \ 878 "cp.b $loadaddr $ubootaddr $filesize && " \ 879 "protect on $ubootaddr +$filesize && " \ 880 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 881 "consoledev=ttyS0\0" \ 882 "ramdiskaddr=2000000\0" \ 883 "fdtaddr=d00000\0" \ 884 "bdev=sda3\0" 885 886 #define CONFIG_LINUX \ 887 "setenv bootargs root=/dev/ram rw " \ 888 "console=$consoledev,$baudrate $othbootargs;" \ 889 "setenv ramdiskaddr 0x02000000;" \ 890 "setenv fdtaddr 0x00c00000;" \ 891 "setenv loadaddr 0x1000000;" \ 892 "bootm $loadaddr $ramdiskaddr $fdtaddr" 893 894 #define CONFIG_NFSBOOTCOMMAND \ 895 "setenv bootargs root=/dev/nfs rw " \ 896 "nfsroot=$serverip:$rootpath " \ 897 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 898 "console=$consoledev,$baudrate $othbootargs;" \ 899 "tftp $loadaddr $bootfile;" \ 900 "tftp $fdtaddr $fdtfile;" \ 901 "bootm $loadaddr - $fdtaddr" 902 903 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 904 905 /* Hash command with SHA acceleration supported in hardware */ 906 #ifdef CONFIG_FSL_CAAM 907 #define CONFIG_CMD_HASH 908 #define CONFIG_SHA_HW_ACCEL 909 #endif 910 911 #include <asm/fsl_secure_boot.h> 912 913 #endif /* __T1024QDS_H */ 914