1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 23 #define CONFIG_SPL_SERIAL_SUPPORT 24 #define CONFIG_SPL_MMC_SUPPORT 25 #define CONFIG_SPL_MMC_MINIMAL 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 28 #define CONFIG_FSL_LAW /* Use common FSL init code */ 29 #define CONFIG_SYS_TEXT_BASE 0x11001000 30 #define CONFIG_SPL_TEXT_BASE 0xD0001000 31 #define CONFIG_SPL_PAD_TO 0x18000 32 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 33 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 34 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 35 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 36 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 38 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 39 #define CONFIG_SPL_MMC_BOOT 40 #ifdef CONFIG_SPL_BUILD 41 #define CONFIG_SPL_COMMON_INIT_DDR 42 #endif 43 #endif 44 45 #ifdef CONFIG_SPIFLASH 46 #ifdef CONFIG_SECURE_BOOT 47 #define CONFIG_RAMBOOT_SPIFLASH 48 #define CONFIG_SYS_TEXT_BASE 0x11000000 49 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 50 #else 51 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 52 #define CONFIG_SPL_SERIAL_SUPPORT 53 #define CONFIG_SPL_SPI_SUPPORT 54 #define CONFIG_SPL_SPI_FLASH_SUPPORT 55 #define CONFIG_SPL_SPI_FLASH_MINIMAL 56 #define CONFIG_SPL_FLUSH_IMAGE 57 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 58 #define CONFIG_FSL_LAW /* Use common FSL init code */ 59 #define CONFIG_SYS_TEXT_BASE 0x11001000 60 #define CONFIG_SPL_TEXT_BASE 0xD0001000 61 #define CONFIG_SPL_PAD_TO 0x18000 62 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 67 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 68 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 69 #define CONFIG_SPL_SPI_BOOT 70 #ifdef CONFIG_SPL_BUILD 71 #define CONFIG_SPL_COMMON_INIT_DDR 72 #endif 73 #endif 74 #endif 75 76 #ifdef CONFIG_NAND 77 #ifdef CONFIG_SECURE_BOOT 78 #define CONFIG_SPL_INIT_MINIMAL 79 #define CONFIG_SPL_SERIAL_SUPPORT 80 #define CONFIG_SPL_NAND_SUPPORT 81 #define CONFIG_SPL_NAND_BOOT 82 #define CONFIG_SPL_FLUSH_IMAGE 83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 84 85 #define CONFIG_SYS_TEXT_BASE 0x00201000 86 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 87 #define CONFIG_SPL_MAX_SIZE 8192 88 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 89 #define CONFIG_SPL_RELOC_STACK 0x00100000 90 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 91 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 92 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 93 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 95 #else 96 #ifdef CONFIG_TPL_BUILD 97 #define CONFIG_SPL_NAND_BOOT 98 #define CONFIG_SPL_FLUSH_IMAGE 99 #define CONFIG_SPL_NAND_INIT 100 #define CONFIG_TPL_SERIAL_SUPPORT 101 #define CONFIG_TPL_NAND_SUPPORT 102 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 103 #define CONFIG_SPL_COMMON_INIT_DDR 104 #define CONFIG_SPL_MAX_SIZE (128 << 10) 105 #define CONFIG_SPL_TEXT_BASE 0xD0001000 106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 107 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 108 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 109 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 110 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 111 #elif defined(CONFIG_SPL_BUILD) 112 #define CONFIG_SPL_INIT_MINIMAL 113 #define CONFIG_SPL_SERIAL_SUPPORT 114 #define CONFIG_SPL_NAND_SUPPORT 115 #define CONFIG_SPL_NAND_MINIMAL 116 #define CONFIG_SPL_FLUSH_IMAGE 117 #define CONFIG_SPL_TEXT_BASE 0xff800000 118 #define CONFIG_SPL_MAX_SIZE 8192 119 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 120 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 121 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 122 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 123 #endif 124 #define CONFIG_SPL_PAD_TO 0x20000 125 #define CONFIG_TPL_PAD_TO 0x20000 126 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 127 #define CONFIG_SYS_TEXT_BASE 0x11001000 128 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 129 #endif 130 #endif 131 132 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 133 #define CONFIG_RAMBOOT_NAND 134 #define CONFIG_SYS_TEXT_BASE 0x11000000 135 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 136 #endif 137 138 #ifndef CONFIG_SYS_TEXT_BASE 139 #define CONFIG_SYS_TEXT_BASE 0xeff40000 140 #endif 141 142 #ifndef CONFIG_RESET_VECTOR_ADDRESS 143 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 144 #endif 145 146 #ifdef CONFIG_SPL_BUILD 147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 148 #else 149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 150 #endif 151 152 /* High Level Configuration Options */ 153 #define CONFIG_BOOKE /* BOOKE */ 154 #define CONFIG_E500 /* BOOKE e500 family */ 155 #define CONFIG_FSL_IFC /* Enable IFC Support */ 156 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 157 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 158 159 #define CONFIG_PCI /* Enable PCI/PCIE */ 160 #if defined(CONFIG_PCI) 161 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 162 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 163 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 164 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 165 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 166 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 167 168 #define CONFIG_CMD_PCI 169 170 /* 171 * PCI Windows 172 * Memory space is mapped 1-1, but I/O space must start from 0. 173 */ 174 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 175 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 176 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 177 #ifdef CONFIG_PHYS_64BIT 178 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 179 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 180 #else 181 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 182 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 183 #endif 184 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 185 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 186 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 187 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 188 #ifdef CONFIG_PHYS_64BIT 189 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 190 #else 191 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 192 #endif 193 194 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 195 #if defined(CONFIG_P1010RDB_PA) 196 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 197 #elif defined(CONFIG_P1010RDB_PB) 198 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 199 #endif 200 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 201 #ifdef CONFIG_PHYS_64BIT 202 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 203 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 204 #else 205 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 206 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 207 #endif 208 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 209 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 210 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 211 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 212 #ifdef CONFIG_PHYS_64BIT 213 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 214 #else 215 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 216 #endif 217 218 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 219 220 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 221 #define CONFIG_DOS_PARTITION 222 #endif 223 224 #define CONFIG_FSL_LAW /* Use common FSL init code */ 225 #define CONFIG_TSEC_ENET 226 #define CONFIG_ENV_OVERWRITE 227 228 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 229 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 230 231 #define CONFIG_MISC_INIT_R 232 #define CONFIG_HWCONFIG 233 /* 234 * These can be toggled for performance analysis, otherwise use default. 235 */ 236 #define CONFIG_L2_CACHE /* toggle L2 cache */ 237 #define CONFIG_BTB /* toggle branch predition */ 238 239 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 240 241 #define CONFIG_ENABLE_36BIT_PHYS 242 243 #ifdef CONFIG_PHYS_64BIT 244 #define CONFIG_ADDR_MAP 1 245 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 246 #endif 247 248 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 249 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 250 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 251 252 /* DDR Setup */ 253 #define CONFIG_SYS_FSL_DDR3 254 #define CONFIG_SYS_DDR_RAW_TIMING 255 #define CONFIG_DDR_SPD 256 #define CONFIG_SYS_SPD_BUS_NUM 1 257 #define SPD_EEPROM_ADDRESS 0x52 258 259 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 260 261 #ifndef __ASSEMBLY__ 262 extern unsigned long get_sdram_size(void); 263 #endif 264 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 265 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 266 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 267 268 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 269 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 270 271 /* DDR3 Controller Settings */ 272 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 273 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 274 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 275 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 276 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 277 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 278 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 279 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 280 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 281 #define CONFIG_SYS_DDR_RCW_1 0x00000000 282 #define CONFIG_SYS_DDR_RCW_2 0x00000000 283 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 284 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 285 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 286 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 287 288 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 289 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 290 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 291 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 292 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 293 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 294 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 295 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 296 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 297 298 /* settings for DDR3 at 667MT/s */ 299 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 300 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 301 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 302 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 303 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 304 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 305 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 306 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 307 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 308 309 #define CONFIG_SYS_CCSRBAR 0xffe00000 310 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 311 312 /* Don't relocate CCSRBAR while in NAND_SPL */ 313 #ifdef CONFIG_SPL_BUILD 314 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 315 #endif 316 317 /* 318 * Memory map 319 * 320 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 321 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 322 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 323 * 324 * Localbus non-cacheable 325 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 326 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 327 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 328 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 329 */ 330 331 /* 332 * IFC Definitions 333 */ 334 /* NOR Flash on IFC */ 335 #ifdef CONFIG_SPL_BUILD 336 #define CONFIG_SYS_NO_FLASH 337 #endif 338 339 #define CONFIG_SYS_FLASH_BASE 0xee000000 340 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 341 342 #ifdef CONFIG_PHYS_64BIT 343 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 344 #else 345 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 346 #endif 347 348 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 349 CSPR_PORT_SIZE_16 | \ 350 CSPR_MSEL_NOR | \ 351 CSPR_V) 352 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 353 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 354 /* NOR Flash Timing Params */ 355 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 356 FTIM0_NOR_TEADC(0x5) | \ 357 FTIM0_NOR_TEAHC(0x5) 358 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 359 FTIM1_NOR_TRAD_NOR(0x0f) 360 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 361 FTIM2_NOR_TCH(0x4) | \ 362 FTIM2_NOR_TWP(0x1c) 363 #define CONFIG_SYS_NOR_FTIM3 0x0 364 365 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 366 #define CONFIG_SYS_FLASH_QUIET_TEST 367 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 368 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 369 370 #undef CONFIG_SYS_FLASH_CHECKSUM 371 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 372 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 373 374 /* CFI for NOR Flash */ 375 #define CONFIG_FLASH_CFI_DRIVER 376 #define CONFIG_SYS_FLASH_CFI 377 #define CONFIG_SYS_FLASH_EMPTY_INFO 378 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 379 380 /* NAND Flash on IFC */ 381 #define CONFIG_SYS_NAND_BASE 0xff800000 382 #ifdef CONFIG_PHYS_64BIT 383 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 384 #else 385 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 386 #endif 387 388 #define CONFIG_MTD_DEVICE 389 #define CONFIG_MTD_PARTITION 390 #define CONFIG_CMD_MTDPARTS 391 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 392 #define MTDPARTS_DEFAULT \ 393 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 394 395 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 396 | CSPR_PORT_SIZE_8 \ 397 | CSPR_MSEL_NAND \ 398 | CSPR_V) 399 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 400 401 #if defined(CONFIG_P1010RDB_PA) 402 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 403 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 404 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 405 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 406 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 407 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 408 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 409 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 410 411 #elif defined(CONFIG_P1010RDB_PB) 412 #define CONFIG_SYS_NAND_ONFI_DETECTION 413 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 414 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 415 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 416 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 417 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 418 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 419 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 420 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 421 #endif 422 423 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 424 #define CONFIG_SYS_MAX_NAND_DEVICE 1 425 #define CONFIG_CMD_NAND 426 427 #if defined(CONFIG_P1010RDB_PA) 428 /* NAND Flash Timing Params */ 429 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 430 FTIM0_NAND_TWP(0x0C) | \ 431 FTIM0_NAND_TWCHT(0x04) | \ 432 FTIM0_NAND_TWH(0x05) 433 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 434 FTIM1_NAND_TWBE(0x1d) | \ 435 FTIM1_NAND_TRR(0x07) | \ 436 FTIM1_NAND_TRP(0x0c) 437 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 438 FTIM2_NAND_TREH(0x05) | \ 439 FTIM2_NAND_TWHRE(0x0f) 440 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 441 442 #elif defined(CONFIG_P1010RDB_PB) 443 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 444 /* ONFI NAND Flash mode0 Timing Params */ 445 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 446 FTIM0_NAND_TWP(0x18) | \ 447 FTIM0_NAND_TWCHT(0x07) | \ 448 FTIM0_NAND_TWH(0x0a)) 449 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 450 FTIM1_NAND_TWBE(0x39) | \ 451 FTIM1_NAND_TRR(0x0e) | \ 452 FTIM1_NAND_TRP(0x18)) 453 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 454 FTIM2_NAND_TREH(0x0a) | \ 455 FTIM2_NAND_TWHRE(0x1e)) 456 #define CONFIG_SYS_NAND_FTIM3 0x0 457 #endif 458 459 #define CONFIG_SYS_NAND_DDR_LAW 11 460 461 /* Set up IFC registers for boot location NOR/NAND */ 462 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 463 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 464 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 465 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 466 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 467 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 468 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 469 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 470 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 471 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 472 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 473 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 474 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 475 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 476 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 477 #else 478 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 479 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 480 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 481 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 482 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 483 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 484 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 485 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 486 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 487 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 488 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 489 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 490 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 491 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 492 #endif 493 494 /* CPLD on IFC */ 495 #define CONFIG_SYS_CPLD_BASE 0xffb00000 496 497 #ifdef CONFIG_PHYS_64BIT 498 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 499 #else 500 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 501 #endif 502 503 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 504 | CSPR_PORT_SIZE_8 \ 505 | CSPR_MSEL_GPCM \ 506 | CSPR_V) 507 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 508 #define CONFIG_SYS_CSOR3 0x0 509 /* CPLD Timing parameters for IFC CS3 */ 510 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 511 FTIM0_GPCM_TEADC(0x0e) | \ 512 FTIM0_GPCM_TEAHC(0x0e)) 513 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 514 FTIM1_GPCM_TRAD(0x1f)) 515 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 516 FTIM2_GPCM_TCH(0x8) | \ 517 FTIM2_GPCM_TWP(0x1f)) 518 #define CONFIG_SYS_CS3_FTIM3 0x0 519 520 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 521 defined(CONFIG_RAMBOOT_NAND) 522 #define CONFIG_SYS_RAMBOOT 523 #define CONFIG_SYS_EXTRA_ENV_RELOC 524 #else 525 #undef CONFIG_SYS_RAMBOOT 526 #endif 527 528 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 529 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 530 #define CONFIG_A003399_NOR_WORKAROUND 531 #endif 532 #endif 533 534 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 535 #define CONFIG_BOARD_EARLY_INIT_R 536 537 #define CONFIG_SYS_INIT_RAM_LOCK 538 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 539 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 540 541 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 542 - GENERATED_GBL_DATA_SIZE) 543 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 544 545 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 546 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 547 548 /* 549 * Config the L2 Cache as L2 SRAM 550 */ 551 #if defined(CONFIG_SPL_BUILD) 552 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 553 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 554 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 555 #define CONFIG_SYS_L2_SIZE (256 << 10) 556 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 557 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 558 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 559 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 560 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 561 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 562 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 563 #elif defined(CONFIG_NAND) 564 #ifdef CONFIG_TPL_BUILD 565 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 566 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 567 #define CONFIG_SYS_L2_SIZE (256 << 10) 568 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 569 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 570 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 571 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 572 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 573 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 574 #else 575 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 576 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 577 #define CONFIG_SYS_L2_SIZE (256 << 10) 578 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 579 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 580 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 581 #endif 582 #endif 583 #endif 584 585 /* Serial Port */ 586 #define CONFIG_CONS_INDEX 1 587 #undef CONFIG_SERIAL_SOFTWARE_FIFO 588 #define CONFIG_SYS_NS16550_SERIAL 589 #define CONFIG_SYS_NS16550_REG_SIZE 1 590 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 591 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 592 #define CONFIG_NS16550_MIN_FUNCTIONS 593 #endif 594 595 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 596 597 #define CONFIG_SYS_BAUDRATE_TABLE \ 598 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 599 600 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 601 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 602 603 /* I2C */ 604 #define CONFIG_SYS_I2C 605 #define CONFIG_SYS_I2C_FSL 606 #define CONFIG_SYS_FSL_I2C_SPEED 400000 607 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 608 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 609 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 610 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 611 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 612 #define I2C_PCA9557_ADDR1 0x18 613 #define I2C_PCA9557_ADDR2 0x19 614 #define I2C_PCA9557_BUS_NUM 0 615 616 /* I2C EEPROM */ 617 #if defined(CONFIG_P1010RDB_PB) 618 #define CONFIG_ID_EEPROM 619 #ifdef CONFIG_ID_EEPROM 620 #define CONFIG_SYS_I2C_EEPROM_NXID 621 #endif 622 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 623 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 624 #define CONFIG_SYS_EEPROM_BUS_NUM 0 625 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 626 #endif 627 /* enable read and write access to EEPROM */ 628 #define CONFIG_CMD_EEPROM 629 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 630 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 631 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 632 633 /* RTC */ 634 #define CONFIG_RTC_PT7C4338 635 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 636 637 /* 638 * SPI interface will not be available in case of NAND boot SPI CS0 will be 639 * used for SLIC 640 */ 641 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 642 /* eSPI - Enhanced SPI */ 643 #define CONFIG_SF_DEFAULT_SPEED 10000000 644 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 645 #endif 646 647 #if defined(CONFIG_TSEC_ENET) 648 #define CONFIG_MII /* MII PHY management */ 649 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 650 #define CONFIG_TSEC1 1 651 #define CONFIG_TSEC1_NAME "eTSEC1" 652 #define CONFIG_TSEC2 1 653 #define CONFIG_TSEC2_NAME "eTSEC2" 654 #define CONFIG_TSEC3 1 655 #define CONFIG_TSEC3_NAME "eTSEC3" 656 657 #define TSEC1_PHY_ADDR 1 658 #define TSEC2_PHY_ADDR 0 659 #define TSEC3_PHY_ADDR 2 660 661 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 662 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 663 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 664 665 #define TSEC1_PHYIDX 0 666 #define TSEC2_PHYIDX 0 667 #define TSEC3_PHYIDX 0 668 669 #define CONFIG_ETHPRIME "eTSEC1" 670 671 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 672 673 /* TBI PHY configuration for SGMII mode */ 674 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 675 TBICR_PHY_RESET \ 676 | TBICR_ANEG_ENABLE \ 677 | TBICR_FULL_DUPLEX \ 678 | TBICR_SPEED1_SET \ 679 ) 680 681 #endif /* CONFIG_TSEC_ENET */ 682 683 /* SATA */ 684 #define CONFIG_FSL_SATA 685 #define CONFIG_FSL_SATA_V2 686 #define CONFIG_LIBATA 687 688 #ifdef CONFIG_FSL_SATA 689 #define CONFIG_SYS_SATA_MAX_DEVICE 2 690 #define CONFIG_SATA1 691 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 692 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 693 #define CONFIG_SATA2 694 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 695 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 696 697 #define CONFIG_CMD_SATA 698 #define CONFIG_LBA48 699 #endif /* #ifdef CONFIG_FSL_SATA */ 700 701 #define CONFIG_MMC 702 #ifdef CONFIG_MMC 703 #define CONFIG_DOS_PARTITION 704 #define CONFIG_FSL_ESDHC 705 #define CONFIG_GENERIC_MMC 706 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 707 #endif 708 709 #define CONFIG_HAS_FSL_DR_USB 710 711 #if defined(CONFIG_HAS_FSL_DR_USB) 712 #define CONFIG_USB_EHCI 713 714 #ifdef CONFIG_USB_EHCI 715 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 716 #define CONFIG_USB_EHCI_FSL 717 #endif 718 #endif 719 720 /* 721 * Environment 722 */ 723 #if defined(CONFIG_SDCARD) 724 #define CONFIG_ENV_IS_IN_MMC 725 #define CONFIG_FSL_FIXED_MMC_LOCATION 726 #define CONFIG_SYS_MMC_ENV_DEV 0 727 #define CONFIG_ENV_SIZE 0x2000 728 #elif defined(CONFIG_SPIFLASH) 729 #define CONFIG_ENV_IS_IN_SPI_FLASH 730 #define CONFIG_ENV_SPI_BUS 0 731 #define CONFIG_ENV_SPI_CS 0 732 #define CONFIG_ENV_SPI_MAX_HZ 10000000 733 #define CONFIG_ENV_SPI_MODE 0 734 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 735 #define CONFIG_ENV_SECT_SIZE 0x10000 736 #define CONFIG_ENV_SIZE 0x2000 737 #elif defined(CONFIG_NAND) 738 #define CONFIG_ENV_IS_IN_NAND 739 #ifdef CONFIG_TPL_BUILD 740 #define CONFIG_ENV_SIZE 0x2000 741 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 742 #else 743 #if defined(CONFIG_P1010RDB_PA) 744 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 745 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 746 #elif defined(CONFIG_P1010RDB_PB) 747 #define CONFIG_ENV_SIZE (16 * 1024) 748 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 749 #endif 750 #endif 751 #define CONFIG_ENV_OFFSET (1024 * 1024) 752 #elif defined(CONFIG_SYS_RAMBOOT) 753 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 754 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 755 #define CONFIG_ENV_SIZE 0x2000 756 #else 757 #define CONFIG_ENV_IS_IN_FLASH 758 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 759 #define CONFIG_ENV_SIZE 0x2000 760 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 761 #endif 762 763 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 764 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 765 766 /* 767 * Command line configuration. 768 */ 769 #define CONFIG_CMD_DATE 770 #define CONFIG_CMD_ERRATA 771 #define CONFIG_CMD_IRQ 772 #define CONFIG_CMD_REGINFO 773 774 #undef CONFIG_WATCHDOG /* watchdog disabled */ 775 776 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 777 || defined(CONFIG_FSL_SATA) 778 #define CONFIG_DOS_PARTITION 779 #endif 780 781 /* Hash command with SHA acceleration supported in hardware */ 782 #ifdef CONFIG_FSL_CAAM 783 #define CONFIG_CMD_HASH 784 #define CONFIG_SHA_HW_ACCEL 785 #endif 786 787 /* 788 * Miscellaneous configurable options 789 */ 790 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 791 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 792 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 793 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 794 795 #if defined(CONFIG_CMD_KGDB) 796 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 797 #else 798 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 799 #endif 800 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 801 /* Print Buffer Size */ 802 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 803 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 804 805 /* 806 * For booting Linux, the board info and command line data 807 * have to be in the first 64 MB of memory, since this is 808 * the maximum mapped by the Linux kernel during initialization. 809 */ 810 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 811 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 812 813 #if defined(CONFIG_CMD_KGDB) 814 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 815 #endif 816 817 /* 818 * Environment Configuration 819 */ 820 821 #if defined(CONFIG_TSEC_ENET) 822 #define CONFIG_HAS_ETH0 823 #define CONFIG_HAS_ETH1 824 #define CONFIG_HAS_ETH2 825 #endif 826 827 #define CONFIG_ROOTPATH "/opt/nfsroot" 828 #define CONFIG_BOOTFILE "uImage" 829 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 830 831 /* default location for tftp and bootm */ 832 #define CONFIG_LOADADDR 1000000 833 834 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 835 836 #define CONFIG_BAUDRATE 115200 837 838 #define CONFIG_EXTRA_ENV_SETTINGS \ 839 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 840 "netdev=eth0\0" \ 841 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 842 "loadaddr=1000000\0" \ 843 "consoledev=ttyS0\0" \ 844 "ramdiskaddr=2000000\0" \ 845 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 846 "fdtaddr=1e00000\0" \ 847 "fdtfile=p1010rdb.dtb\0" \ 848 "bdev=sda1\0" \ 849 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 850 "othbootargs=ramdisk_size=600000\0" \ 851 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 852 "console=$consoledev,$baudrate $othbootargs; " \ 853 "usb start;" \ 854 "fatload usb 0:2 $loadaddr $bootfile;" \ 855 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 856 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 857 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 858 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 859 "console=$consoledev,$baudrate $othbootargs; " \ 860 "usb start;" \ 861 "ext2load usb 0:4 $loadaddr $bootfile;" \ 862 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 863 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 864 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 865 CONFIG_BOOTMODE 866 867 #if defined(CONFIG_P1010RDB_PA) 868 #define CONFIG_BOOTMODE \ 869 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 870 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 871 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 872 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 873 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 874 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 875 876 #elif defined(CONFIG_P1010RDB_PB) 877 #define CONFIG_BOOTMODE \ 878 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 879 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 880 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 881 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 882 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 883 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 884 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 885 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 886 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 887 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 888 #endif 889 890 #define CONFIG_RAMBOOTCOMMAND \ 891 "setenv bootargs root=/dev/ram rw " \ 892 "console=$consoledev,$baudrate $othbootargs; " \ 893 "tftp $ramdiskaddr $ramdiskfile;" \ 894 "tftp $loadaddr $bootfile;" \ 895 "tftp $fdtaddr $fdtfile;" \ 896 "bootm $loadaddr $ramdiskaddr $fdtaddr" 897 898 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 899 900 #include <asm/fsl_secure_boot.h> 901 902 #endif /* __CONFIG_H */ 903