1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_PCIE4 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 24 #ifndef CONFIG_SDCARD 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_SYS_TEXT_BASE 0x00201000 34 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 35 #define CONFIG_SPL_PAD_TO 0x40000 36 #define CONFIG_SPL_MAX_SIZE 0x28000 37 #define RESET_VECTOR_OFFSET 0x27FFC 38 #define BOOT_PAGE_OFFSET 0x27000 39 40 #ifdef CONFIG_SDCARD 41 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 42 #define CONFIG_SPL_MMC_SUPPORT 43 #define CONFIG_SPL_MMC_MINIMAL 44 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 45 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 46 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 47 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 48 #ifndef CONFIG_SPL_BUILD 49 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 50 #endif 51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 52 #define CONFIG_SPL_MMC_BOOT 53 #endif 54 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_SKIP_RELOCATE 57 #define CONFIG_SPL_COMMON_INIT_DDR 58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #define CONFIG_SYS_NO_FLASH 60 #endif 61 62 #endif 63 #endif /* CONFIG_RAMBOOT_PBL */ 64 65 #define CONFIG_DDR_ECC 66 67 #define CONFIG_CMD_REGINFO 68 69 /* High Level Configuration Options */ 70 #define CONFIG_BOOKE 71 #define CONFIG_E500 /* BOOKE e500 family */ 72 #define CONFIG_E500MC /* BOOKE e500mc family */ 73 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 74 #define CONFIG_MP /* support multiple processors */ 75 76 #ifndef CONFIG_SYS_TEXT_BASE 77 #define CONFIG_SYS_TEXT_BASE 0xeff40000 78 #endif 79 80 #ifndef CONFIG_RESET_VECTOR_ADDRESS 81 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 82 #endif 83 84 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 85 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 86 #define CONFIG_FSL_IFC /* Enable IFC Support */ 87 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 88 #define CONFIG_PCI /* Enable PCI/PCIE */ 89 #define CONFIG_PCIE1 /* PCIE controller 1 */ 90 #define CONFIG_PCIE2 /* PCIE controller 2 */ 91 #define CONFIG_PCIE3 /* PCIE controller 3 */ 92 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 93 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 94 95 #define CONFIG_FSL_LAW /* Use common FSL init code */ 96 97 #define CONFIG_ENV_OVERWRITE 98 99 /* 100 * These can be toggled for performance analysis, otherwise use default. 101 */ 102 #define CONFIG_SYS_CACHE_STASHING 103 #define CONFIG_BTB /* toggle branch predition */ 104 #ifdef CONFIG_DDR_ECC 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 106 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 107 #endif 108 109 #define CONFIG_ENABLE_36BIT_PHYS 110 111 #define CONFIG_ADDR_MAP 112 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 113 114 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 115 #define CONFIG_SYS_MEMTEST_END 0x00400000 116 #define CONFIG_SYS_ALT_MEMTEST 117 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 118 119 /* 120 * Config the L3 Cache as L3 SRAM 121 */ 122 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 123 #define CONFIG_SYS_L3_SIZE (512 << 10) 124 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 125 #ifdef CONFIG_RAMBOOT_PBL 126 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 127 #endif 128 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 129 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 130 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 131 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 132 133 #define CONFIG_SYS_DCSRBAR 0xf0000000 134 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 135 136 /* 137 * DDR Setup 138 */ 139 #define CONFIG_VERY_BIG_RAM 140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 141 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 142 143 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 144 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 145 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 146 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 147 148 #define CONFIG_DDR_SPD 149 #define CONFIG_SYS_FSL_DDR3 150 151 /* 152 * IFC Definitions 153 */ 154 #define CONFIG_SYS_FLASH_BASE 0xe0000000 155 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 156 157 #ifdef CONFIG_SPL_BUILD 158 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 159 #else 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 161 #endif 162 163 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 164 #define CONFIG_MISC_INIT_R 165 166 #define CONFIG_HWCONFIG 167 168 /* define to use L1 as initial stack */ 169 #define CONFIG_L1_INIT_RAM 170 #define CONFIG_SYS_INIT_RAM_LOCK 171 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 174 /* The assembler doesn't like typecast */ 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 176 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 177 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 178 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 179 180 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 181 GENERATED_GBL_DATA_SIZE) 182 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 183 184 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 185 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 186 187 /* Serial Port - controlled on board with jumper J8 188 * open - index 2 189 * shorted - index 1 190 */ 191 #define CONFIG_CONS_INDEX 1 192 #define CONFIG_SYS_NS16550_SERIAL 193 #define CONFIG_SYS_NS16550_REG_SIZE 1 194 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 195 196 #define CONFIG_SYS_BAUDRATE_TABLE \ 197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 198 199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 201 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 202 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 203 204 /* I2C */ 205 #define CONFIG_SYS_I2C 206 #define CONFIG_SYS_I2C_FSL 207 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 208 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 209 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 211 212 /* 213 * General PCI 214 * Memory space is mapped 1-1, but I/O space must start from 0. 215 */ 216 217 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 218 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 219 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 220 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 221 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 222 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 223 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 224 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 225 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 226 227 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 228 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 229 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 230 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 231 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 232 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 233 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 234 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 235 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 236 237 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 238 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 239 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 240 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 241 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 242 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 243 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 244 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 245 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 246 247 /* controller 4, Base address 203000 */ 248 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 249 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 250 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 251 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 252 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 253 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 254 255 #ifdef CONFIG_PCI 256 #define CONFIG_PCI_INDIRECT_BRIDGE 257 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 258 259 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 260 #define CONFIG_DOS_PARTITION 261 #endif /* CONFIG_PCI */ 262 263 /* SATA */ 264 #ifdef CONFIG_FSL_SATA_V2 265 #define CONFIG_LIBATA 266 #define CONFIG_FSL_SATA 267 268 #define CONFIG_SYS_SATA_MAX_DEVICE 2 269 #define CONFIG_SATA1 270 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 271 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 272 #define CONFIG_SATA2 273 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 274 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 275 276 #define CONFIG_LBA48 277 #define CONFIG_CMD_SATA 278 #define CONFIG_DOS_PARTITION 279 #endif 280 281 #ifdef CONFIG_FMAN_ENET 282 #define CONFIG_MII /* MII PHY management */ 283 #define CONFIG_ETHPRIME "FM1@DTSEC1" 284 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 285 #endif 286 287 /* 288 * Environment 289 */ 290 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 291 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 292 293 /* 294 * Command line configuration. 295 */ 296 #define CONFIG_CMD_ERRATA 297 #define CONFIG_CMD_IRQ 298 299 #ifdef CONFIG_PCI 300 #define CONFIG_CMD_PCI 301 #endif 302 303 /* 304 * Miscellaneous configurable options 305 */ 306 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 307 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 308 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 309 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 310 #ifdef CONFIG_CMD_KGDB 311 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 312 #else 313 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 314 #endif 315 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 316 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 317 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 318 319 /* 320 * For booting Linux, the board info and command line data 321 * have to be in the first 64 MB of memory, since this is 322 * the maximum mapped by the Linux kernel during initialization. 323 */ 324 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 325 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 326 327 #ifdef CONFIG_CMD_KGDB 328 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 329 #endif 330 331 /* 332 * Environment Configuration 333 */ 334 #define CONFIG_ROOTPATH "/opt/nfsroot" 335 #define CONFIG_BOOTFILE "uImage" 336 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 337 338 /* default location for tftp and bootm */ 339 #define CONFIG_LOADADDR 1000000 340 341 #define CONFIG_BAUDRATE 115200 342 343 #define CONFIG_HVBOOT \ 344 "setenv bootargs config-addr=0x60000000; " \ 345 "bootm 0x01000000 - 0x00f00000" 346 347 #ifdef CONFIG_SYS_NO_FLASH 348 #ifndef CONFIG_RAMBOOT_PBL 349 #define CONFIG_ENV_IS_NOWHERE 350 #endif 351 #else 352 #define CONFIG_FLASH_CFI_DRIVER 353 #define CONFIG_SYS_FLASH_CFI 354 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 355 #endif 356 357 #if defined(CONFIG_SPIFLASH) 358 #define CONFIG_SYS_EXTRA_ENV_RELOC 359 #define CONFIG_ENV_IS_IN_SPI_FLASH 360 #define CONFIG_ENV_SPI_BUS 0 361 #define CONFIG_ENV_SPI_CS 0 362 #define CONFIG_ENV_SPI_MAX_HZ 10000000 363 #define CONFIG_ENV_SPI_MODE 0 364 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 365 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 366 #define CONFIG_ENV_SECT_SIZE 0x10000 367 #elif defined(CONFIG_SDCARD) 368 #define CONFIG_SYS_EXTRA_ENV_RELOC 369 #define CONFIG_ENV_IS_IN_MMC 370 #define CONFIG_SYS_MMC_ENV_DEV 0 371 #define CONFIG_ENV_SIZE 0x2000 372 #define CONFIG_ENV_OFFSET (512 * 0x800) 373 #elif defined(CONFIG_NAND) 374 #define CONFIG_SYS_EXTRA_ENV_RELOC 375 #define CONFIG_ENV_IS_IN_NAND 376 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 377 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 378 #elif defined(CONFIG_ENV_IS_NOWHERE) 379 #define CONFIG_ENV_SIZE 0x2000 380 #else 381 #define CONFIG_ENV_IS_IN_FLASH 382 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 383 #define CONFIG_ENV_SIZE 0x2000 384 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 385 #endif 386 387 #define CONFIG_SYS_CLK_FREQ 66666666 388 #define CONFIG_DDR_CLK_FREQ 133333333 389 390 #ifndef __ASSEMBLY__ 391 unsigned long get_board_sys_clk(void); 392 unsigned long get_board_ddr_clk(void); 393 #endif 394 395 /* 396 * DDR Setup 397 */ 398 #define CONFIG_SYS_SPD_BUS_NUM 0 399 #define SPD_EEPROM_ADDRESS1 0x52 400 #define SPD_EEPROM_ADDRESS2 0x54 401 #define SPD_EEPROM_ADDRESS3 0x56 402 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 403 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 404 405 /* 406 * IFC Definitions 407 */ 408 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 409 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 410 + 0x8000000) | \ 411 CSPR_PORT_SIZE_16 | \ 412 CSPR_MSEL_NOR | \ 413 CSPR_V) 414 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 415 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 416 CSPR_PORT_SIZE_16 | \ 417 CSPR_MSEL_NOR | \ 418 CSPR_V) 419 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 420 /* NOR Flash Timing Params */ 421 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 422 423 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 424 FTIM0_NOR_TEADC(0x5) | \ 425 FTIM0_NOR_TEAHC(0x5)) 426 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 427 FTIM1_NOR_TRAD_NOR(0x1A) |\ 428 FTIM1_NOR_TSEQRAD_NOR(0x13)) 429 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 430 FTIM2_NOR_TCH(0x4) | \ 431 FTIM2_NOR_TWPH(0x0E) | \ 432 FTIM2_NOR_TWP(0x1c)) 433 #define CONFIG_SYS_NOR_FTIM3 0x0 434 435 #define CONFIG_SYS_FLASH_QUIET_TEST 436 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 437 438 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 439 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 440 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 441 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 442 443 #define CONFIG_SYS_FLASH_EMPTY_INFO 444 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 445 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 446 447 /* NAND Flash on IFC */ 448 #define CONFIG_NAND_FSL_IFC 449 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 450 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 451 #define CONFIG_SYS_NAND_BASE 0xff800000 452 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 453 454 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 455 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 456 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 457 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 458 | CSPR_V) 459 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 460 461 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 462 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 463 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 464 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 465 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 466 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 467 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 468 469 #define CONFIG_SYS_NAND_ONFI_DETECTION 470 471 /* ONFI NAND Flash mode0 Timing Params */ 472 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 473 FTIM0_NAND_TWP(0x18) | \ 474 FTIM0_NAND_TWCHT(0x07) | \ 475 FTIM0_NAND_TWH(0x0a)) 476 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 477 FTIM1_NAND_TWBE(0x39) | \ 478 FTIM1_NAND_TRR(0x0e) | \ 479 FTIM1_NAND_TRP(0x18)) 480 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 481 FTIM2_NAND_TREH(0x0a) | \ 482 FTIM2_NAND_TWHRE(0x1e)) 483 #define CONFIG_SYS_NAND_FTIM3 0x0 484 485 #define CONFIG_SYS_NAND_DDR_LAW 11 486 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 487 #define CONFIG_SYS_MAX_NAND_DEVICE 1 488 #define CONFIG_CMD_NAND 489 490 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 491 492 #if defined(CONFIG_NAND) 493 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 494 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 495 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 496 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 497 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 498 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 499 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 500 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 501 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 502 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 503 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 504 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 505 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 506 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 507 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 508 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 509 #else 510 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 511 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 512 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 513 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 514 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 515 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 516 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 517 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 518 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 519 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 520 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 521 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 522 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 523 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 524 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 525 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 526 #endif 527 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 528 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 529 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 530 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 531 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 532 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 533 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 534 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 535 536 /* CPLD on IFC */ 537 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 538 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 539 #define CONFIG_SYS_CSPR3_EXT (0xf) 540 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 541 | CSPR_PORT_SIZE_8 \ 542 | CSPR_MSEL_GPCM \ 543 | CSPR_V) 544 545 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 546 #define CONFIG_SYS_CSOR3 0x0 547 548 /* CPLD Timing parameters for IFC CS3 */ 549 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 550 FTIM0_GPCM_TEADC(0x0e) | \ 551 FTIM0_GPCM_TEAHC(0x0e)) 552 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 553 FTIM1_GPCM_TRAD(0x1f)) 554 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 555 FTIM2_GPCM_TCH(0x8) | \ 556 FTIM2_GPCM_TWP(0x1f)) 557 #define CONFIG_SYS_CS3_FTIM3 0x0 558 559 #if defined(CONFIG_RAMBOOT_PBL) 560 #define CONFIG_SYS_RAMBOOT 561 #endif 562 563 /* I2C */ 564 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 565 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 566 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 567 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 568 569 #define I2C_MUX_CH_DEFAULT 0x8 570 #define I2C_MUX_CH_VOL_MONITOR 0xa 571 #define I2C_MUX_CH_VSC3316_FS 0xc 572 #define I2C_MUX_CH_VSC3316_BS 0xd 573 574 /* Voltage monitor on channel 2*/ 575 #define I2C_VOL_MONITOR_ADDR 0x40 576 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 577 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 578 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 579 580 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 581 #ifndef CONFIG_SPL_BUILD 582 #define CONFIG_VID 583 #endif 584 #define CONFIG_VOL_MONITOR_IR36021_SET 585 #define CONFIG_VOL_MONITOR_IR36021_READ 586 /* The lowest and highest voltage allowed for T4240RDB */ 587 #define VDD_MV_MIN 819 588 #define VDD_MV_MAX 1212 589 590 /* 591 * eSPI - Enhanced SPI 592 */ 593 #define CONFIG_SF_DEFAULT_SPEED 10000000 594 #define CONFIG_SF_DEFAULT_MODE 0 595 596 /* Qman/Bman */ 597 #ifndef CONFIG_NOBQFMAN 598 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 599 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 600 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 601 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 602 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 603 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 604 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 605 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 606 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 607 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 608 CONFIG_SYS_BMAN_CENA_SIZE) 609 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 610 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 611 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 612 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 613 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 614 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 615 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 616 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 617 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 618 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 619 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 620 CONFIG_SYS_QMAN_CENA_SIZE) 621 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 622 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 623 624 #define CONFIG_SYS_DPAA_FMAN 625 #define CONFIG_SYS_DPAA_PME 626 #define CONFIG_SYS_PMAN 627 #define CONFIG_SYS_DPAA_DCE 628 #define CONFIG_SYS_DPAA_RMAN 629 #define CONFIG_SYS_INTERLAKEN 630 631 /* Default address of microcode for the Linux Fman driver */ 632 #if defined(CONFIG_SPIFLASH) 633 /* 634 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 635 * env, so we got 0x110000. 636 */ 637 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 638 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 639 #elif defined(CONFIG_SDCARD) 640 /* 641 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 642 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 643 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 644 */ 645 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 646 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 647 #elif defined(CONFIG_NAND) 648 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 649 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 650 #else 651 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 652 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 653 #endif 654 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 655 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 656 #endif /* CONFIG_NOBQFMAN */ 657 658 #ifdef CONFIG_SYS_DPAA_FMAN 659 #define CONFIG_FMAN_ENET 660 #define CONFIG_PHYLIB_10G 661 #define CONFIG_PHY_VITESSE 662 #define CONFIG_PHY_CORTINA 663 #define CONFIG_SYS_CORTINA_FW_IN_NOR 664 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 665 #define CONFIG_CORTINA_FW_LENGTH 0x40000 666 #define CONFIG_PHY_TERANETICS 667 #define SGMII_PHY_ADDR1 0x0 668 #define SGMII_PHY_ADDR2 0x1 669 #define SGMII_PHY_ADDR3 0x2 670 #define SGMII_PHY_ADDR4 0x3 671 #define SGMII_PHY_ADDR5 0x4 672 #define SGMII_PHY_ADDR6 0x5 673 #define SGMII_PHY_ADDR7 0x6 674 #define SGMII_PHY_ADDR8 0x7 675 #define FM1_10GEC1_PHY_ADDR 0x10 676 #define FM1_10GEC2_PHY_ADDR 0x11 677 #define FM2_10GEC1_PHY_ADDR 0x12 678 #define FM2_10GEC2_PHY_ADDR 0x13 679 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 680 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 681 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 682 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 683 #endif 684 685 /* SATA */ 686 #ifdef CONFIG_FSL_SATA_V2 687 #define CONFIG_LIBATA 688 #define CONFIG_FSL_SATA 689 690 #define CONFIG_SYS_SATA_MAX_DEVICE 2 691 #define CONFIG_SATA1 692 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 693 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 694 #define CONFIG_SATA2 695 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 696 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 697 698 #define CONFIG_LBA48 699 #define CONFIG_CMD_SATA 700 #define CONFIG_DOS_PARTITION 701 #endif 702 703 #ifdef CONFIG_FMAN_ENET 704 #define CONFIG_MII /* MII PHY management */ 705 #define CONFIG_ETHPRIME "FM1@DTSEC1" 706 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 707 #endif 708 709 /* 710 * USB 711 */ 712 #define CONFIG_USB_EHCI 713 #define CONFIG_USB_EHCI_FSL 714 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 715 #define CONFIG_HAS_FSL_DR_USB 716 717 #define CONFIG_MMC 718 719 #ifdef CONFIG_MMC 720 #define CONFIG_FSL_ESDHC 721 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 722 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 723 #define CONFIG_GENERIC_MMC 724 #define CONFIG_DOS_PARTITION 725 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 726 #endif 727 728 /* Hash command with SHA acceleration supported in hardware */ 729 #ifdef CONFIG_FSL_CAAM 730 #define CONFIG_CMD_HASH 731 #define CONFIG_SHA_HW_ACCEL 732 #endif 733 734 735 #define __USB_PHY_TYPE utmi 736 737 /* 738 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 739 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 740 * interleaving. It can be cacheline, page, bank, superbank. 741 * See doc/README.fsl-ddr for details. 742 */ 743 #ifdef CONFIG_PPC_T4240 744 #define CTRL_INTLV_PREFERED 3way_4KB 745 #else 746 #define CTRL_INTLV_PREFERED cacheline 747 #endif 748 749 #define CONFIG_EXTRA_ENV_SETTINGS \ 750 "hwconfig=fsl_ddr:" \ 751 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 752 "bank_intlv=auto;" \ 753 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 754 "netdev=eth0\0" \ 755 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 756 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 757 "tftpflash=tftpboot $loadaddr $uboot && " \ 758 "protect off $ubootaddr +$filesize && " \ 759 "erase $ubootaddr +$filesize && " \ 760 "cp.b $loadaddr $ubootaddr $filesize && " \ 761 "protect on $ubootaddr +$filesize && " \ 762 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 763 "consoledev=ttyS0\0" \ 764 "ramdiskaddr=2000000\0" \ 765 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 766 "fdtaddr=1e00000\0" \ 767 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 768 "bdev=sda3\0" 769 770 #define CONFIG_HVBOOT \ 771 "setenv bootargs config-addr=0x60000000; " \ 772 "bootm 0x01000000 - 0x00f00000" 773 774 #define CONFIG_LINUX \ 775 "setenv bootargs root=/dev/ram rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "setenv ramdiskaddr 0x02000000;" \ 778 "setenv fdtaddr 0x00c00000;" \ 779 "setenv loadaddr 0x1000000;" \ 780 "bootm $loadaddr $ramdiskaddr $fdtaddr" 781 782 #define CONFIG_HDBOOT \ 783 "setenv bootargs root=/dev/$bdev rw " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "tftp $loadaddr $bootfile;" \ 786 "tftp $fdtaddr $fdtfile;" \ 787 "bootm $loadaddr - $fdtaddr" 788 789 #define CONFIG_NFSBOOTCOMMAND \ 790 "setenv bootargs root=/dev/nfs rw " \ 791 "nfsroot=$serverip:$rootpath " \ 792 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 793 "console=$consoledev,$baudrate $othbootargs;" \ 794 "tftp $loadaddr $bootfile;" \ 795 "tftp $fdtaddr $fdtfile;" \ 796 "bootm $loadaddr - $fdtaddr" 797 798 #define CONFIG_RAMBOOTCOMMAND \ 799 "setenv bootargs root=/dev/ram rw " \ 800 "console=$consoledev,$baudrate $othbootargs;" \ 801 "tftp $ramdiskaddr $ramdiskfile;" \ 802 "tftp $loadaddr $bootfile;" \ 803 "tftp $fdtaddr $fdtfile;" \ 804 "bootm $loadaddr $ramdiskaddr $fdtaddr" 805 806 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 807 808 #include <asm/fsl_secure_boot.h> 809 810 #endif /* __CONFIG_H */ 811