1 /* 2 * Copyright (C) Stefano Babic <sbabic@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 8 #ifndef __PCM058_CONFIG_H 9 #define __PCM058_CONFIG_H 10 11 #include <config_distro_defaults.h> 12 13 #ifdef CONFIG_SPL 14 #define CONFIG_SPL_YMODEM_SUPPORT 15 #define CONFIG_SPL_MMC_SUPPORT 16 #define CONFIG_SPL_SPI_SUPPORT 17 #define CONFIG_SPL_SPI_FLASH_SUPPORT 18 #define CONFIG_SPL_SPI_LOAD 19 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 20 #include "imx6_spl.h" 21 #endif 22 23 #include "mx6_common.h" 24 25 /* Thermal */ 26 #define CONFIG_IMX_THERMAL 27 28 /* Serial */ 29 #define CONFIG_MXC_UART 30 #define CONFIG_MXC_UART_BASE UART2_BASE 31 #define CONFIG_CONSOLE_DEV "ttymxc1" 32 33 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 34 35 /* Early setup */ 36 #define CONFIG_BOARD_EARLY_INIT_F 37 #define CONFIG_BOARD_LATE_INIT 38 #define CONFIG_DISPLAY_BOARDINFO_LATE 39 40 41 /* Size of malloc() pool */ 42 #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) 43 44 /* Ethernet */ 45 #define CONFIG_FEC_MXC 46 #define CONFIG_MII 47 #define IMX_FEC_BASE ENET_BASE_ADDR 48 #define CONFIG_FEC_XCV_TYPE RGMII 49 #define CONFIG_ETHPRIME "FEC" 50 #define CONFIG_FEC_MXC_PHYADDR 3 51 52 #define CONFIG_PHYLIB 53 #define CONFIG_PHY_MICREL 54 #define CONFIG_PHY_KSZ9031 55 56 /* SPI Flash */ 57 #define CONFIG_MXC_SPI 58 #define CONFIG_SF_DEFAULT_BUS 0 59 #define CONFIG_SF_DEFAULT_CS 0 60 #define CONFIG_SF_DEFAULT_SPEED 20000000 61 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 62 63 /* I2C Configs */ 64 #define CONFIG_SYS_I2C 65 #define CONFIG_SYS_I2C_MXC 66 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */ 67 #define CONFIG_SYS_I2C_SPEED 100000 68 69 #ifndef CONFIG_SPL_BUILD 70 #define CONFIG_CMD_NAND 71 /* Enable NAND support */ 72 #define CONFIG_CMD_NAND_TRIMFFS 73 #define CONFIG_NAND_MXS 74 #define CONFIG_SYS_MAX_NAND_DEVICE 1 75 #define CONFIG_SYS_NAND_BASE 0x40000000 76 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 77 #define CONFIG_SYS_NAND_ONFI_DETECTION 78 #endif 79 80 /* DMA stuff, needed for GPMI/MXS NAND support */ 81 #define CONFIG_APBH_DMA 82 #define CONFIG_APBH_DMA_BURST 83 #define CONFIG_APBH_DMA_BURST8 84 85 /* Filesystem support */ 86 #define CONFIG_LZO 87 #define CONFIG_CMD_UBIFS 88 #define CONFIG_CMD_MTDPARTS 89 #define CONFIG_MTD_PARTITIONS 90 #define CONFIG_MTD_DEVICE 91 #define MTDIDS_DEFAULT "nand0=nand" 92 #define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" 93 94 /* Various command support */ 95 #define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */ 96 #define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ 97 #define CONFIG_CMD_GSC 98 #define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */ 99 #define CONFIG_CMD_UBI 100 #define CONFIG_RBTREE 101 102 /* Physical Memory Map */ 103 #define CONFIG_NR_DRAM_BANKS 1 104 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 105 106 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 107 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 108 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 109 110 #define CONFIG_SYS_INIT_SP_OFFSET \ 111 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 112 #define CONFIG_SYS_INIT_SP_ADDR \ 113 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 114 115 /* MMC Configs */ 116 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 117 #define CONFIG_SYS_FSL_USDHC_NUM 1 118 119 /* Environment organization */ 120 #define CONFIG_ENV_IS_IN_SPI_FLASH 121 #define CONFIG_ENV_SIZE (16 * 1024) 122 #define CONFIG_ENV_OFFSET (1024 * SZ_1K) 123 #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) 124 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 125 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 126 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 127 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 128 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 129 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 130 CONFIG_ENV_SECT_SIZE) 131 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 132 133 #ifdef CONFIG_ENV_IS_IN_NAND 134 #define CONFIG_ENV_OFFSET (0x1E0000) 135 #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) 136 #endif 137 138 #endif 139