1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_SERIAL_SUPPORT 23 #define CONFIG_SPL_MMC_MINIMAL 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_FSL_LAW /* Use common FSL init code */ 27 #define CONFIG_SYS_TEXT_BASE 0x11001000 28 #define CONFIG_SPL_TEXT_BASE 0xD0001000 29 #define CONFIG_SPL_PAD_TO 0x18000 30 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 31 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 32 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 33 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 34 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 35 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 36 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 37 #define CONFIG_SPL_MMC_BOOT 38 #ifdef CONFIG_SPL_BUILD 39 #define CONFIG_SPL_COMMON_INIT_DDR 40 #endif 41 #endif 42 43 #ifdef CONFIG_SPIFLASH 44 #ifdef CONFIG_SECURE_BOOT 45 #define CONFIG_RAMBOOT_SPIFLASH 46 #define CONFIG_SYS_TEXT_BASE 0x11000000 47 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 48 #else 49 #define CONFIG_SPL_SERIAL_SUPPORT 50 #define CONFIG_SPL_SPI_SUPPORT 51 #define CONFIG_SPL_SPI_FLASH_SUPPORT 52 #define CONFIG_SPL_SPI_FLASH_MINIMAL 53 #define CONFIG_SPL_FLUSH_IMAGE 54 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 55 #define CONFIG_FSL_LAW /* Use common FSL init code */ 56 #define CONFIG_SYS_TEXT_BASE 0x11001000 57 #define CONFIG_SPL_TEXT_BASE 0xD0001000 58 #define CONFIG_SPL_PAD_TO 0x18000 59 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 65 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 66 #define CONFIG_SPL_SPI_BOOT 67 #ifdef CONFIG_SPL_BUILD 68 #define CONFIG_SPL_COMMON_INIT_DDR 69 #endif 70 #endif 71 #endif 72 73 #ifdef CONFIG_NAND 74 #ifdef CONFIG_SECURE_BOOT 75 #define CONFIG_SPL_INIT_MINIMAL 76 #define CONFIG_SPL_SERIAL_SUPPORT 77 #define CONFIG_SPL_NAND_BOOT 78 #define CONFIG_SPL_FLUSH_IMAGE 79 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 80 81 #define CONFIG_SYS_TEXT_BASE 0x00201000 82 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 83 #define CONFIG_SPL_MAX_SIZE 8192 84 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 85 #define CONFIG_SPL_RELOC_STACK 0x00100000 86 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 87 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 88 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 89 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 91 #else 92 #ifdef CONFIG_TPL_BUILD 93 #define CONFIG_SPL_NAND_BOOT 94 #define CONFIG_SPL_FLUSH_IMAGE 95 #define CONFIG_SPL_NAND_INIT 96 #define CONFIG_TPL_SERIAL_SUPPORT 97 #define CONFIG_SPL_COMMON_INIT_DDR 98 #define CONFIG_SPL_MAX_SIZE (128 << 10) 99 #define CONFIG_SPL_TEXT_BASE 0xD0001000 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 102 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 103 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 104 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 105 #elif defined(CONFIG_SPL_BUILD) 106 #define CONFIG_SPL_INIT_MINIMAL 107 #define CONFIG_SPL_SERIAL_SUPPORT 108 #define CONFIG_SPL_NAND_MINIMAL 109 #define CONFIG_SPL_FLUSH_IMAGE 110 #define CONFIG_SPL_TEXT_BASE 0xff800000 111 #define CONFIG_SPL_MAX_SIZE 8192 112 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 113 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 114 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 115 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 116 #endif 117 #define CONFIG_SPL_PAD_TO 0x20000 118 #define CONFIG_TPL_PAD_TO 0x20000 119 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 120 #define CONFIG_SYS_TEXT_BASE 0x11001000 121 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 122 #endif 123 #endif 124 125 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 126 #define CONFIG_RAMBOOT_NAND 127 #define CONFIG_SYS_TEXT_BASE 0x11000000 128 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 129 #endif 130 131 #ifndef CONFIG_SYS_TEXT_BASE 132 #define CONFIG_SYS_TEXT_BASE 0xeff40000 133 #endif 134 135 #ifndef CONFIG_RESET_VECTOR_ADDRESS 136 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 137 #endif 138 139 #ifdef CONFIG_SPL_BUILD 140 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 141 #else 142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 143 #endif 144 145 /* High Level Configuration Options */ 146 #define CONFIG_BOOKE /* BOOKE */ 147 #define CONFIG_E500 /* BOOKE e500 family */ 148 #define CONFIG_FSL_IFC /* Enable IFC Support */ 149 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 150 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 151 152 #define CONFIG_PCI /* Enable PCI/PCIE */ 153 #if defined(CONFIG_PCI) 154 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 155 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 156 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 157 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 158 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 159 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 160 161 #define CONFIG_CMD_PCI 162 163 /* 164 * PCI Windows 165 * Memory space is mapped 1-1, but I/O space must start from 0. 166 */ 167 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 168 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 169 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 170 #ifdef CONFIG_PHYS_64BIT 171 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 172 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 173 #else 174 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 175 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 176 #endif 177 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 178 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 179 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 180 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 181 #ifdef CONFIG_PHYS_64BIT 182 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 183 #else 184 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 185 #endif 186 187 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 188 #if defined(CONFIG_P1010RDB_PA) 189 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 190 #elif defined(CONFIG_P1010RDB_PB) 191 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 192 #endif 193 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 194 #ifdef CONFIG_PHYS_64BIT 195 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 196 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 197 #else 198 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 199 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 200 #endif 201 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 202 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 203 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 204 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 205 #ifdef CONFIG_PHYS_64BIT 206 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 207 #else 208 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 209 #endif 210 211 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 212 213 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 214 #define CONFIG_DOS_PARTITION 215 #endif 216 217 #define CONFIG_FSL_LAW /* Use common FSL init code */ 218 #define CONFIG_TSEC_ENET 219 #define CONFIG_ENV_OVERWRITE 220 221 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 222 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 223 224 #define CONFIG_MISC_INIT_R 225 #define CONFIG_HWCONFIG 226 /* 227 * These can be toggled for performance analysis, otherwise use default. 228 */ 229 #define CONFIG_L2_CACHE /* toggle L2 cache */ 230 #define CONFIG_BTB /* toggle branch predition */ 231 232 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 233 234 #define CONFIG_ENABLE_36BIT_PHYS 235 236 #ifdef CONFIG_PHYS_64BIT 237 #define CONFIG_ADDR_MAP 1 238 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 239 #endif 240 241 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 242 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 243 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 244 245 /* DDR Setup */ 246 #define CONFIG_SYS_FSL_DDR3 247 #define CONFIG_SYS_DDR_RAW_TIMING 248 #define CONFIG_DDR_SPD 249 #define CONFIG_SYS_SPD_BUS_NUM 1 250 #define SPD_EEPROM_ADDRESS 0x52 251 252 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 253 254 #ifndef __ASSEMBLY__ 255 extern unsigned long get_sdram_size(void); 256 #endif 257 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 258 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 259 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 260 261 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 262 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 263 264 /* DDR3 Controller Settings */ 265 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 266 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 267 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 268 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 269 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 270 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 271 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 272 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 273 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 274 #define CONFIG_SYS_DDR_RCW_1 0x00000000 275 #define CONFIG_SYS_DDR_RCW_2 0x00000000 276 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 277 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 278 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 279 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 280 281 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 282 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 283 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 284 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 285 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 286 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 287 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 288 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 289 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 290 291 /* settings for DDR3 at 667MT/s */ 292 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 293 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 294 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 295 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 296 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 297 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 298 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 299 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 300 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 301 302 #define CONFIG_SYS_CCSRBAR 0xffe00000 303 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 304 305 /* Don't relocate CCSRBAR while in NAND_SPL */ 306 #ifdef CONFIG_SPL_BUILD 307 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 308 #endif 309 310 /* 311 * Memory map 312 * 313 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 314 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 315 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 316 * 317 * Localbus non-cacheable 318 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 319 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 320 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 321 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 322 */ 323 324 /* 325 * IFC Definitions 326 */ 327 /* NOR Flash on IFC */ 328 #ifdef CONFIG_SPL_BUILD 329 #define CONFIG_SYS_NO_FLASH 330 #endif 331 332 #define CONFIG_SYS_FLASH_BASE 0xee000000 333 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 334 335 #ifdef CONFIG_PHYS_64BIT 336 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 337 #else 338 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 339 #endif 340 341 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 342 CSPR_PORT_SIZE_16 | \ 343 CSPR_MSEL_NOR | \ 344 CSPR_V) 345 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 346 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 347 /* NOR Flash Timing Params */ 348 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 349 FTIM0_NOR_TEADC(0x5) | \ 350 FTIM0_NOR_TEAHC(0x5) 351 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 352 FTIM1_NOR_TRAD_NOR(0x0f) 353 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 354 FTIM2_NOR_TCH(0x4) | \ 355 FTIM2_NOR_TWP(0x1c) 356 #define CONFIG_SYS_NOR_FTIM3 0x0 357 358 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 359 #define CONFIG_SYS_FLASH_QUIET_TEST 360 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 361 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 362 363 #undef CONFIG_SYS_FLASH_CHECKSUM 364 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 365 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 366 367 /* CFI for NOR Flash */ 368 #define CONFIG_FLASH_CFI_DRIVER 369 #define CONFIG_SYS_FLASH_CFI 370 #define CONFIG_SYS_FLASH_EMPTY_INFO 371 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 372 373 /* NAND Flash on IFC */ 374 #define CONFIG_SYS_NAND_BASE 0xff800000 375 #ifdef CONFIG_PHYS_64BIT 376 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 377 #else 378 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 379 #endif 380 381 #define CONFIG_MTD_DEVICE 382 #define CONFIG_MTD_PARTITION 383 #define CONFIG_CMD_MTDPARTS 384 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 385 #define MTDPARTS_DEFAULT \ 386 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 387 388 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 389 | CSPR_PORT_SIZE_8 \ 390 | CSPR_MSEL_NAND \ 391 | CSPR_V) 392 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 393 394 #if defined(CONFIG_P1010RDB_PA) 395 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 396 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 397 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 398 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 399 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 400 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 401 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 402 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 403 404 #elif defined(CONFIG_P1010RDB_PB) 405 #define CONFIG_SYS_NAND_ONFI_DETECTION 406 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 407 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 408 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 409 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 410 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 411 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 412 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 413 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 414 #endif 415 416 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 417 #define CONFIG_SYS_MAX_NAND_DEVICE 1 418 #define CONFIG_CMD_NAND 419 420 #if defined(CONFIG_P1010RDB_PA) 421 /* NAND Flash Timing Params */ 422 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 423 FTIM0_NAND_TWP(0x0C) | \ 424 FTIM0_NAND_TWCHT(0x04) | \ 425 FTIM0_NAND_TWH(0x05) 426 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 427 FTIM1_NAND_TWBE(0x1d) | \ 428 FTIM1_NAND_TRR(0x07) | \ 429 FTIM1_NAND_TRP(0x0c) 430 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 431 FTIM2_NAND_TREH(0x05) | \ 432 FTIM2_NAND_TWHRE(0x0f) 433 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 434 435 #elif defined(CONFIG_P1010RDB_PB) 436 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 437 /* ONFI NAND Flash mode0 Timing Params */ 438 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 439 FTIM0_NAND_TWP(0x18) | \ 440 FTIM0_NAND_TWCHT(0x07) | \ 441 FTIM0_NAND_TWH(0x0a)) 442 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 443 FTIM1_NAND_TWBE(0x39) | \ 444 FTIM1_NAND_TRR(0x0e) | \ 445 FTIM1_NAND_TRP(0x18)) 446 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 447 FTIM2_NAND_TREH(0x0a) | \ 448 FTIM2_NAND_TWHRE(0x1e)) 449 #define CONFIG_SYS_NAND_FTIM3 0x0 450 #endif 451 452 #define CONFIG_SYS_NAND_DDR_LAW 11 453 454 /* Set up IFC registers for boot location NOR/NAND */ 455 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 456 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 457 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 458 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 459 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 460 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 461 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 462 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 463 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 464 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 465 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 466 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 467 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 468 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 469 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 470 #else 471 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 472 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 473 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 474 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 475 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 476 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 477 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 478 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 479 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 480 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 481 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 482 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 483 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 484 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 485 #endif 486 487 /* CPLD on IFC */ 488 #define CONFIG_SYS_CPLD_BASE 0xffb00000 489 490 #ifdef CONFIG_PHYS_64BIT 491 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 492 #else 493 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 494 #endif 495 496 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 497 | CSPR_PORT_SIZE_8 \ 498 | CSPR_MSEL_GPCM \ 499 | CSPR_V) 500 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 501 #define CONFIG_SYS_CSOR3 0x0 502 /* CPLD Timing parameters for IFC CS3 */ 503 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 504 FTIM0_GPCM_TEADC(0x0e) | \ 505 FTIM0_GPCM_TEAHC(0x0e)) 506 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 507 FTIM1_GPCM_TRAD(0x1f)) 508 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 509 FTIM2_GPCM_TCH(0x8) | \ 510 FTIM2_GPCM_TWP(0x1f)) 511 #define CONFIG_SYS_CS3_FTIM3 0x0 512 513 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 514 defined(CONFIG_RAMBOOT_NAND) 515 #define CONFIG_SYS_RAMBOOT 516 #define CONFIG_SYS_EXTRA_ENV_RELOC 517 #else 518 #undef CONFIG_SYS_RAMBOOT 519 #endif 520 521 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 522 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 523 #define CONFIG_A003399_NOR_WORKAROUND 524 #endif 525 #endif 526 527 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 528 #define CONFIG_BOARD_EARLY_INIT_R 529 530 #define CONFIG_SYS_INIT_RAM_LOCK 531 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 532 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 533 534 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 535 - GENERATED_GBL_DATA_SIZE) 536 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 537 538 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 539 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 540 541 /* 542 * Config the L2 Cache as L2 SRAM 543 */ 544 #if defined(CONFIG_SPL_BUILD) 545 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 546 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 547 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 548 #define CONFIG_SYS_L2_SIZE (256 << 10) 549 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 550 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 551 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 552 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 553 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 554 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 555 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 556 #elif defined(CONFIG_NAND) 557 #ifdef CONFIG_TPL_BUILD 558 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 559 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 560 #define CONFIG_SYS_L2_SIZE (256 << 10) 561 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 562 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 563 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 564 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 565 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 566 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 567 #else 568 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 569 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 570 #define CONFIG_SYS_L2_SIZE (256 << 10) 571 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 572 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 573 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 574 #endif 575 #endif 576 #endif 577 578 /* Serial Port */ 579 #define CONFIG_CONS_INDEX 1 580 #undef CONFIG_SERIAL_SOFTWARE_FIFO 581 #define CONFIG_SYS_NS16550_SERIAL 582 #define CONFIG_SYS_NS16550_REG_SIZE 1 583 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 584 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 585 #define CONFIG_NS16550_MIN_FUNCTIONS 586 #endif 587 588 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 589 590 #define CONFIG_SYS_BAUDRATE_TABLE \ 591 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 592 593 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 594 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 595 596 /* I2C */ 597 #define CONFIG_SYS_I2C 598 #define CONFIG_SYS_I2C_FSL 599 #define CONFIG_SYS_FSL_I2C_SPEED 400000 600 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 601 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 602 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 603 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 604 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 605 #define I2C_PCA9557_ADDR1 0x18 606 #define I2C_PCA9557_ADDR2 0x19 607 #define I2C_PCA9557_BUS_NUM 0 608 609 /* I2C EEPROM */ 610 #if defined(CONFIG_P1010RDB_PB) 611 #define CONFIG_ID_EEPROM 612 #ifdef CONFIG_ID_EEPROM 613 #define CONFIG_SYS_I2C_EEPROM_NXID 614 #endif 615 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 616 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 617 #define CONFIG_SYS_EEPROM_BUS_NUM 0 618 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 619 #endif 620 /* enable read and write access to EEPROM */ 621 #define CONFIG_CMD_EEPROM 622 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 623 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 624 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 625 626 /* RTC */ 627 #define CONFIG_RTC_PT7C4338 628 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 629 630 /* 631 * SPI interface will not be available in case of NAND boot SPI CS0 will be 632 * used for SLIC 633 */ 634 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 635 /* eSPI - Enhanced SPI */ 636 #define CONFIG_SF_DEFAULT_SPEED 10000000 637 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 638 #endif 639 640 #if defined(CONFIG_TSEC_ENET) 641 #define CONFIG_MII /* MII PHY management */ 642 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 643 #define CONFIG_TSEC1 1 644 #define CONFIG_TSEC1_NAME "eTSEC1" 645 #define CONFIG_TSEC2 1 646 #define CONFIG_TSEC2_NAME "eTSEC2" 647 #define CONFIG_TSEC3 1 648 #define CONFIG_TSEC3_NAME "eTSEC3" 649 650 #define TSEC1_PHY_ADDR 1 651 #define TSEC2_PHY_ADDR 0 652 #define TSEC3_PHY_ADDR 2 653 654 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 655 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 656 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 657 658 #define TSEC1_PHYIDX 0 659 #define TSEC2_PHYIDX 0 660 #define TSEC3_PHYIDX 0 661 662 #define CONFIG_ETHPRIME "eTSEC1" 663 664 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 665 666 /* TBI PHY configuration for SGMII mode */ 667 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 668 TBICR_PHY_RESET \ 669 | TBICR_ANEG_ENABLE \ 670 | TBICR_FULL_DUPLEX \ 671 | TBICR_SPEED1_SET \ 672 ) 673 674 #endif /* CONFIG_TSEC_ENET */ 675 676 /* SATA */ 677 #define CONFIG_FSL_SATA 678 #define CONFIG_FSL_SATA_V2 679 #define CONFIG_LIBATA 680 681 #ifdef CONFIG_FSL_SATA 682 #define CONFIG_SYS_SATA_MAX_DEVICE 2 683 #define CONFIG_SATA1 684 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 685 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 686 #define CONFIG_SATA2 687 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 688 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 689 690 #define CONFIG_CMD_SATA 691 #define CONFIG_LBA48 692 #endif /* #ifdef CONFIG_FSL_SATA */ 693 694 #define CONFIG_MMC 695 #ifdef CONFIG_MMC 696 #define CONFIG_DOS_PARTITION 697 #define CONFIG_FSL_ESDHC 698 #define CONFIG_GENERIC_MMC 699 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 700 #endif 701 702 #define CONFIG_HAS_FSL_DR_USB 703 704 #if defined(CONFIG_HAS_FSL_DR_USB) 705 #define CONFIG_USB_EHCI 706 707 #ifdef CONFIG_USB_EHCI 708 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 709 #define CONFIG_USB_EHCI_FSL 710 #endif 711 #endif 712 713 /* 714 * Environment 715 */ 716 #if defined(CONFIG_SDCARD) 717 #define CONFIG_ENV_IS_IN_MMC 718 #define CONFIG_FSL_FIXED_MMC_LOCATION 719 #define CONFIG_SYS_MMC_ENV_DEV 0 720 #define CONFIG_ENV_SIZE 0x2000 721 #elif defined(CONFIG_SPIFLASH) 722 #define CONFIG_ENV_IS_IN_SPI_FLASH 723 #define CONFIG_ENV_SPI_BUS 0 724 #define CONFIG_ENV_SPI_CS 0 725 #define CONFIG_ENV_SPI_MAX_HZ 10000000 726 #define CONFIG_ENV_SPI_MODE 0 727 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 728 #define CONFIG_ENV_SECT_SIZE 0x10000 729 #define CONFIG_ENV_SIZE 0x2000 730 #elif defined(CONFIG_NAND) 731 #define CONFIG_ENV_IS_IN_NAND 732 #ifdef CONFIG_TPL_BUILD 733 #define CONFIG_ENV_SIZE 0x2000 734 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 735 #else 736 #if defined(CONFIG_P1010RDB_PA) 737 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 738 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 739 #elif defined(CONFIG_P1010RDB_PB) 740 #define CONFIG_ENV_SIZE (16 * 1024) 741 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 742 #endif 743 #endif 744 #define CONFIG_ENV_OFFSET (1024 * 1024) 745 #elif defined(CONFIG_SYS_RAMBOOT) 746 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 747 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 748 #define CONFIG_ENV_SIZE 0x2000 749 #else 750 #define CONFIG_ENV_IS_IN_FLASH 751 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 752 #define CONFIG_ENV_SIZE 0x2000 753 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 754 #endif 755 756 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 757 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 758 759 /* 760 * Command line configuration. 761 */ 762 #define CONFIG_CMD_DATE 763 #define CONFIG_CMD_ERRATA 764 #define CONFIG_CMD_IRQ 765 #define CONFIG_CMD_REGINFO 766 767 #undef CONFIG_WATCHDOG /* watchdog disabled */ 768 769 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 770 || defined(CONFIG_FSL_SATA) 771 #define CONFIG_DOS_PARTITION 772 #endif 773 774 /* Hash command with SHA acceleration supported in hardware */ 775 #ifdef CONFIG_FSL_CAAM 776 #define CONFIG_CMD_HASH 777 #define CONFIG_SHA_HW_ACCEL 778 #endif 779 780 /* 781 * Miscellaneous configurable options 782 */ 783 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 784 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 785 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 786 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 787 788 #if defined(CONFIG_CMD_KGDB) 789 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 790 #else 791 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 792 #endif 793 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 794 /* Print Buffer Size */ 795 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 796 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 797 798 /* 799 * For booting Linux, the board info and command line data 800 * have to be in the first 64 MB of memory, since this is 801 * the maximum mapped by the Linux kernel during initialization. 802 */ 803 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 804 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 805 806 #if defined(CONFIG_CMD_KGDB) 807 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 808 #endif 809 810 /* 811 * Environment Configuration 812 */ 813 814 #if defined(CONFIG_TSEC_ENET) 815 #define CONFIG_HAS_ETH0 816 #define CONFIG_HAS_ETH1 817 #define CONFIG_HAS_ETH2 818 #endif 819 820 #define CONFIG_ROOTPATH "/opt/nfsroot" 821 #define CONFIG_BOOTFILE "uImage" 822 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 823 824 /* default location for tftp and bootm */ 825 #define CONFIG_LOADADDR 1000000 826 827 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 828 829 #define CONFIG_BAUDRATE 115200 830 831 #define CONFIG_EXTRA_ENV_SETTINGS \ 832 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 833 "netdev=eth0\0" \ 834 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 835 "loadaddr=1000000\0" \ 836 "consoledev=ttyS0\0" \ 837 "ramdiskaddr=2000000\0" \ 838 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 839 "fdtaddr=1e00000\0" \ 840 "fdtfile=p1010rdb.dtb\0" \ 841 "bdev=sda1\0" \ 842 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 843 "othbootargs=ramdisk_size=600000\0" \ 844 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 845 "console=$consoledev,$baudrate $othbootargs; " \ 846 "usb start;" \ 847 "fatload usb 0:2 $loadaddr $bootfile;" \ 848 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 849 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 850 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 851 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 852 "console=$consoledev,$baudrate $othbootargs; " \ 853 "usb start;" \ 854 "ext2load usb 0:4 $loadaddr $bootfile;" \ 855 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 856 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 857 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 858 CONFIG_BOOTMODE 859 860 #if defined(CONFIG_P1010RDB_PA) 861 #define CONFIG_BOOTMODE \ 862 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 863 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 864 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 865 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 866 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 867 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 868 869 #elif defined(CONFIG_P1010RDB_PB) 870 #define CONFIG_BOOTMODE \ 871 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 872 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 873 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 874 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 875 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 876 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 877 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 878 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 879 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 880 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 881 #endif 882 883 #define CONFIG_RAMBOOTCOMMAND \ 884 "setenv bootargs root=/dev/ram rw " \ 885 "console=$consoledev,$baudrate $othbootargs; " \ 886 "tftp $ramdiskaddr $ramdiskfile;" \ 887 "tftp $loadaddr $bootfile;" \ 888 "tftp $fdtaddr $fdtfile;" \ 889 "bootm $loadaddr $ramdiskaddr $fdtaddr" 890 891 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 892 893 #include <asm/fsl_secure_boot.h> 894 895 #endif /* __CONFIG_H */ 896