1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 18 #define CONFIG_SPL_SERIAL_SUPPORT 19 #define CONFIG_SPL_MMC_MINIMAL 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_FSL_LAW /* Use common FSL init code */ 23 #define CONFIG_SYS_TEXT_BASE 0x11001000 24 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 25 #define CONFIG_SPL_PAD_TO 0x20000 26 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 27 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 28 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 29 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 30 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 31 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 33 #define CONFIG_SPL_MMC_BOOT 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_COMMON_INIT_DDR 36 #endif 37 #endif 38 39 #ifdef CONFIG_SPIFLASH 40 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 41 #define CONFIG_SPL_SERIAL_SUPPORT 42 #define CONFIG_SPL_SPI_SUPPORT 43 #define CONFIG_SPL_SPI_FLASH_SUPPORT 44 #define CONFIG_SPL_SPI_FLASH_MINIMAL 45 #define CONFIG_SPL_FLUSH_IMAGE 46 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 47 #define CONFIG_FSL_LAW /* Use common FSL init code */ 48 #define CONFIG_SYS_TEXT_BASE 0x11001000 49 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 50 #define CONFIG_SPL_PAD_TO 0x20000 51 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 58 #define CONFIG_SPL_SPI_BOOT 59 #ifdef CONFIG_SPL_BUILD 60 #define CONFIG_SPL_COMMON_INIT_DDR 61 #endif 62 #endif 63 64 #define CONFIG_NAND_FSL_ELBC 65 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 66 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 67 68 #ifdef CONFIG_NAND 69 #ifdef CONFIG_TPL_BUILD 70 #define CONFIG_SPL_NAND_BOOT 71 #define CONFIG_SPL_FLUSH_IMAGE 72 #define CONFIG_TPL_NAND_INIT 73 #define CONFIG_TPL_SERIAL_SUPPORT 74 #define CONFIG_TPL_NAND_SUPPORT 75 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 76 #define CONFIG_SPL_COMMON_INIT_DDR 77 #define CONFIG_SPL_MAX_SIZE (128 << 10) 78 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 80 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 81 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 82 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 83 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 84 #elif defined(CONFIG_SPL_BUILD) 85 #define CONFIG_SPL_INIT_MINIMAL 86 #define CONFIG_SPL_SERIAL_SUPPORT 87 #define CONFIG_SPL_NAND_SUPPORT 88 #define CONFIG_SPL_FLUSH_IMAGE 89 #define CONFIG_SPL_TEXT_BASE 0xff800000 90 #define CONFIG_SPL_MAX_SIZE 4096 91 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 92 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 93 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 94 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 95 #endif 96 #define CONFIG_SPL_PAD_TO 0x20000 97 #define CONFIG_TPL_PAD_TO 0x20000 98 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 99 #define CONFIG_SYS_TEXT_BASE 0x11001000 100 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 101 #endif 102 103 /* High Level Configuration Options */ 104 #define CONFIG_BOOKE /* BOOKE */ 105 #define CONFIG_E500 /* BOOKE e500 family */ 106 #define CONFIG_P1022 107 #define CONFIG_P1022DS 108 #define CONFIG_MP /* support multiple processors */ 109 110 #ifndef CONFIG_SYS_TEXT_BASE 111 #define CONFIG_SYS_TEXT_BASE 0xeff40000 112 #endif 113 114 #ifndef CONFIG_RESET_VECTOR_ADDRESS 115 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 116 #endif 117 118 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 119 #define CONFIG_PCI /* Enable PCI/PCIE */ 120 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 121 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 122 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 123 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 124 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 125 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 126 127 #define CONFIG_ENABLE_36BIT_PHYS 128 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_ADDR_MAP 131 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 132 #endif 133 134 #define CONFIG_FSL_LAW /* Use common FSL init code */ 135 136 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 137 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 138 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 139 140 /* 141 * These can be toggled for performance analysis, otherwise use default. 142 */ 143 #define CONFIG_L2_CACHE 144 #define CONFIG_BTB 145 146 #define CONFIG_SYS_MEMTEST_START 0x00000000 147 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 148 149 #define CONFIG_SYS_CCSRBAR 0xffe00000 150 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 151 152 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 153 SPL code*/ 154 #ifdef CONFIG_SPL_BUILD 155 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 156 #endif 157 158 /* DDR Setup */ 159 #define CONFIG_DDR_SPD 160 #define CONFIG_VERY_BIG_RAM 161 #define CONFIG_SYS_FSL_DDR3 162 163 #ifdef CONFIG_DDR_ECC 164 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 165 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 166 #endif 167 168 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 169 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 170 171 #define CONFIG_NUM_DDR_CONTROLLERS 1 172 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 173 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 174 175 /* I2C addresses of SPD EEPROMs */ 176 #define CONFIG_SYS_SPD_BUS_NUM 1 177 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 178 179 /* These are used when DDR doesn't use SPD. */ 180 #define CONFIG_SYS_SDRAM_SIZE 2048 181 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 182 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 183 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 184 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 185 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 186 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 187 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 188 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 189 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 190 #define CONFIG_SYS_DDR_MODE_1 0x00441221 191 #define CONFIG_SYS_DDR_MODE_2 0x00000000 192 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 193 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 194 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 195 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 196 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 197 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 198 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 199 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 200 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 201 202 /* 203 * Memory map 204 * 205 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 206 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 207 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 208 * 209 * Localbus cacheable (TBD) 210 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 211 * 212 * Localbus non-cacheable 213 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 214 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 215 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 216 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 217 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 218 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 219 */ 220 221 /* 222 * Local Bus Definitions 223 */ 224 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 225 #ifdef CONFIG_PHYS_64BIT 226 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 227 #else 228 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 229 #endif 230 231 #define CONFIG_FLASH_BR_PRELIM \ 232 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 233 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 234 235 #ifdef CONFIG_NAND 236 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 237 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 238 #else 239 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 240 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 241 #endif 242 243 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 244 #define CONFIG_SYS_FLASH_QUIET_TEST 245 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 246 247 #define CONFIG_SYS_MAX_FLASH_BANKS 1 248 #define CONFIG_SYS_MAX_FLASH_SECT 1024 249 250 #ifndef CONFIG_SYS_MONITOR_BASE 251 #ifdef CONFIG_SPL_BUILD 252 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 253 #else 254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 255 #endif 256 #endif 257 258 #define CONFIG_FLASH_CFI_DRIVER 259 #define CONFIG_SYS_FLASH_CFI 260 #define CONFIG_SYS_FLASH_EMPTY_INFO 261 262 /* Nand Flash */ 263 #if defined(CONFIG_NAND_FSL_ELBC) 264 #define CONFIG_SYS_NAND_BASE 0xff800000 265 #ifdef CONFIG_PHYS_64BIT 266 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 267 #else 268 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 269 #endif 270 271 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 272 #define CONFIG_SYS_MAX_NAND_DEVICE 1 273 #define CONFIG_CMD_NAND 1 274 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 275 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 276 277 /* NAND flash config */ 278 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 279 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 280 | BR_PS_8 /* Port Size = 8 bit */ \ 281 | BR_MS_FCM /* MSEL = FCM */ \ 282 | BR_V) /* valid */ 283 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 284 | OR_FCM_PGS /* Large Page*/ \ 285 | OR_FCM_CSCT \ 286 | OR_FCM_CST \ 287 | OR_FCM_CHT \ 288 | OR_FCM_SCY_1 \ 289 | OR_FCM_TRLX \ 290 | OR_FCM_EHTR) 291 #ifdef CONFIG_NAND 292 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 293 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 294 #else 295 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 296 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 297 #endif 298 299 #endif /* CONFIG_NAND_FSL_ELBC */ 300 301 #define CONFIG_BOARD_EARLY_INIT_F 302 #define CONFIG_BOARD_EARLY_INIT_R 303 #define CONFIG_MISC_INIT_R 304 #define CONFIG_HWCONFIG 305 306 #define CONFIG_FSL_NGPIXIS 307 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 308 #ifdef CONFIG_PHYS_64BIT 309 #define PIXIS_BASE_PHYS 0xfffdf0000ull 310 #else 311 #define PIXIS_BASE_PHYS PIXIS_BASE 312 #endif 313 314 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 315 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 316 317 #define PIXIS_LBMAP_SWITCH 7 318 #define PIXIS_LBMAP_MASK 0xF0 319 #define PIXIS_LBMAP_ALTBANK 0x20 320 #define PIXIS_SPD 0x07 321 #define PIXIS_SPD_SYSCLK_MASK 0x07 322 #define PIXIS_ELBC_SPI_MASK 0xc0 323 #define PIXIS_SPI 0x80 324 325 #define CONFIG_SYS_INIT_RAM_LOCK 326 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 327 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 328 329 #define CONFIG_SYS_GBL_DATA_OFFSET \ 330 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 331 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 332 333 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 334 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 335 336 /* 337 * Config the L2 Cache as L2 SRAM 338 */ 339 #if defined(CONFIG_SPL_BUILD) 340 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 341 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 342 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 343 #define CONFIG_SYS_L2_SIZE (256 << 10) 344 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 345 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 346 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 347 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 348 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 349 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 350 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 351 #elif defined(CONFIG_NAND) 352 #ifdef CONFIG_TPL_BUILD 353 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 354 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 355 #define CONFIG_SYS_L2_SIZE (256 << 10) 356 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 357 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 358 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 359 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 360 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 361 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 362 #else 363 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 364 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 365 #define CONFIG_SYS_L2_SIZE (256 << 10) 366 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 367 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 368 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 369 #endif 370 #endif 371 #endif 372 373 /* 374 * Serial Port 375 */ 376 #define CONFIG_CONS_INDEX 1 377 #define CONFIG_SYS_NS16550_SERIAL 378 #define CONFIG_SYS_NS16550_REG_SIZE 1 379 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 380 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 381 #define CONFIG_NS16550_MIN_FUNCTIONS 382 #endif 383 384 #define CONFIG_SYS_BAUDRATE_TABLE \ 385 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 386 387 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 388 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 389 390 /* Video */ 391 392 #ifdef CONFIG_FSL_DIU_FB 393 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 394 #define CONFIG_VIDEO 395 #define CONFIG_CMD_BMP 396 #define CONFIG_CFB_CONSOLE 397 #define CONFIG_VIDEO_SW_CURSOR 398 #define CONFIG_VGA_AS_SINGLE_DEVICE 399 #define CONFIG_VIDEO_LOGO 400 #define CONFIG_VIDEO_BMP_LOGO 401 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 402 /* 403 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 404 * disable empty flash sector detection, which is I/O-intensive. 405 */ 406 #undef CONFIG_SYS_FLASH_EMPTY_INFO 407 #endif 408 409 #ifndef CONFIG_FSL_DIU_FB 410 #endif 411 412 #ifdef CONFIG_ATI 413 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 414 #define CONFIG_VIDEO 415 #define CONFIG_BIOSEMU 416 #define CONFIG_VIDEO_SW_CURSOR 417 #define CONFIG_ATI_RADEON_FB 418 #define CONFIG_VIDEO_LOGO 419 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 420 #define CONFIG_CFB_CONSOLE 421 #define CONFIG_VGA_AS_SINGLE_DEVICE 422 #endif 423 424 /* I2C */ 425 #define CONFIG_SYS_I2C 426 #define CONFIG_SYS_I2C_FSL 427 #define CONFIG_SYS_FSL_I2C_SPEED 400000 428 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 429 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 430 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 431 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 432 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 433 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 434 435 /* 436 * I2C2 EEPROM 437 */ 438 #define CONFIG_ID_EEPROM 439 #define CONFIG_SYS_I2C_EEPROM_NXID 440 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 441 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 442 #define CONFIG_SYS_EEPROM_BUS_NUM 1 443 444 /* 445 * eSPI - Enhanced SPI 446 */ 447 448 #define CONFIG_HARD_SPI 449 450 #define CONFIG_SF_DEFAULT_SPEED 10000000 451 #define CONFIG_SF_DEFAULT_MODE 0 452 453 /* 454 * General PCI 455 * Memory space is mapped 1-1, but I/O space must start from 0. 456 */ 457 458 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 459 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 462 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 463 #else 464 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 465 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 466 #endif 467 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 468 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 469 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 472 #else 473 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 474 #endif 475 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 476 477 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 478 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 481 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 482 #else 483 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 484 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 485 #endif 486 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 487 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 488 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 491 #else 492 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 493 #endif 494 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 495 496 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 497 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 498 #ifdef CONFIG_PHYS_64BIT 499 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 500 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 501 #else 502 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 503 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 504 #endif 505 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 506 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 507 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 508 #ifdef CONFIG_PHYS_64BIT 509 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 510 #else 511 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 512 #endif 513 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 514 515 #ifdef CONFIG_PCI 516 #define CONFIG_PCI_INDIRECT_BRIDGE 517 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 518 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 519 #endif 520 521 /* SATA */ 522 #define CONFIG_LIBATA 523 #define CONFIG_FSL_SATA 524 #define CONFIG_FSL_SATA_V2 525 526 #define CONFIG_SYS_SATA_MAX_DEVICE 2 527 #define CONFIG_SATA1 528 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 529 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 530 #define CONFIG_SATA2 531 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 532 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 533 534 #ifdef CONFIG_FSL_SATA 535 #define CONFIG_LBA48 536 #define CONFIG_CMD_SATA 537 #define CONFIG_DOS_PARTITION 538 #endif 539 540 #define CONFIG_MMC 541 #ifdef CONFIG_MMC 542 #define CONFIG_FSL_ESDHC 543 #define CONFIG_GENERIC_MMC 544 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 545 #endif 546 547 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 548 #define CONFIG_DOS_PARTITION 549 #endif 550 551 #define CONFIG_TSEC_ENET 552 #ifdef CONFIG_TSEC_ENET 553 554 #define CONFIG_TSECV2 555 556 #define CONFIG_MII /* MII PHY management */ 557 #define CONFIG_TSEC1 1 558 #define CONFIG_TSEC1_NAME "eTSEC1" 559 #define CONFIG_TSEC2 1 560 #define CONFIG_TSEC2_NAME "eTSEC2" 561 562 #define TSEC1_PHY_ADDR 1 563 #define TSEC2_PHY_ADDR 2 564 565 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 566 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 567 568 #define TSEC1_PHYIDX 0 569 #define TSEC2_PHYIDX 0 570 571 #define CONFIG_ETHPRIME "eTSEC1" 572 573 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 574 #endif 575 576 /* 577 * Dynamic MTD Partition support with mtdparts 578 */ 579 #define CONFIG_MTD_DEVICE 580 #define CONFIG_MTD_PARTITIONS 581 #define CONFIG_CMD_MTDPARTS 582 #define CONFIG_FLASH_CFI_MTD 583 #ifdef CONFIG_PHYS_64BIT 584 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 585 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 586 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 587 "512k(dtb),768k(u-boot)" 588 #else 589 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 590 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 591 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 592 "512k(dtb),768k(u-boot)" 593 #endif 594 595 /* 596 * Environment 597 */ 598 #ifdef CONFIG_SPIFLASH 599 #define CONFIG_ENV_IS_IN_SPI_FLASH 600 #define CONFIG_ENV_SPI_BUS 0 601 #define CONFIG_ENV_SPI_CS 0 602 #define CONFIG_ENV_SPI_MAX_HZ 10000000 603 #define CONFIG_ENV_SPI_MODE 0 604 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 605 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 606 #define CONFIG_ENV_SECT_SIZE 0x10000 607 #elif defined(CONFIG_SDCARD) 608 #define CONFIG_ENV_IS_IN_MMC 609 #define CONFIG_FSL_FIXED_MMC_LOCATION 610 #define CONFIG_ENV_SIZE 0x2000 611 #define CONFIG_SYS_MMC_ENV_DEV 0 612 #elif defined(CONFIG_NAND) 613 #ifdef CONFIG_TPL_BUILD 614 #define CONFIG_ENV_SIZE 0x2000 615 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 616 #else 617 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 618 #endif 619 #define CONFIG_ENV_IS_IN_NAND 620 #define CONFIG_ENV_OFFSET (1024 * 1024) 621 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 622 #elif defined(CONFIG_SYS_RAMBOOT) 623 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 624 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 625 #define CONFIG_ENV_SIZE 0x2000 626 #else 627 #define CONFIG_ENV_IS_IN_FLASH 628 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 629 #define CONFIG_ENV_SIZE 0x2000 630 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 631 #endif 632 633 #define CONFIG_LOADS_ECHO 634 #define CONFIG_SYS_LOADS_BAUD_CHANGE 635 636 /* 637 * Command line configuration. 638 */ 639 #define CONFIG_CMD_ERRATA 640 #define CONFIG_CMD_IRQ 641 #define CONFIG_CMD_REGINFO 642 643 #ifdef CONFIG_PCI 644 #define CONFIG_CMD_PCI 645 #endif 646 647 /* 648 * USB 649 */ 650 #define CONFIG_HAS_FSL_DR_USB 651 #ifdef CONFIG_HAS_FSL_DR_USB 652 #define CONFIG_USB_EHCI 653 654 #ifdef CONFIG_USB_EHCI 655 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 656 #define CONFIG_USB_EHCI_FSL 657 #endif 658 #endif 659 660 /* 661 * Miscellaneous configurable options 662 */ 663 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 664 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 665 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 666 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 667 #ifdef CONFIG_CMD_KGDB 668 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 669 #else 670 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 671 #endif 672 /* Print Buffer Size */ 673 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 674 #define CONFIG_SYS_MAXARGS 16 675 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 676 677 /* 678 * For booting Linux, the board info and command line data 679 * have to be in the first 64 MB of memory, since this is 680 * the maximum mapped by the Linux kernel during initialization. 681 */ 682 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 683 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 684 685 #ifdef CONFIG_CMD_KGDB 686 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 687 #endif 688 689 /* 690 * Environment Configuration 691 */ 692 693 #define CONFIG_HOSTNAME p1022ds 694 #define CONFIG_ROOTPATH "/opt/nfsroot" 695 #define CONFIG_BOOTFILE "uImage" 696 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 697 698 #define CONFIG_LOADADDR 1000000 699 700 701 #define CONFIG_BAUDRATE 115200 702 703 #define CONFIG_EXTRA_ENV_SETTINGS \ 704 "netdev=eth0\0" \ 705 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 706 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 707 "tftpflash=tftpboot $loadaddr $uboot && " \ 708 "protect off $ubootaddr +$filesize && " \ 709 "erase $ubootaddr +$filesize && " \ 710 "cp.b $loadaddr $ubootaddr $filesize && " \ 711 "protect on $ubootaddr +$filesize && " \ 712 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 713 "consoledev=ttyS0\0" \ 714 "ramdiskaddr=2000000\0" \ 715 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 716 "fdtaddr=1e00000\0" \ 717 "fdtfile=p1022ds.dtb\0" \ 718 "bdev=sda3\0" \ 719 "hwconfig=esdhc;audclk:12\0" 720 721 #define CONFIG_HDBOOT \ 722 "setenv bootargs root=/dev/$bdev rw " \ 723 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 724 "tftp $loadaddr $bootfile;" \ 725 "tftp $fdtaddr $fdtfile;" \ 726 "bootm $loadaddr - $fdtaddr" 727 728 #define CONFIG_NFSBOOTCOMMAND \ 729 "setenv bootargs root=/dev/nfs rw " \ 730 "nfsroot=$serverip:$rootpath " \ 731 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 732 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 733 "tftp $loadaddr $bootfile;" \ 734 "tftp $fdtaddr $fdtfile;" \ 735 "bootm $loadaddr - $fdtaddr" 736 737 #define CONFIG_RAMBOOTCOMMAND \ 738 "setenv bootargs root=/dev/ram rw " \ 739 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 740 "tftp $ramdiskaddr $ramdiskfile;" \ 741 "tftp $loadaddr $bootfile;" \ 742 "tftp $fdtaddr $fdtfile;" \ 743 "bootm $loadaddr $ramdiskaddr $fdtaddr" 744 745 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 746 747 #endif 748