| a55957b9 | 26-Aug-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Mo
ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the same PLL name. We can not define SC_*PLLCTRL in the common header. Move them to per-SoC .c file. Also, fix some PLL comments.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| c5161eee | 13-Aug-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"
This reverts commit 82d075e79fa509ffb8ecd8dd2dc216929d6e8289.
Commit 82d075e79fa5 ("ARM: uniphier: fix ROM boot mode for PH1-sLD3") was a work
Revert "ARM: uniphier: fix ROM boot mode for PH1-sLD3"
This reverts commit 82d075e79fa509ffb8ecd8dd2dc216929d6e8289.
Commit 82d075e79fa5 ("ARM: uniphier: fix ROM boot mode for PH1-sLD3") was a workaround for sLD3. Now the sLD3 SoC support has been removed.
Revert it to allow to simplify the init code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 0aa8b2c3 | 13-Aug-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Revert "ARM: uniphier: move lowlevel debug init code after page table switch"
This reverts commit bcc51c1512a3deb6a9fdd37362c6dde32ad3da23.
Commit bcc51c1512a3 ("ARM: uniphier: move lowlevel debug
Revert "ARM: uniphier: move lowlevel debug init code after page table switch"
This reverts commit bcc51c1512a3deb6a9fdd37362c6dde32ad3da23.
Commit bcc51c1512a3 ("ARM: uniphier: move lowlevel debug init code after page table switch") was intended to support lowlevel debug for sLD3. Now the sLD3 SoC support has been removed.
Revert it to allow to enable lowlevel debug earlier.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| b8faf5f1 | 13-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: remove part number info from the boot log
As is often the case with SoC development, slightly different products (i.e. different part number) are developed based on the same silicon-d
ARM: uniphier: remove part number info from the boot log
As is often the case with SoC development, slightly different products (i.e. different part number) are developed based on the same silicon-die. Such fine grained information is unmaintainable.
Also, "SoC:" is a better fit that "CPU:".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 45f41c13 | 12-May-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: uniphier: add weird workaround code for LD20
When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS. The boot flow is as follows: BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot)
This boot se
ARM: uniphier: add weird workaround code for LD20
When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS. The boot flow is as follows: BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot)
This boot sequence works fine for LD11 SoC (Cortex-A53), but LD20 SoC (Cortex-A72) hangs in U-Boot. The solution I found is to read sctlr_el1 and write back the value as-is. This should be no effect, but surprisingly fixes the problem for LD20 to boot. I do not know why.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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