1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 36 37 /* support deep sleep */ 38 #ifdef CONFIG_PPC_T1024 39 #define CONFIG_DEEP_SLEEP 40 #endif 41 #if defined(CONFIG_DEEP_SLEEP) 42 #define CONFIG_SILENT_CONSOLE 43 #define CONFIG_BOARD_EARLY_INIT_F 44 #endif 45 46 #ifdef CONFIG_RAMBOOT_PBL 47 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 48 #if defined(CONFIG_T1024RDB) 49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 50 #elif defined(CONFIG_T1023RDB) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 52 #endif 53 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 54 #define CONFIG_SPL_SERIAL_SUPPORT 55 #define CONFIG_SPL_FLUSH_IMAGE 56 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 57 #define CONFIG_FSL_LAW /* Use common FSL init code */ 58 #define CONFIG_SYS_TEXT_BASE 0x30001000 59 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 60 #define CONFIG_SPL_PAD_TO 0x40000 61 #define CONFIG_SPL_MAX_SIZE 0x28000 62 #define RESET_VECTOR_OFFSET 0x27FFC 63 #define BOOT_PAGE_OFFSET 0x27000 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SPL_SKIP_RELOCATE 66 #define CONFIG_SPL_COMMON_INIT_DDR 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #define CONFIG_SYS_NO_FLASH 69 #endif 70 71 #ifdef CONFIG_NAND 72 #define CONFIG_SPL_NAND_SUPPORT 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 75 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 78 #define CONFIG_SPL_NAND_BOOT 79 #endif 80 81 #ifdef CONFIG_SPIFLASH 82 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 83 #define CONFIG_SPL_SPI_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_SUPPORT 85 #define CONFIG_SPL_SPI_FLASH_MINIMAL 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #define CONFIG_SPL_SPI_BOOT 95 #endif 96 97 #ifdef CONFIG_SDCARD 98 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 99 #define CONFIG_SPL_MMC_MINIMAL 100 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 101 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 102 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 103 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 105 #ifndef CONFIG_SPL_BUILD 106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 107 #endif 108 #define CONFIG_SPL_MMC_BOOT 109 #endif 110 111 #endif /* CONFIG_RAMBOOT_PBL */ 112 113 #ifndef CONFIG_SYS_TEXT_BASE 114 #define CONFIG_SYS_TEXT_BASE 0xeff40000 115 #endif 116 117 #ifndef CONFIG_RESET_VECTOR_ADDRESS 118 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 119 #endif 120 121 #ifndef CONFIG_SYS_NO_FLASH 122 #define CONFIG_FLASH_CFI_DRIVER 123 #define CONFIG_SYS_FLASH_CFI 124 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 125 #endif 126 127 /* PCIe Boot - Master */ 128 #define CONFIG_SRIO_PCIE_BOOT_MASTER 129 /* 130 * for slave u-boot IMAGE instored in master memory space, 131 * PHYS must be aligned based on the SIZE 132 */ 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 135 #ifdef CONFIG_PHYS_64BIT 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 138 #else 139 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 141 #endif 142 /* 143 * for slave UCODE and ENV instored in master memory space, 144 * PHYS must be aligned based on the SIZE 145 */ 146 #ifdef CONFIG_PHYS_64BIT 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 149 #else 150 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 152 #endif 153 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 154 /* slave core release by master*/ 155 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 156 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 157 158 /* PCIe Boot - Slave */ 159 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 160 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 162 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 163 /* Set 1M boot space for PCIe boot */ 164 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 165 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 166 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 167 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 168 #define CONFIG_SYS_NO_FLASH 169 #endif 170 171 #if defined(CONFIG_SPIFLASH) 172 #define CONFIG_SYS_EXTRA_ENV_RELOC 173 #define CONFIG_ENV_IS_IN_SPI_FLASH 174 #define CONFIG_ENV_SPI_BUS 0 175 #define CONFIG_ENV_SPI_CS 0 176 #define CONFIG_ENV_SPI_MAX_HZ 10000000 177 #define CONFIG_ENV_SPI_MODE 0 178 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 179 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 180 #if defined(CONFIG_T1024RDB) 181 #define CONFIG_ENV_SECT_SIZE 0x10000 182 #elif defined(CONFIG_T1023RDB) 183 #define CONFIG_ENV_SECT_SIZE 0x40000 184 #endif 185 #elif defined(CONFIG_SDCARD) 186 #define CONFIG_SYS_EXTRA_ENV_RELOC 187 #define CONFIG_ENV_IS_IN_MMC 188 #define CONFIG_SYS_MMC_ENV_DEV 0 189 #define CONFIG_ENV_SIZE 0x2000 190 #define CONFIG_ENV_OFFSET (512 * 0x800) 191 #elif defined(CONFIG_NAND) 192 #define CONFIG_SYS_EXTRA_ENV_RELOC 193 #define CONFIG_ENV_IS_IN_NAND 194 #define CONFIG_ENV_SIZE 0x2000 195 #if defined(CONFIG_T1024RDB) 196 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 197 #elif defined(CONFIG_T1023RDB) 198 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 199 #endif 200 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 201 #define CONFIG_ENV_IS_IN_REMOTE 202 #define CONFIG_ENV_ADDR 0xffe20000 203 #define CONFIG_ENV_SIZE 0x2000 204 #elif defined(CONFIG_ENV_IS_NOWHERE) 205 #define CONFIG_ENV_SIZE 0x2000 206 #else 207 #define CONFIG_ENV_IS_IN_FLASH 208 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 209 #define CONFIG_ENV_SIZE 0x2000 210 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 211 #endif 212 213 #ifndef __ASSEMBLY__ 214 unsigned long get_board_sys_clk(void); 215 unsigned long get_board_ddr_clk(void); 216 #endif 217 218 #define CONFIG_SYS_CLK_FREQ 100000000 219 #define CONFIG_DDR_CLK_FREQ 100000000 220 221 /* 222 * These can be toggled for performance analysis, otherwise use default. 223 */ 224 #define CONFIG_SYS_CACHE_STASHING 225 #define CONFIG_BACKSIDE_L2_CACHE 226 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 227 #define CONFIG_BTB /* toggle branch predition */ 228 #define CONFIG_DDR_ECC 229 #ifdef CONFIG_DDR_ECC 230 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 231 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 232 #endif 233 234 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 235 #define CONFIG_SYS_MEMTEST_END 0x00400000 236 #define CONFIG_SYS_ALT_MEMTEST 237 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 238 239 /* 240 * Config the L3 Cache as L3 SRAM 241 */ 242 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 243 #define CONFIG_SYS_L3_SIZE (256 << 10) 244 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 245 #ifdef CONFIG_RAMBOOT_PBL 246 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 247 #endif 248 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 249 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 250 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 251 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 252 253 #ifdef CONFIG_PHYS_64BIT 254 #define CONFIG_SYS_DCSRBAR 0xf0000000 255 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 256 #endif 257 258 /* EEPROM */ 259 #define CONFIG_ID_EEPROM 260 #define CONFIG_SYS_I2C_EEPROM_NXID 261 #define CONFIG_SYS_EEPROM_BUS_NUM 0 262 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 263 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 264 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 265 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 266 267 /* 268 * DDR Setup 269 */ 270 #define CONFIG_VERY_BIG_RAM 271 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 272 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 273 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 274 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 275 #define CONFIG_FSL_DDR_INTERACTIVE 276 #if defined(CONFIG_T1024RDB) 277 #define CONFIG_DDR_SPD 278 #define CONFIG_SYS_FSL_DDR3 279 #define CONFIG_SYS_SPD_BUS_NUM 0 280 #define SPD_EEPROM_ADDRESS 0x51 281 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 282 #elif defined(CONFIG_T1023RDB) 283 #define CONFIG_SYS_FSL_DDR4 284 #define CONFIG_SYS_DDR_RAW_TIMING 285 #define CONFIG_SYS_SDRAM_SIZE 2048 286 #endif 287 288 /* 289 * IFC Definitions 290 */ 291 #define CONFIG_SYS_FLASH_BASE 0xe8000000 292 #ifdef CONFIG_PHYS_64BIT 293 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 294 #else 295 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 296 #endif 297 298 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 299 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 300 CSPR_PORT_SIZE_16 | \ 301 CSPR_MSEL_NOR | \ 302 CSPR_V) 303 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 304 305 /* NOR Flash Timing Params */ 306 #if defined(CONFIG_T1024RDB) 307 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 308 #elif defined(CONFIG_T1023RDB) 309 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 310 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 311 #endif 312 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 313 FTIM0_NOR_TEADC(0x5) | \ 314 FTIM0_NOR_TEAHC(0x5)) 315 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 316 FTIM1_NOR_TRAD_NOR(0x1A) |\ 317 FTIM1_NOR_TSEQRAD_NOR(0x13)) 318 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 319 FTIM2_NOR_TCH(0x4) | \ 320 FTIM2_NOR_TWPH(0x0E) | \ 321 FTIM2_NOR_TWP(0x1c)) 322 #define CONFIG_SYS_NOR_FTIM3 0x0 323 324 #define CONFIG_SYS_FLASH_QUIET_TEST 325 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 326 327 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 328 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 329 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 330 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 331 332 #define CONFIG_SYS_FLASH_EMPTY_INFO 333 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 334 335 #ifdef CONFIG_T1024RDB 336 /* CPLD on IFC */ 337 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 338 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 339 #define CONFIG_SYS_CSPR2_EXT (0xf) 340 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 341 | CSPR_PORT_SIZE_8 \ 342 | CSPR_MSEL_GPCM \ 343 | CSPR_V) 344 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 345 #define CONFIG_SYS_CSOR2 0x0 346 347 /* CPLD Timing parameters for IFC CS2 */ 348 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 349 FTIM0_GPCM_TEADC(0x0e) | \ 350 FTIM0_GPCM_TEAHC(0x0e)) 351 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 352 FTIM1_GPCM_TRAD(0x1f)) 353 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 354 FTIM2_GPCM_TCH(0x8) | \ 355 FTIM2_GPCM_TWP(0x1f)) 356 #define CONFIG_SYS_CS2_FTIM3 0x0 357 #endif 358 359 /* NAND Flash on IFC */ 360 #define CONFIG_NAND_FSL_IFC 361 #define CONFIG_SYS_NAND_BASE 0xff800000 362 #ifdef CONFIG_PHYS_64BIT 363 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 364 #else 365 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 366 #endif 367 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 368 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 369 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 370 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 371 | CSPR_V) 372 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 373 374 #if defined(CONFIG_T1024RDB) 375 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 376 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 377 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 378 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 379 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 380 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 381 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 382 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 383 #elif defined(CONFIG_T1023RDB) 384 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 385 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 386 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 387 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 388 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 389 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 390 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 391 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 392 #endif 393 394 #define CONFIG_SYS_NAND_ONFI_DETECTION 395 /* ONFI NAND Flash mode0 Timing Params */ 396 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 397 FTIM0_NAND_TWP(0x18) | \ 398 FTIM0_NAND_TWCHT(0x07) | \ 399 FTIM0_NAND_TWH(0x0a)) 400 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 401 FTIM1_NAND_TWBE(0x39) | \ 402 FTIM1_NAND_TRR(0x0e) | \ 403 FTIM1_NAND_TRP(0x18)) 404 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 405 FTIM2_NAND_TREH(0x0a) | \ 406 FTIM2_NAND_TWHRE(0x1e)) 407 #define CONFIG_SYS_NAND_FTIM3 0x0 408 409 #define CONFIG_SYS_NAND_DDR_LAW 11 410 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 411 #define CONFIG_SYS_MAX_NAND_DEVICE 1 412 #define CONFIG_CMD_NAND 413 414 #if defined(CONFIG_NAND) 415 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 416 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 417 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 418 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 419 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 420 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 421 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 422 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 423 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 424 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 425 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 426 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 427 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 428 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 429 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 430 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 431 #else 432 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 433 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 434 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 435 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 436 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 437 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 438 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 439 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 440 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 441 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 442 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 443 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 444 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 445 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 446 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 447 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 448 #endif 449 450 #ifdef CONFIG_SPL_BUILD 451 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 452 #else 453 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 454 #endif 455 456 #if defined(CONFIG_RAMBOOT_PBL) 457 #define CONFIG_SYS_RAMBOOT 458 #endif 459 460 #define CONFIG_BOARD_EARLY_INIT_R 461 #define CONFIG_MISC_INIT_R 462 463 #define CONFIG_HWCONFIG 464 465 /* define to use L1 as initial stack */ 466 #define CONFIG_L1_INIT_RAM 467 #define CONFIG_SYS_INIT_RAM_LOCK 468 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 472 /* The assembler doesn't like typecast */ 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 474 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 475 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 476 #else 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 480 #endif 481 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 482 483 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 484 GENERATED_GBL_DATA_SIZE) 485 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 486 487 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 488 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 489 490 /* Serial Port */ 491 #define CONFIG_CONS_INDEX 1 492 #define CONFIG_SYS_NS16550_SERIAL 493 #define CONFIG_SYS_NS16550_REG_SIZE 1 494 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 495 496 #define CONFIG_SYS_BAUDRATE_TABLE \ 497 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 498 499 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 500 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 501 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 502 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 503 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 504 505 /* Video */ 506 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 507 #ifdef CONFIG_FSL_DIU_FB 508 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 509 #define CONFIG_VIDEO 510 #define CONFIG_CMD_BMP 511 #define CONFIG_CFB_CONSOLE 512 #define CONFIG_VIDEO_SW_CURSOR 513 #define CONFIG_VGA_AS_SINGLE_DEVICE 514 #define CONFIG_VIDEO_LOGO 515 #define CONFIG_VIDEO_BMP_LOGO 516 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 517 /* 518 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 519 * disable empty flash sector detection, which is I/O-intensive. 520 */ 521 #undef CONFIG_SYS_FLASH_EMPTY_INFO 522 #endif 523 524 /* I2C */ 525 #define CONFIG_SYS_I2C 526 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 527 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 528 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 529 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 530 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 531 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 532 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 533 534 #define I2C_PCA6408_BUS_NUM 1 535 #define I2C_PCA6408_ADDR 0x20 536 537 /* I2C bus multiplexer */ 538 #define I2C_MUX_CH_DEFAULT 0x8 539 540 /* 541 * RTC configuration 542 */ 543 #define RTC 544 #define CONFIG_RTC_DS1337 1 545 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 546 547 /* 548 * eSPI - Enhanced SPI 549 */ 550 #define CONFIG_SPI_FLASH_BAR 551 #define CONFIG_SF_DEFAULT_SPEED 10000000 552 #define CONFIG_SF_DEFAULT_MODE 0 553 554 /* 555 * General PCIe 556 * Memory space is mapped 1-1, but I/O space must start from 0. 557 */ 558 #define CONFIG_PCI /* Enable PCI/PCIE */ 559 #define CONFIG_PCIE1 /* PCIE controller 1 */ 560 #define CONFIG_PCIE2 /* PCIE controller 2 */ 561 #define CONFIG_PCIE3 /* PCIE controller 3 */ 562 #ifdef CONFIG_PPC_T1040 563 #define CONFIG_PCIE4 /* PCIE controller 4 */ 564 #endif 565 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 566 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 567 #define CONFIG_PCI_INDIRECT_BRIDGE 568 569 #ifdef CONFIG_PCI 570 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 571 #ifdef CONFIG_PCIE1 572 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 573 #ifdef CONFIG_PHYS_64BIT 574 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 575 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 576 #else 577 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 578 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 579 #endif 580 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 581 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 582 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 583 #ifdef CONFIG_PHYS_64BIT 584 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 585 #else 586 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 587 #endif 588 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 589 #endif 590 591 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 592 #ifdef CONFIG_PCIE2 593 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 594 #ifdef CONFIG_PHYS_64BIT 595 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 596 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 597 #else 598 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 599 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 600 #endif 601 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 602 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 603 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 606 #else 607 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 608 #endif 609 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 610 #endif 611 612 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 613 #ifdef CONFIG_PCIE3 614 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 615 #ifdef CONFIG_PHYS_64BIT 616 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 617 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 618 #else 619 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 620 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 621 #endif 622 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 623 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 624 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 625 #ifdef CONFIG_PHYS_64BIT 626 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 627 #else 628 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 629 #endif 630 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 631 #endif 632 633 /* controller 4, Base address 203000, to be removed */ 634 #ifdef CONFIG_PCIE4 635 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 636 #ifdef CONFIG_PHYS_64BIT 637 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 638 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 639 #else 640 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 641 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 642 #endif 643 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 644 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 645 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 646 #ifdef CONFIG_PHYS_64BIT 647 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 648 #else 649 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 650 #endif 651 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 652 #endif 653 654 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 655 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 656 #define CONFIG_DOS_PARTITION 657 #endif /* CONFIG_PCI */ 658 659 /* 660 * USB 661 */ 662 #define CONFIG_HAS_FSL_DR_USB 663 664 #ifdef CONFIG_HAS_FSL_DR_USB 665 #define CONFIG_USB_EHCI 666 #define CONFIG_USB_EHCI_FSL 667 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 668 #endif 669 670 /* 671 * SDHC 672 */ 673 #define CONFIG_MMC 674 #ifdef CONFIG_MMC 675 #define CONFIG_FSL_ESDHC 676 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 677 #define CONFIG_GENERIC_MMC 678 #define CONFIG_DOS_PARTITION 679 #endif 680 681 /* Qman/Bman */ 682 #ifndef CONFIG_NOBQFMAN 683 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 684 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 685 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 686 #ifdef CONFIG_PHYS_64BIT 687 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 688 #else 689 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 690 #endif 691 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 692 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 693 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 694 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 695 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 696 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 697 CONFIG_SYS_BMAN_CENA_SIZE) 698 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 699 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 700 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 701 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 702 #ifdef CONFIG_PHYS_64BIT 703 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 704 #else 705 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 706 #endif 707 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 708 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 709 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 710 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 711 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 712 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 713 CONFIG_SYS_QMAN_CENA_SIZE) 714 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 715 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 716 717 #define CONFIG_SYS_DPAA_FMAN 718 719 #ifdef CONFIG_T1024RDB 720 #define CONFIG_QE 721 #define CONFIG_U_QE 722 #endif 723 /* Default address of microcode for the Linux FMan driver */ 724 #if defined(CONFIG_SPIFLASH) 725 /* 726 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 727 * env, so we got 0x110000. 728 */ 729 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 730 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 731 #define CONFIG_SYS_QE_FW_ADDR 0x130000 732 #elif defined(CONFIG_SDCARD) 733 /* 734 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 735 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 736 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 737 */ 738 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 739 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 740 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 741 #elif defined(CONFIG_NAND) 742 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 743 #if defined(CONFIG_T1024RDB) 744 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 745 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 746 #elif defined(CONFIG_T1023RDB) 747 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 748 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 749 #endif 750 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 751 /* 752 * Slave has no ucode locally, it can fetch this from remote. When implementing 753 * in two corenet boards, slave's ucode could be stored in master's memory 754 * space, the address can be mapped from slave TLB->slave LAW-> 755 * slave SRIO or PCIE outbound window->master inbound window-> 756 * master LAW->the ucode address in master's memory space. 757 */ 758 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 759 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 760 #else 761 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 762 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 763 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 764 #endif 765 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 766 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 767 #endif /* CONFIG_NOBQFMAN */ 768 769 #ifdef CONFIG_SYS_DPAA_FMAN 770 #define CONFIG_FMAN_ENET 771 #define CONFIG_PHYLIB_10G 772 #define CONFIG_PHY_REALTEK 773 #define CONFIG_PHY_AQUANTIA 774 #if defined(CONFIG_T1024RDB) 775 #define RGMII_PHY1_ADDR 0x2 776 #define RGMII_PHY2_ADDR 0x6 777 #define SGMII_AQR_PHY_ADDR 0x2 778 #define FM1_10GEC1_PHY_ADDR 0x1 779 #elif defined(CONFIG_T1023RDB) 780 #define RGMII_PHY1_ADDR 0x1 781 #define SGMII_RTK_PHY_ADDR 0x3 782 #define SGMII_AQR_PHY_ADDR 0x2 783 #endif 784 #endif 785 786 #ifdef CONFIG_FMAN_ENET 787 #define CONFIG_MII /* MII PHY management */ 788 #define CONFIG_ETHPRIME "FM1@DTSEC4" 789 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 790 #endif 791 792 /* 793 * Dynamic MTD Partition support with mtdparts 794 */ 795 #ifndef CONFIG_SYS_NO_FLASH 796 #define CONFIG_MTD_DEVICE 797 #define CONFIG_MTD_PARTITIONS 798 #define CONFIG_CMD_MTDPARTS 799 #define CONFIG_FLASH_CFI_MTD 800 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 801 "spi0=spife110000.1" 802 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 803 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 804 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 805 "1m(uboot),5m(kernel),128k(dtb),-(user)" 806 #endif 807 808 /* 809 * Environment 810 */ 811 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 812 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 813 814 /* 815 * Command line configuration. 816 */ 817 #define CONFIG_CMD_DATE 818 #define CONFIG_CMD_EEPROM 819 #define CONFIG_CMD_ERRATA 820 #define CONFIG_CMD_IRQ 821 #define CONFIG_CMD_REGINFO 822 823 #ifdef CONFIG_PCI 824 #define CONFIG_CMD_PCI 825 #endif 826 827 /* 828 * Miscellaneous configurable options 829 */ 830 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 831 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 832 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 833 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 834 #ifdef CONFIG_CMD_KGDB 835 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 836 #else 837 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 838 #endif 839 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 840 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 841 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 842 843 /* 844 * For booting Linux, the board info and command line data 845 * have to be in the first 64 MB of memory, since this is 846 * the maximum mapped by the Linux kernel during initialization. 847 */ 848 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 849 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 850 851 #ifdef CONFIG_CMD_KGDB 852 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 853 #endif 854 855 /* 856 * Environment Configuration 857 */ 858 #define CONFIG_ROOTPATH "/opt/nfsroot" 859 #define CONFIG_BOOTFILE "uImage" 860 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 861 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 862 #define CONFIG_BAUDRATE 115200 863 #define __USB_PHY_TYPE utmi 864 865 #ifdef CONFIG_PPC_T1024 866 #define CONFIG_BOARDNAME t1024rdb 867 #define BANK_INTLV cs0_cs1 868 #else 869 #define CONFIG_BOARDNAME t1023rdb 870 #define BANK_INTLV null 871 #endif 872 873 #define CONFIG_EXTRA_ENV_SETTINGS \ 874 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 875 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 876 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 877 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 878 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 879 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 880 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 881 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 882 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 883 "netdev=eth0\0" \ 884 "tftpflash=tftpboot $loadaddr $uboot && " \ 885 "protect off $ubootaddr +$filesize && " \ 886 "erase $ubootaddr +$filesize && " \ 887 "cp.b $loadaddr $ubootaddr $filesize && " \ 888 "protect on $ubootaddr +$filesize && " \ 889 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 890 "consoledev=ttyS0\0" \ 891 "ramdiskaddr=2000000\0" \ 892 "fdtaddr=1e00000\0" \ 893 "bdev=sda3\0" 894 895 #define CONFIG_LINUX \ 896 "setenv bootargs root=/dev/ram rw " \ 897 "console=$consoledev,$baudrate $othbootargs;" \ 898 "setenv ramdiskaddr 0x02000000;" \ 899 "setenv fdtaddr 0x00c00000;" \ 900 "setenv loadaddr 0x1000000;" \ 901 "bootm $loadaddr $ramdiskaddr $fdtaddr" 902 903 #define CONFIG_NFSBOOTCOMMAND \ 904 "setenv bootargs root=/dev/nfs rw " \ 905 "nfsroot=$serverip:$rootpath " \ 906 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 907 "console=$consoledev,$baudrate $othbootargs;" \ 908 "tftp $loadaddr $bootfile;" \ 909 "tftp $fdtaddr $fdtfile;" \ 910 "bootm $loadaddr - $fdtaddr" 911 912 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 913 914 /* Hash command with SHA acceleration supported in hardware */ 915 #ifdef CONFIG_FSL_CAAM 916 #define CONFIG_CMD_HASH 917 #define CONFIG_SHA_HW_ACCEL 918 #endif 919 920 #include <asm/fsl_secure_boot.h> 921 922 #endif /* __T1024RDB_H */ 923