1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 QDS board configuration file 9 */ 10 11 #ifndef __T1024QDS_H 12 #define __T1024QDS_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_DEEP_SLEEP 36 #if defined(CONFIG_DEEP_SLEEP) 37 #define CONFIG_SILENT_CONSOLE 38 #define CONFIG_BOARD_EARLY_INIT_F 39 #endif 40 41 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_SPL_LIBGENERIC_SUPPORT 51 #define CONFIG_FSL_LAW /* Use common FSL init code */ 52 #define CONFIG_SYS_TEXT_BASE 0x00201000 53 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 54 #define CONFIG_SPL_PAD_TO 0x40000 55 #define CONFIG_SPL_MAX_SIZE 0x28000 56 #define RESET_VECTOR_OFFSET 0x27FFC 57 #define BOOT_PAGE_OFFSET 0x27000 58 #ifdef CONFIG_SPL_BUILD 59 #define CONFIG_SPL_SKIP_RELOCATE 60 #define CONFIG_SPL_COMMON_INIT_DDR 61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 62 #define CONFIG_SYS_NO_FLASH 63 #endif 64 65 #ifdef CONFIG_NAND 66 #define CONFIG_SPL_NAND_SUPPORT 67 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 68 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 69 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 70 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 72 #define CONFIG_SPL_NAND_BOOT 73 #endif 74 75 #ifdef CONFIG_SPIFLASH 76 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 77 #define CONFIG_SPL_SPI_SUPPORT 78 #define CONFIG_SPL_SPI_FLASH_SUPPORT 79 #define CONFIG_SPL_SPI_FLASH_MINIMAL 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 85 #ifndef CONFIG_SPL_BUILD 86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 87 #endif 88 #define CONFIG_SPL_SPI_BOOT 89 #endif 90 91 #ifdef CONFIG_SDCARD 92 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 93 #define CONFIG_SPL_MMC_SUPPORT 94 #define CONFIG_SPL_MMC_MINIMAL 95 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 96 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 97 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 98 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 99 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 100 #ifndef CONFIG_SPL_BUILD 101 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 102 #endif 103 #define CONFIG_SPL_MMC_BOOT 104 #endif 105 106 #endif /* CONFIG_RAMBOOT_PBL */ 107 108 #ifndef CONFIG_SYS_TEXT_BASE 109 #define CONFIG_SYS_TEXT_BASE 0xeff40000 110 #endif 111 112 #ifndef CONFIG_RESET_VECTOR_ADDRESS 113 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 114 #endif 115 116 #ifndef CONFIG_SYS_NO_FLASH 117 #define CONFIG_FLASH_CFI_DRIVER 118 #define CONFIG_SYS_FLASH_CFI 119 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 120 #endif 121 122 /* PCIe Boot - Master */ 123 #define CONFIG_SRIO_PCIE_BOOT_MASTER 124 /* 125 * for slave u-boot IMAGE instored in master memory space, 126 * PHYS must be aligned based on the SIZE 127 */ 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 129 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 130 #ifdef CONFIG_PHYS_64BIT 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 132 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 133 #else 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 136 #endif 137 /* 138 * for slave UCODE and ENV instored in master memory space, 139 * PHYS must be aligned based on the SIZE 140 */ 141 #ifdef CONFIG_PHYS_64BIT 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 143 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 144 #else 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 146 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 147 #endif 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 149 /* slave core release by master*/ 150 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 151 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 152 153 /* PCIe Boot - Slave */ 154 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 158 /* Set 1M boot space for PCIe boot */ 159 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 160 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 161 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 162 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 163 #define CONFIG_SYS_NO_FLASH 164 #endif 165 166 #if defined(CONFIG_SPIFLASH) 167 #define CONFIG_SYS_EXTRA_ENV_RELOC 168 #define CONFIG_ENV_IS_IN_SPI_FLASH 169 #define CONFIG_ENV_SPI_BUS 0 170 #define CONFIG_ENV_SPI_CS 0 171 #define CONFIG_ENV_SPI_MAX_HZ 10000000 172 #define CONFIG_ENV_SPI_MODE 0 173 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 174 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 175 #define CONFIG_ENV_SECT_SIZE 0x10000 176 #elif defined(CONFIG_SDCARD) 177 #define CONFIG_SYS_EXTRA_ENV_RELOC 178 #define CONFIG_ENV_IS_IN_MMC 179 #define CONFIG_SYS_MMC_ENV_DEV 0 180 #define CONFIG_ENV_SIZE 0x2000 181 #define CONFIG_ENV_OFFSET (512 * 0x800) 182 #elif defined(CONFIG_NAND) 183 #define CONFIG_SYS_EXTRA_ENV_RELOC 184 #define CONFIG_ENV_IS_IN_NAND 185 #define CONFIG_ENV_SIZE 0x2000 186 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 187 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 188 #define CONFIG_ENV_IS_IN_REMOTE 189 #define CONFIG_ENV_ADDR 0xffe20000 190 #define CONFIG_ENV_SIZE 0x2000 191 #elif defined(CONFIG_ENV_IS_NOWHERE) 192 #define CONFIG_ENV_SIZE 0x2000 193 #else 194 #define CONFIG_ENV_IS_IN_FLASH 195 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 196 #define CONFIG_ENV_SIZE 0x2000 197 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 198 #endif 199 200 #ifndef __ASSEMBLY__ 201 unsigned long get_board_sys_clk(void); 202 unsigned long get_board_ddr_clk(void); 203 #endif 204 205 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 206 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 207 208 /* 209 * These can be toggled for performance analysis, otherwise use default. 210 */ 211 #define CONFIG_SYS_CACHE_STASHING 212 #define CONFIG_BACKSIDE_L2_CACHE 213 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 214 #define CONFIG_BTB /* toggle branch predition */ 215 #define CONFIG_DDR_ECC 216 #ifdef CONFIG_DDR_ECC 217 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 218 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 219 #endif 220 221 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 222 #define CONFIG_SYS_MEMTEST_END 0x00400000 223 #define CONFIG_SYS_ALT_MEMTEST 224 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 225 226 /* 227 * Config the L3 Cache as L3 SRAM 228 */ 229 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 230 #define CONFIG_SYS_L3_SIZE (256 << 10) 231 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 232 #ifdef CONFIG_RAMBOOT_PBL 233 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 234 #endif 235 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 236 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 237 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 238 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 239 240 #ifdef CONFIG_PHYS_64BIT 241 #define CONFIG_SYS_DCSRBAR 0xf0000000 242 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 243 #endif 244 245 /* EEPROM */ 246 #define CONFIG_ID_EEPROM 247 #define CONFIG_SYS_I2C_EEPROM_NXID 248 #define CONFIG_SYS_EEPROM_BUS_NUM 0 249 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 250 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 251 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 253 254 /* 255 * DDR Setup 256 */ 257 #define CONFIG_VERY_BIG_RAM 258 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 259 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 260 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 261 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 262 #define CONFIG_DDR_SPD 263 #ifndef CONFIG_SYS_FSL_DDR4 264 #define CONFIG_SYS_FSL_DDR3 265 #endif 266 267 #define CONFIG_SYS_SPD_BUS_NUM 0 268 #define SPD_EEPROM_ADDRESS 0x51 269 270 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 271 272 /* 273 * IFC Definitions 274 */ 275 #define CONFIG_SYS_FLASH_BASE 0xe0000000 276 #ifdef CONFIG_PHYS_64BIT 277 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 278 #else 279 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 280 #endif 281 282 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 283 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 284 + 0x8000000) | \ 285 CSPR_PORT_SIZE_16 | \ 286 CSPR_MSEL_NOR | \ 287 CSPR_V) 288 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 289 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 290 CSPR_PORT_SIZE_16 | \ 291 CSPR_MSEL_NOR | \ 292 CSPR_V) 293 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 294 /* NOR Flash Timing Params */ 295 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 296 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 297 FTIM0_NOR_TEADC(0x5) | \ 298 FTIM0_NOR_TEAHC(0x5)) 299 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 300 FTIM1_NOR_TRAD_NOR(0x1A) |\ 301 FTIM1_NOR_TSEQRAD_NOR(0x13)) 302 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 303 FTIM2_NOR_TCH(0x4) | \ 304 FTIM2_NOR_TWPH(0x0E) | \ 305 FTIM2_NOR_TWP(0x1c)) 306 #define CONFIG_SYS_NOR_FTIM3 0x0 307 308 #define CONFIG_SYS_FLASH_QUIET_TEST 309 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 310 311 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 312 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 313 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 314 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 315 316 #define CONFIG_SYS_FLASH_EMPTY_INFO 317 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 318 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 319 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 320 #define QIXIS_BASE 0xffdf0000 321 #ifdef CONFIG_PHYS_64BIT 322 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 323 #else 324 #define QIXIS_BASE_PHYS QIXIS_BASE 325 #endif 326 #define QIXIS_LBMAP_SWITCH 0x06 327 #define QIXIS_LBMAP_MASK 0x0f 328 #define QIXIS_LBMAP_SHIFT 0 329 #define QIXIS_LBMAP_DFLTBANK 0x00 330 #define QIXIS_LBMAP_ALTBANK 0x04 331 #define QIXIS_RST_CTL_RESET 0x31 332 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 333 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 334 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 335 #define QIXIS_RST_FORCE_MEM 0x01 336 337 #define CONFIG_SYS_CSPR3_EXT (0xf) 338 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 339 | CSPR_PORT_SIZE_8 \ 340 | CSPR_MSEL_GPCM \ 341 | CSPR_V) 342 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 343 #define CONFIG_SYS_CSOR3 0x0 344 /* QIXIS Timing parameters for IFC CS3 */ 345 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 346 FTIM0_GPCM_TEADC(0x0e) | \ 347 FTIM0_GPCM_TEAHC(0x0e)) 348 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 349 FTIM1_GPCM_TRAD(0x3f)) 350 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 351 FTIM2_GPCM_TCH(0x8) | \ 352 FTIM2_GPCM_TWP(0x1f)) 353 #define CONFIG_SYS_CS3_FTIM3 0x0 354 355 #define CONFIG_NAND_FSL_IFC 356 #define CONFIG_SYS_NAND_BASE 0xff800000 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 359 #else 360 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 361 #endif 362 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 363 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 364 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 365 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 366 | CSPR_V) 367 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 368 369 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 370 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 371 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 372 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 373 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 374 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 375 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 376 377 #define CONFIG_SYS_NAND_ONFI_DETECTION 378 379 /* ONFI NAND Flash mode0 Timing Params */ 380 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 381 FTIM0_NAND_TWP(0x18) | \ 382 FTIM0_NAND_TWCHT(0x07) | \ 383 FTIM0_NAND_TWH(0x0a)) 384 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 385 FTIM1_NAND_TWBE(0x39) | \ 386 FTIM1_NAND_TRR(0x0e) | \ 387 FTIM1_NAND_TRP(0x18)) 388 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 389 FTIM2_NAND_TREH(0x0a) | \ 390 FTIM2_NAND_TWHRE(0x1e)) 391 #define CONFIG_SYS_NAND_FTIM3 0x0 392 393 #define CONFIG_SYS_NAND_DDR_LAW 11 394 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 395 #define CONFIG_SYS_MAX_NAND_DEVICE 1 396 #define CONFIG_CMD_NAND 397 398 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 399 400 #if defined(CONFIG_NAND) 401 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 402 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 403 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 404 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 405 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 406 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 407 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 408 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 409 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 410 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 411 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 412 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 413 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 414 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 415 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 416 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 417 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 418 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 419 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 420 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 421 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 422 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 423 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 424 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 425 #else 426 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 427 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 428 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 429 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 430 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 431 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 432 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 433 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 434 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 435 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 436 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 437 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 438 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 439 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 440 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 441 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 442 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 443 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 444 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 445 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 446 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 447 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 448 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 449 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 450 #endif 451 452 #ifdef CONFIG_SPL_BUILD 453 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 454 #else 455 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 456 #endif 457 458 #if defined(CONFIG_RAMBOOT_PBL) 459 #define CONFIG_SYS_RAMBOOT 460 #endif 461 462 #define CONFIG_BOARD_EARLY_INIT_R 463 #define CONFIG_MISC_INIT_R 464 465 #define CONFIG_HWCONFIG 466 467 /* define to use L1 as initial stack */ 468 #define CONFIG_L1_INIT_RAM 469 #define CONFIG_SYS_INIT_RAM_LOCK 470 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 474 /* The assembler doesn't like typecast */ 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 476 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 477 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 478 #else 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 481 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 482 #endif 483 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 484 485 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 486 GENERATED_GBL_DATA_SIZE) 487 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 488 489 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 490 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 491 492 /* Serial Port */ 493 #define CONFIG_CONS_INDEX 1 494 #define CONFIG_SYS_NS16550_SERIAL 495 #define CONFIG_SYS_NS16550_REG_SIZE 1 496 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 497 498 #define CONFIG_SYS_BAUDRATE_TABLE \ 499 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 500 501 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 502 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 503 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 504 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 505 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 506 507 /* Video */ 508 #ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */ 509 #define CONFIG_FSL_DIU_FB 510 #ifdef CONFIG_FSL_DIU_FB 511 #define CONFIG_FSL_DIU_CH7301 512 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 513 #define CONFIG_VIDEO 514 #define CONFIG_CMD_BMP 515 #define CONFIG_CFB_CONSOLE 516 #define CONFIG_VIDEO_SW_CURSOR 517 #define CONFIG_VGA_AS_SINGLE_DEVICE 518 #define CONFIG_VIDEO_LOGO 519 #define CONFIG_VIDEO_BMP_LOGO 520 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 521 /* 522 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 523 * disable empty flash sector detection, which is I/O-intensive. 524 */ 525 #undef CONFIG_SYS_FLASH_EMPTY_INFO 526 #endif 527 #endif 528 529 /* I2C */ 530 #define CONFIG_SYS_I2C 531 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 532 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 533 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 534 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 535 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 536 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 537 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 538 539 #define I2C_MUX_PCA_ADDR 0x77 540 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 541 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 542 #define I2C_RETIMER_ADDR 0x18 543 544 /* I2C bus multiplexer */ 545 #define I2C_MUX_CH_DEFAULT 0x8 546 #define I2C_MUX_CH_DIU 0xC 547 #define I2C_MUX_CH5 0xD 548 #define I2C_MUX_CH7 0xF 549 550 /* LDI/DVI Encoder for display */ 551 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 552 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 553 554 /* 555 * RTC configuration 556 */ 557 #define RTC 558 #define CONFIG_RTC_DS3231 1 559 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 560 561 /* 562 * eSPI - Enhanced SPI 563 */ 564 #ifndef CONFIG_SPL_BUILD 565 #endif 566 #define CONFIG_SPI_FLASH_BAR 567 #define CONFIG_SF_DEFAULT_SPEED 10000000 568 #define CONFIG_SF_DEFAULT_MODE 0 569 570 /* 571 * General PCIe 572 * Memory space is mapped 1-1, but I/O space must start from 0. 573 */ 574 #define CONFIG_PCI /* Enable PCI/PCIE */ 575 #define CONFIG_PCIE1 /* PCIE controller 1 */ 576 #define CONFIG_PCIE2 /* PCIE controller 2 */ 577 #define CONFIG_PCIE3 /* PCIE controller 3 */ 578 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 579 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 580 #define CONFIG_PCI_INDIRECT_BRIDGE 581 582 #ifdef CONFIG_PCI 583 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 584 #ifdef CONFIG_PCIE1 585 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 586 #ifdef CONFIG_PHYS_64BIT 587 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 588 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 589 #else 590 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 591 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 592 #endif 593 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 594 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 595 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 596 #ifdef CONFIG_PHYS_64BIT 597 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 598 #else 599 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 600 #endif 601 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 602 #endif 603 604 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 605 #ifdef CONFIG_PCIE2 606 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 607 #ifdef CONFIG_PHYS_64BIT 608 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 609 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 610 #else 611 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 612 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 613 #endif 614 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 615 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 616 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 617 #ifdef CONFIG_PHYS_64BIT 618 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 619 #else 620 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 621 #endif 622 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 623 #endif 624 625 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 626 #ifdef CONFIG_PCIE3 627 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 628 #ifdef CONFIG_PHYS_64BIT 629 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 630 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 631 #else 632 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 633 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 634 #endif 635 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 636 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 637 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 638 #ifdef CONFIG_PHYS_64BIT 639 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 640 #else 641 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 642 #endif 643 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 644 #endif 645 646 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 647 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 648 #define CONFIG_DOS_PARTITION 649 #endif /* CONFIG_PCI */ 650 651 /* 652 *SATA 653 */ 654 #define CONFIG_FSL_SATA_V2 655 #ifdef CONFIG_FSL_SATA_V2 656 #define CONFIG_LIBATA 657 #define CONFIG_FSL_SATA 658 #define CONFIG_SYS_SATA_MAX_DEVICE 1 659 #define CONFIG_SATA1 660 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 661 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 662 #define CONFIG_LBA48 663 #define CONFIG_CMD_SATA 664 #define CONFIG_DOS_PARTITION 665 #endif 666 667 /* 668 * USB 669 */ 670 #define CONFIG_HAS_FSL_DR_USB 671 672 #ifdef CONFIG_HAS_FSL_DR_USB 673 #define CONFIG_USB_EHCI 674 #define CONFIG_USB_EHCI_FSL 675 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 676 #endif 677 678 /* 679 * SDHC 680 */ 681 #define CONFIG_MMC 682 #ifdef CONFIG_MMC 683 #define CONFIG_FSL_ESDHC 684 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 685 #define CONFIG_GENERIC_MMC 686 #define CONFIG_DOS_PARTITION 687 #endif 688 689 /* Qman/Bman */ 690 #ifndef CONFIG_NOBQFMAN 691 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 692 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 693 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 694 #ifdef CONFIG_PHYS_64BIT 695 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 696 #else 697 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 698 #endif 699 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 700 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 701 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 702 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 703 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 704 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 705 CONFIG_SYS_BMAN_CENA_SIZE) 706 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 707 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 708 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 709 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 710 #ifdef CONFIG_PHYS_64BIT 711 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 712 #else 713 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 714 #endif 715 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 716 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 717 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 718 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 719 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 720 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 721 CONFIG_SYS_QMAN_CENA_SIZE) 722 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 723 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 724 725 #define CONFIG_SYS_DPAA_FMAN 726 727 #define CONFIG_QE 728 #define CONFIG_U_QE 729 /* Default address of microcode for the Linux FMan driver */ 730 #if defined(CONFIG_SPIFLASH) 731 /* 732 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 733 * env, so we got 0x110000. 734 */ 735 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 736 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 737 #define CONFIG_SYS_QE_FW_ADDR 0x130000 738 #elif defined(CONFIG_SDCARD) 739 /* 740 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 741 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 742 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 743 */ 744 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 745 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 746 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 747 #elif defined(CONFIG_NAND) 748 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 749 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 750 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 751 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 752 /* 753 * Slave has no ucode locally, it can fetch this from remote. When implementing 754 * in two corenet boards, slave's ucode could be stored in master's memory 755 * space, the address can be mapped from slave TLB->slave LAW-> 756 * slave SRIO or PCIE outbound window->master inbound window-> 757 * master LAW->the ucode address in master's memory space. 758 */ 759 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 760 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 761 #else 762 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 763 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 764 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 765 #endif 766 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 767 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 768 #endif /* CONFIG_NOBQFMAN */ 769 770 #ifdef CONFIG_SYS_DPAA_FMAN 771 #define CONFIG_FMAN_ENET 772 #define CONFIG_PHYLIB_10G 773 #define CONFIG_PHY_VITESSE 774 #define CONFIG_PHY_REALTEK 775 #define CONFIG_PHY_TERANETICS 776 #define RGMII_PHY1_ADDR 0x1 777 #define RGMII_PHY2_ADDR 0x2 778 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 779 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 780 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 781 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 782 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 783 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 784 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 785 #endif 786 787 #ifdef CONFIG_FMAN_ENET 788 #define CONFIG_MII /* MII PHY management */ 789 #define CONFIG_ETHPRIME "FM1@DTSEC4" 790 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 791 #endif 792 793 /* 794 * Dynamic MTD Partition support with mtdparts 795 */ 796 #ifndef CONFIG_SYS_NO_FLASH 797 #define CONFIG_MTD_DEVICE 798 #define CONFIG_MTD_PARTITIONS 799 #define CONFIG_CMD_MTDPARTS 800 #define CONFIG_FLASH_CFI_MTD 801 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 802 "spi0=spife110000.0" 803 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 804 "128k(dtb),96m(fs),-(user);"\ 805 "fff800000.flash:2m(uboot),9m(kernel),"\ 806 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 807 "2m(uboot),9m(kernel),128k(dtb),-(user)" 808 #endif 809 810 /* 811 * Environment 812 */ 813 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 814 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 815 816 /* 817 * Command line configuration. 818 */ 819 #define CONFIG_CMD_DATE 820 #define CONFIG_CMD_EEPROM 821 #define CONFIG_CMD_ERRATA 822 #define CONFIG_CMD_IRQ 823 #define CONFIG_CMD_REGINFO 824 825 #ifdef CONFIG_PCI 826 #define CONFIG_CMD_PCI 827 #endif 828 829 /* 830 * Miscellaneous configurable options 831 */ 832 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 833 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 834 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 835 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 836 #ifdef CONFIG_CMD_KGDB 837 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 838 #else 839 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 840 #endif 841 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 842 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 843 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 844 845 /* 846 * For booting Linux, the board info and command line data 847 * have to be in the first 64 MB of memory, since this is 848 * the maximum mapped by the Linux kernel during initialization. 849 */ 850 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 851 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 852 853 #ifdef CONFIG_CMD_KGDB 854 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 855 #endif 856 857 /* 858 * Environment Configuration 859 */ 860 #define CONFIG_ROOTPATH "/opt/nfsroot" 861 #define CONFIG_BOOTFILE "uImage" 862 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 863 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 864 #define CONFIG_BAUDRATE 115200 865 #define __USB_PHY_TYPE utmi 866 867 #define CONFIG_EXTRA_ENV_SETTINGS \ 868 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ 869 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 870 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 871 "ramdiskfile=t1024qds/ramdisk.uboot\0" \ 872 "fdtfile=t1024qds/t1024qds.dtb\0" \ 873 "netdev=eth0\0" \ 874 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 875 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 876 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 877 "tftpflash=tftpboot $loadaddr $uboot && " \ 878 "protect off $ubootaddr +$filesize && " \ 879 "erase $ubootaddr +$filesize && " \ 880 "cp.b $loadaddr $ubootaddr $filesize && " \ 881 "protect on $ubootaddr +$filesize && " \ 882 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 883 "consoledev=ttyS0\0" \ 884 "ramdiskaddr=2000000\0" \ 885 "fdtaddr=d00000\0" \ 886 "bdev=sda3\0" 887 888 #define CONFIG_LINUX \ 889 "setenv bootargs root=/dev/ram rw " \ 890 "console=$consoledev,$baudrate $othbootargs;" \ 891 "setenv ramdiskaddr 0x02000000;" \ 892 "setenv fdtaddr 0x00c00000;" \ 893 "setenv loadaddr 0x1000000;" \ 894 "bootm $loadaddr $ramdiskaddr $fdtaddr" 895 896 #define CONFIG_NFSBOOTCOMMAND \ 897 "setenv bootargs root=/dev/nfs rw " \ 898 "nfsroot=$serverip:$rootpath " \ 899 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 900 "console=$consoledev,$baudrate $othbootargs;" \ 901 "tftp $loadaddr $bootfile;" \ 902 "tftp $fdtaddr $fdtfile;" \ 903 "bootm $loadaddr - $fdtaddr" 904 905 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 906 907 /* Hash command with SHA acceleration supported in hardware */ 908 #ifdef CONFIG_FSL_CAAM 909 #define CONFIG_CMD_HASH 910 #define CONFIG_SHA_HW_ACCEL 911 #endif 912 913 #include <asm/fsl_secure_boot.h> 914 915 #endif /* __T1024QDS_H */ 916