1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #include <asm/config_mpc85xx.h> 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 21 #ifndef CONFIG_SECURE_BOOT 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #else 24 #define CONFIG_SYS_FSL_PBL_PBI \ 25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 26 #endif 27 28 #ifdef CONFIG_T1040RDB 29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 30 #endif 31 #ifdef CONFIG_T1042RDB_PI 32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 33 #endif 34 #ifdef CONFIG_T1042RDB 35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 36 #endif 37 #ifdef CONFIG_T1040D4RDB 38 #define CONFIG_SYS_FSL_PBL_RCW \ 39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 40 #endif 41 #ifdef CONFIG_T1042D4RDB 42 #define CONFIG_SYS_FSL_PBL_RCW \ 43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 44 #endif 45 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_FSL_LAW /* Use common FSL init code */ 49 #define CONFIG_SYS_TEXT_BASE 0x30001000 50 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 51 #define CONFIG_SPL_PAD_TO 0x40000 52 #define CONFIG_SPL_MAX_SIZE 0x28000 53 #ifdef CONFIG_SPL_BUILD 54 #define CONFIG_SPL_SKIP_RELOCATE 55 #define CONFIG_SPL_COMMON_INIT_DDR 56 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 57 #define CONFIG_SYS_NO_FLASH 58 #endif 59 #define RESET_VECTOR_OFFSET 0x27FFC 60 #define BOOT_PAGE_OFFSET 0x27000 61 62 #ifdef CONFIG_NAND 63 #ifdef CONFIG_SECURE_BOOT 64 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 65 /* 66 * HDR would be appended at end of image and copied to DDR along 67 * with U-Boot image. 68 */ 69 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 70 CONFIG_U_BOOT_HDR_SIZE) 71 #else 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 73 #endif 74 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 75 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 78 #define CONFIG_SPL_NAND_BOOT 79 #endif 80 81 #ifdef CONFIG_SPIFLASH 82 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 83 #define CONFIG_SPL_SPI_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_SUPPORT 85 #define CONFIG_SPL_SPI_FLASH_MINIMAL 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #define CONFIG_SPL_SPI_BOOT 95 #endif 96 97 #ifdef CONFIG_SDCARD 98 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 99 #define CONFIG_SPL_MMC_MINIMAL 100 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 101 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 102 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 103 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 105 #ifndef CONFIG_SPL_BUILD 106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 107 #endif 108 #define CONFIG_SPL_MMC_BOOT 109 #endif 110 111 #endif 112 113 /* High Level Configuration Options */ 114 #define CONFIG_BOOKE 115 #define CONFIG_E500MC /* BOOKE e500mc family */ 116 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 117 #define CONFIG_MP /* support multiple processors */ 118 119 /* support deep sleep */ 120 #define CONFIG_DEEP_SLEEP 121 #if defined(CONFIG_DEEP_SLEEP) 122 #define CONFIG_BOARD_EARLY_INIT_F 123 #define CONFIG_SILENT_CONSOLE 124 #endif 125 126 #ifndef CONFIG_SYS_TEXT_BASE 127 #define CONFIG_SYS_TEXT_BASE 0xeff40000 128 #endif 129 130 #ifndef CONFIG_RESET_VECTOR_ADDRESS 131 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 132 #endif 133 134 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 135 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 136 #define CONFIG_FSL_IFC /* Enable IFC Support */ 137 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 138 #define CONFIG_PCI /* Enable PCI/PCIE */ 139 #define CONFIG_PCI_INDIRECT_BRIDGE 140 #define CONFIG_PCIE1 /* PCIE controller 1 */ 141 #define CONFIG_PCIE2 /* PCIE controller 2 */ 142 #define CONFIG_PCIE3 /* PCIE controller 3 */ 143 #define CONFIG_PCIE4 /* PCIE controller 4 */ 144 145 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 146 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 147 148 #define CONFIG_FSL_LAW /* Use common FSL init code */ 149 150 #define CONFIG_ENV_OVERWRITE 151 152 #ifndef CONFIG_SYS_NO_FLASH 153 #define CONFIG_FLASH_CFI_DRIVER 154 #define CONFIG_SYS_FLASH_CFI 155 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 156 #endif 157 158 #if defined(CONFIG_SPIFLASH) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_SPI_FLASH 161 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 162 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 163 #define CONFIG_ENV_SECT_SIZE 0x10000 164 #elif defined(CONFIG_SDCARD) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_MMC 167 #define CONFIG_SYS_MMC_ENV_DEV 0 168 #define CONFIG_ENV_SIZE 0x2000 169 #define CONFIG_ENV_OFFSET (512 * 0x800) 170 #elif defined(CONFIG_NAND) 171 #ifdef CONFIG_SECURE_BOOT 172 #define CONFIG_RAMBOOT_NAND 173 #define CONFIG_BOOTSCRIPT_COPY_RAM 174 #endif 175 #define CONFIG_SYS_EXTRA_ENV_RELOC 176 #define CONFIG_ENV_IS_IN_NAND 177 #define CONFIG_ENV_SIZE 0x2000 178 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 179 #else 180 #define CONFIG_ENV_IS_IN_FLASH 181 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 182 #define CONFIG_ENV_SIZE 0x2000 183 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 184 #endif 185 186 #define CONFIG_SYS_CLK_FREQ 100000000 187 #define CONFIG_DDR_CLK_FREQ 66666666 188 189 /* 190 * These can be toggled for performance analysis, otherwise use default. 191 */ 192 #define CONFIG_SYS_CACHE_STASHING 193 #define CONFIG_BACKSIDE_L2_CACHE 194 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 195 #define CONFIG_BTB /* toggle branch predition */ 196 #define CONFIG_DDR_ECC 197 #ifdef CONFIG_DDR_ECC 198 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 199 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 200 #endif 201 202 #define CONFIG_ENABLE_36BIT_PHYS 203 204 #define CONFIG_ADDR_MAP 205 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 206 207 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 208 #define CONFIG_SYS_MEMTEST_END 0x00400000 209 #define CONFIG_SYS_ALT_MEMTEST 210 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 211 212 /* 213 * Config the L3 Cache as L3 SRAM 214 */ 215 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 216 /* 217 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 218 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 219 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 220 */ 221 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 222 #define CONFIG_SYS_L3_SIZE 256 << 10 223 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 224 #ifdef CONFIG_RAMBOOT_PBL 225 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 226 #endif 227 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 228 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 229 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 230 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 231 232 #define CONFIG_SYS_DCSRBAR 0xf0000000 233 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 234 235 /* 236 * DDR Setup 237 */ 238 #define CONFIG_VERY_BIG_RAM 239 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 240 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 241 242 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 243 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 244 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 245 246 #define CONFIG_DDR_SPD 247 #ifndef CONFIG_SYS_FSL_DDR4 248 #define CONFIG_SYS_FSL_DDR3 249 #endif 250 251 #define CONFIG_SYS_SPD_BUS_NUM 0 252 #define SPD_EEPROM_ADDRESS 0x51 253 254 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 255 256 /* 257 * IFC Definitions 258 */ 259 #define CONFIG_SYS_FLASH_BASE 0xe8000000 260 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 261 262 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 263 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 264 CSPR_PORT_SIZE_16 | \ 265 CSPR_MSEL_NOR | \ 266 CSPR_V) 267 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 268 269 /* 270 * TDM Definition 271 */ 272 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 273 274 /* NOR Flash Timing Params */ 275 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 276 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 277 FTIM0_NOR_TEADC(0x5) | \ 278 FTIM0_NOR_TEAHC(0x5)) 279 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 280 FTIM1_NOR_TRAD_NOR(0x1A) |\ 281 FTIM1_NOR_TSEQRAD_NOR(0x13)) 282 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 283 FTIM2_NOR_TCH(0x4) | \ 284 FTIM2_NOR_TWPH(0x0E) | \ 285 FTIM2_NOR_TWP(0x1c)) 286 #define CONFIG_SYS_NOR_FTIM3 0x0 287 288 #define CONFIG_SYS_FLASH_QUIET_TEST 289 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 290 291 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 292 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 293 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 294 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 295 296 #define CONFIG_SYS_FLASH_EMPTY_INFO 297 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 298 299 /* CPLD on IFC */ 300 #define CPLD_LBMAP_MASK 0x3F 301 #define CPLD_BANK_SEL_MASK 0x07 302 #define CPLD_BANK_OVERRIDE 0x40 303 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 304 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 305 #define CPLD_LBMAP_RESET 0xFF 306 #define CPLD_LBMAP_SHIFT 0x03 307 308 #if defined(CONFIG_T1042RDB_PI) 309 #define CPLD_DIU_SEL_DFP 0x80 310 #elif defined(CONFIG_T1042D4RDB) 311 #define CPLD_DIU_SEL_DFP 0xc0 312 #endif 313 314 #if defined(CONFIG_T1040D4RDB) 315 #define CPLD_INT_MASK_ALL 0xFF 316 #define CPLD_INT_MASK_THERM 0x80 317 #define CPLD_INT_MASK_DVI_DFP 0x40 318 #define CPLD_INT_MASK_QSGMII1 0x20 319 #define CPLD_INT_MASK_QSGMII2 0x10 320 #define CPLD_INT_MASK_SGMI1 0x08 321 #define CPLD_INT_MASK_SGMI2 0x04 322 #define CPLD_INT_MASK_TDMR1 0x02 323 #define CPLD_INT_MASK_TDMR2 0x01 324 #endif 325 326 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 327 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 328 #define CONFIG_SYS_CSPR2_EXT (0xf) 329 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 330 | CSPR_PORT_SIZE_8 \ 331 | CSPR_MSEL_GPCM \ 332 | CSPR_V) 333 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 334 #define CONFIG_SYS_CSOR2 0x0 335 /* CPLD Timing parameters for IFC CS2 */ 336 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 337 FTIM0_GPCM_TEADC(0x0e) | \ 338 FTIM0_GPCM_TEAHC(0x0e)) 339 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 340 FTIM1_GPCM_TRAD(0x1f)) 341 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 342 FTIM2_GPCM_TCH(0x8) | \ 343 FTIM2_GPCM_TWP(0x1f)) 344 #define CONFIG_SYS_CS2_FTIM3 0x0 345 346 /* NAND Flash on IFC */ 347 #define CONFIG_NAND_FSL_IFC 348 #define CONFIG_SYS_NAND_BASE 0xff800000 349 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 350 351 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 352 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 353 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 354 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 355 | CSPR_V) 356 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 357 358 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 359 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 360 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 361 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 362 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 363 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 364 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 365 366 #define CONFIG_SYS_NAND_ONFI_DETECTION 367 368 /* ONFI NAND Flash mode0 Timing Params */ 369 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 370 FTIM0_NAND_TWP(0x18) | \ 371 FTIM0_NAND_TWCHT(0x07) | \ 372 FTIM0_NAND_TWH(0x0a)) 373 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 374 FTIM1_NAND_TWBE(0x39) | \ 375 FTIM1_NAND_TRR(0x0e) | \ 376 FTIM1_NAND_TRP(0x18)) 377 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 378 FTIM2_NAND_TREH(0x0a) | \ 379 FTIM2_NAND_TWHRE(0x1e)) 380 #define CONFIG_SYS_NAND_FTIM3 0x0 381 382 #define CONFIG_SYS_NAND_DDR_LAW 11 383 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 384 #define CONFIG_SYS_MAX_NAND_DEVICE 1 385 #define CONFIG_CMD_NAND 386 387 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 388 389 #if defined(CONFIG_NAND) 390 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 391 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 392 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 393 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 394 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 395 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 396 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 397 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 398 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 399 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 400 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 401 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 402 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 403 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 404 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 405 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 406 #else 407 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 408 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 409 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 410 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 411 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 412 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 413 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 414 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 415 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 416 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 417 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 418 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 419 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 420 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 421 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 422 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 423 #endif 424 425 #ifdef CONFIG_SPL_BUILD 426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 427 #else 428 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 429 #endif 430 431 #if defined(CONFIG_RAMBOOT_PBL) 432 #define CONFIG_SYS_RAMBOOT 433 #endif 434 435 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 436 #if defined(CONFIG_NAND) 437 #define CONFIG_A008044_WORKAROUND 438 #endif 439 #endif 440 441 #define CONFIG_BOARD_EARLY_INIT_R 442 #define CONFIG_MISC_INIT_R 443 444 #define CONFIG_HWCONFIG 445 446 /* define to use L1 as initial stack */ 447 #define CONFIG_L1_INIT_RAM 448 #define CONFIG_SYS_INIT_RAM_LOCK 449 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 452 /* The assembler doesn't like typecast */ 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 454 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 455 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 456 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 457 458 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 459 GENERATED_GBL_DATA_SIZE) 460 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 461 462 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 463 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 464 465 /* Serial Port - controlled on board with jumper J8 466 * open - index 2 467 * shorted - index 1 468 */ 469 #define CONFIG_CONS_INDEX 1 470 #define CONFIG_SYS_NS16550_SERIAL 471 #define CONFIG_SYS_NS16550_REG_SIZE 1 472 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 473 474 #define CONFIG_SYS_BAUDRATE_TABLE \ 475 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 476 477 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 478 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 479 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 480 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 481 #ifndef CONFIG_SPL_BUILD 482 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 483 #endif 484 485 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 486 /* Video */ 487 #define CONFIG_FSL_DIU_FB 488 489 #ifdef CONFIG_FSL_DIU_FB 490 #define CONFIG_FSL_DIU_CH7301 491 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 492 #define CONFIG_VIDEO 493 #define CONFIG_CMD_BMP 494 #define CONFIG_CFB_CONSOLE 495 #define CONFIG_CFB_CONSOLE_ANSI 496 #define CONFIG_VIDEO_SW_CURSOR 497 #define CONFIG_VGA_AS_SINGLE_DEVICE 498 #define CONFIG_VIDEO_LOGO 499 #define CONFIG_VIDEO_BMP_LOGO 500 #endif 501 #endif 502 503 /* I2C */ 504 #define CONFIG_SYS_I2C 505 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 506 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 507 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 508 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 509 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 510 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 511 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 512 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 513 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 514 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 515 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 516 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 517 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 518 519 /* I2C bus multiplexer */ 520 #define I2C_MUX_PCA_ADDR 0x70 521 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 522 #define I2C_MUX_CH_DEFAULT 0x8 523 #endif 524 525 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 526 /* LDI/DVI Encoder for display */ 527 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 528 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 529 530 /* 531 * RTC configuration 532 */ 533 #define RTC 534 #define CONFIG_RTC_DS1337 1 535 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 536 537 /*DVI encoder*/ 538 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 539 #endif 540 541 /* 542 * eSPI - Enhanced SPI 543 */ 544 #define CONFIG_SPI_FLASH_BAR 545 #define CONFIG_SF_DEFAULT_SPEED 10000000 546 #define CONFIG_SF_DEFAULT_MODE 0 547 #define CONFIG_ENV_SPI_BUS 0 548 #define CONFIG_ENV_SPI_CS 0 549 #define CONFIG_ENV_SPI_MAX_HZ 10000000 550 #define CONFIG_ENV_SPI_MODE 0 551 552 /* 553 * General PCI 554 * Memory space is mapped 1-1, but I/O space must start from 0. 555 */ 556 557 #ifdef CONFIG_PCI 558 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 559 #ifdef CONFIG_PCIE1 560 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 561 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 562 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 563 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 564 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 565 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 566 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 567 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 568 #endif 569 570 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 571 #ifdef CONFIG_PCIE2 572 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 573 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 574 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 575 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 576 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 577 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 578 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 579 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 580 #endif 581 582 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 583 #ifdef CONFIG_PCIE3 584 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 585 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 586 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 587 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 588 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 589 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 590 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 591 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 592 #endif 593 594 /* controller 4, Base address 203000 */ 595 #ifdef CONFIG_PCIE4 596 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 597 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 598 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 599 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 600 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 601 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 602 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 603 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 604 #endif 605 606 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 607 608 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 609 #define CONFIG_DOS_PARTITION 610 #endif /* CONFIG_PCI */ 611 612 /* SATA */ 613 #define CONFIG_FSL_SATA_V2 614 #ifdef CONFIG_FSL_SATA_V2 615 #define CONFIG_LIBATA 616 #define CONFIG_FSL_SATA 617 618 #define CONFIG_SYS_SATA_MAX_DEVICE 1 619 #define CONFIG_SATA1 620 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 621 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 622 623 #define CONFIG_LBA48 624 #define CONFIG_CMD_SATA 625 #define CONFIG_DOS_PARTITION 626 #endif 627 628 /* 629 * USB 630 */ 631 #define CONFIG_HAS_FSL_DR_USB 632 633 #ifdef CONFIG_HAS_FSL_DR_USB 634 #define CONFIG_USB_EHCI 635 636 #ifdef CONFIG_USB_EHCI 637 #define CONFIG_USB_EHCI_FSL 638 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 639 #endif 640 #endif 641 642 #define CONFIG_MMC 643 644 #ifdef CONFIG_MMC 645 #define CONFIG_FSL_ESDHC 646 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 647 #define CONFIG_GENERIC_MMC 648 #define CONFIG_DOS_PARTITION 649 #endif 650 651 /* Qman/Bman */ 652 #ifndef CONFIG_NOBQFMAN 653 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 654 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 655 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 656 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 657 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 658 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 659 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 660 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 661 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 662 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 663 CONFIG_SYS_BMAN_CENA_SIZE) 664 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 665 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 666 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 667 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 668 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 669 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 670 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 671 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 672 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 673 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 674 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 675 CONFIG_SYS_QMAN_CENA_SIZE) 676 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 677 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 678 679 #define CONFIG_SYS_DPAA_FMAN 680 #define CONFIG_SYS_DPAA_PME 681 682 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 683 #define CONFIG_QE 684 #define CONFIG_U_QE 685 #endif 686 687 /* Default address of microcode for the Linux Fman driver */ 688 #if defined(CONFIG_SPIFLASH) 689 /* 690 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 691 * env, so we got 0x110000. 692 */ 693 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 694 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 695 #elif defined(CONFIG_SDCARD) 696 /* 697 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 698 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 699 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 700 */ 701 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 702 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 703 #elif defined(CONFIG_NAND) 704 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 705 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 706 #else 707 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 708 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 709 #endif 710 711 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 712 #if defined(CONFIG_SPIFLASH) 713 #define CONFIG_SYS_QE_FW_ADDR 0x130000 714 #elif defined(CONFIG_SDCARD) 715 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 716 #elif defined(CONFIG_NAND) 717 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 718 #else 719 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 720 #endif 721 #endif 722 723 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 724 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 725 #endif /* CONFIG_NOBQFMAN */ 726 727 #ifdef CONFIG_SYS_DPAA_FMAN 728 #define CONFIG_FMAN_ENET 729 #define CONFIG_PHY_VITESSE 730 #define CONFIG_PHY_REALTEK 731 #endif 732 733 #ifdef CONFIG_FMAN_ENET 734 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 735 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 736 #elif defined(CONFIG_T1040D4RDB) 737 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 738 #elif defined(CONFIG_T1042D4RDB) 739 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 740 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 741 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 742 #endif 743 744 #ifdef CONFIG_T104XD4RDB 745 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 746 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 747 #else 748 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 749 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 750 #endif 751 752 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 753 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 754 #define CONFIG_VSC9953 755 #define CONFIG_CMD_ETHSW 756 #ifdef CONFIG_T1040RDB 757 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 758 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 759 #else 760 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 761 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 762 #endif 763 #endif 764 765 #define CONFIG_MII /* MII PHY management */ 766 #define CONFIG_ETHPRIME "FM1@DTSEC4" 767 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 768 #endif 769 770 /* 771 * Environment 772 */ 773 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 774 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 775 776 /* 777 * Command line configuration. 778 */ 779 #ifdef CONFIG_T1042RDB_PI 780 #define CONFIG_CMD_DATE 781 #endif 782 #define CONFIG_CMD_ERRATA 783 #define CONFIG_CMD_IRQ 784 #define CONFIG_CMD_REGINFO 785 786 #ifdef CONFIG_PCI 787 #define CONFIG_CMD_PCI 788 #endif 789 790 /* Hash command with SHA acceleration supported in hardware */ 791 #ifdef CONFIG_FSL_CAAM 792 #define CONFIG_CMD_HASH 793 #define CONFIG_SHA_HW_ACCEL 794 #endif 795 796 /* 797 * Miscellaneous configurable options 798 */ 799 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 800 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 801 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 802 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 803 #ifdef CONFIG_CMD_KGDB 804 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 805 #else 806 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 807 #endif 808 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 809 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 810 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 811 812 /* 813 * For booting Linux, the board info and command line data 814 * have to be in the first 64 MB of memory, since this is 815 * the maximum mapped by the Linux kernel during initialization. 816 */ 817 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 818 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 819 820 #ifdef CONFIG_CMD_KGDB 821 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 822 #endif 823 824 /* 825 * Dynamic MTD Partition support with mtdparts 826 */ 827 #ifndef CONFIG_SYS_NO_FLASH 828 #define CONFIG_MTD_DEVICE 829 #define CONFIG_MTD_PARTITIONS 830 #define CONFIG_CMD_MTDPARTS 831 #define CONFIG_FLASH_CFI_MTD 832 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 833 "spi0=spife110000.0" 834 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 835 "128k(dtb),96m(fs),-(user);"\ 836 "fff800000.flash:2m(uboot),9m(kernel),"\ 837 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 838 "2m(uboot),9m(kernel),128k(dtb),-(user)" 839 #endif 840 841 /* 842 * Environment Configuration 843 */ 844 #define CONFIG_ROOTPATH "/opt/nfsroot" 845 #define CONFIG_BOOTFILE "uImage" 846 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 847 848 /* default location for tftp and bootm */ 849 #define CONFIG_LOADADDR 1000000 850 851 852 #define CONFIG_BAUDRATE 115200 853 854 #define __USB_PHY_TYPE utmi 855 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 856 857 #ifdef CONFIG_T1040RDB 858 #define FDTFILE "t1040rdb/t1040rdb.dtb" 859 #elif defined(CONFIG_T1042RDB_PI) 860 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 861 #elif defined(CONFIG_T1042RDB) 862 #define FDTFILE "t1042rdb/t1042rdb.dtb" 863 #elif defined(CONFIG_T1040D4RDB) 864 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 865 #elif defined(CONFIG_T1042D4RDB) 866 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 867 #endif 868 869 #ifdef CONFIG_FSL_DIU_FB 870 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 871 #else 872 #define DIU_ENVIRONMENT 873 #endif 874 875 #define CONFIG_EXTRA_ENV_SETTINGS \ 876 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 877 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 878 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 879 "netdev=eth0\0" \ 880 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 881 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 882 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 883 "tftpflash=tftpboot $loadaddr $uboot && " \ 884 "protect off $ubootaddr +$filesize && " \ 885 "erase $ubootaddr +$filesize && " \ 886 "cp.b $loadaddr $ubootaddr $filesize && " \ 887 "protect on $ubootaddr +$filesize && " \ 888 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 889 "consoledev=ttyS0\0" \ 890 "ramdiskaddr=2000000\0" \ 891 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 892 "fdtaddr=1e00000\0" \ 893 "fdtfile=" __stringify(FDTFILE) "\0" \ 894 "bdev=sda3\0" 895 896 #define CONFIG_LINUX \ 897 "setenv bootargs root=/dev/ram rw " \ 898 "console=$consoledev,$baudrate $othbootargs;" \ 899 "setenv ramdiskaddr 0x02000000;" \ 900 "setenv fdtaddr 0x00c00000;" \ 901 "setenv loadaddr 0x1000000;" \ 902 "bootm $loadaddr $ramdiskaddr $fdtaddr" 903 904 #define CONFIG_HDBOOT \ 905 "setenv bootargs root=/dev/$bdev rw " \ 906 "console=$consoledev,$baudrate $othbootargs;" \ 907 "tftp $loadaddr $bootfile;" \ 908 "tftp $fdtaddr $fdtfile;" \ 909 "bootm $loadaddr - $fdtaddr" 910 911 #define CONFIG_NFSBOOTCOMMAND \ 912 "setenv bootargs root=/dev/nfs rw " \ 913 "nfsroot=$serverip:$rootpath " \ 914 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 915 "console=$consoledev,$baudrate $othbootargs;" \ 916 "tftp $loadaddr $bootfile;" \ 917 "tftp $fdtaddr $fdtfile;" \ 918 "bootm $loadaddr - $fdtaddr" 919 920 #define CONFIG_RAMBOOTCOMMAND \ 921 "setenv bootargs root=/dev/ram rw " \ 922 "console=$consoledev,$baudrate $othbootargs;" \ 923 "tftp $ramdiskaddr $ramdiskfile;" \ 924 "tftp $loadaddr $bootfile;" \ 925 "tftp $fdtaddr $fdtfile;" \ 926 "bootm $loadaddr $ramdiskaddr $fdtaddr" 927 928 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 929 930 #include <asm/fsl_secure_boot.h> 931 932 #endif /* __CONFIG_H */ 933