1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_C29XPCIE 17 #define CONFIG_PPC_C29X 18 #endif 19 20 #ifdef CONFIG_SPIFLASH 21 #define CONFIG_RAMBOOT_SPIFLASH 22 #define CONFIG_SYS_TEXT_BASE 0x11000000 23 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 24 #endif 25 26 #ifdef CONFIG_NAND 27 #ifdef CONFIG_TPL_BUILD 28 #define CONFIG_SPL_NAND_BOOT 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_NAND_INIT 31 #define CONFIG_TPL_SERIAL_SUPPORT 32 #define CONFIG_TPL_LIBGENERIC_SUPPORT 33 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 34 #define CONFIG_TPL_NAND_SUPPORT 35 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #define CONFIG_SPL_MAX_SIZE (128 << 10) 38 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 41 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 42 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 43 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 44 #elif defined(CONFIG_SPL_BUILD) 45 #define CONFIG_SPL_INIT_MINIMAL 46 #define CONFIG_SPL_SERIAL_SUPPORT 47 #define CONFIG_SPL_NAND_SUPPORT 48 #define CONFIG_SPL_NAND_MINIMAL 49 #define CONFIG_SPL_FLUSH_IMAGE 50 #define CONFIG_SPL_TEXT_BASE 0xff800000 51 #define CONFIG_SPL_MAX_SIZE 8192 52 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 53 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 54 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 55 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 56 #endif 57 #define CONFIG_SPL_PAD_TO 0x20000 58 #define CONFIG_TPL_PAD_TO 0x20000 59 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 60 #define CONFIG_SYS_TEXT_BASE 0x11001000 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 62 #endif 63 64 #ifndef CONFIG_SYS_TEXT_BASE 65 #define CONFIG_SYS_TEXT_BASE 0xeff40000 66 #endif 67 68 #ifndef CONFIG_RESET_VECTOR_ADDRESS 69 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 70 #endif 71 72 #ifdef CONFIG_SPL_BUILD 73 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 74 #else 75 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 76 #endif 77 78 #ifdef CONFIG_SPL_BUILD 79 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 80 #endif 81 82 /* High Level Configuration Options */ 83 #define CONFIG_BOOKE /* BOOKE */ 84 #define CONFIG_E500 /* BOOKE e500 family */ 85 #define CONFIG_FSL_IFC /* Enable IFC Support */ 86 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 87 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 88 89 #define CONFIG_PCI /* Enable PCI/PCIE */ 90 #ifdef CONFIG_PCI 91 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 92 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 93 #define CONFIG_PCI_INDIRECT_BRIDGE 94 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 95 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 96 97 #define CONFIG_CMD_PCI 98 99 /* 100 * PCI Windows 101 * Memory space is mapped 1-1, but I/O space must start from 0. 102 */ 103 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 104 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 105 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 106 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 107 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 108 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 109 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 110 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 111 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 112 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 113 114 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 115 116 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 117 #define CONFIG_DOS_PARTITION 118 #endif 119 120 #define CONFIG_FSL_LAW /* Use common FSL init code */ 121 #define CONFIG_TSEC_ENET 122 #define CONFIG_ENV_OVERWRITE 123 124 #define CONFIG_DDR_CLK_FREQ 100000000 125 #define CONFIG_SYS_CLK_FREQ 66666666 126 127 #define CONFIG_HWCONFIG 128 129 /* 130 * These can be toggled for performance analysis, otherwise use default. 131 */ 132 #define CONFIG_L2_CACHE /* toggle L2 cache */ 133 #define CONFIG_BTB /* toggle branch predition */ 134 135 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 136 137 #define CONFIG_ENABLE_36BIT_PHYS 138 139 #define CONFIG_ADDR_MAP 1 140 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 141 142 #define CONFIG_SYS_MEMTEST_START 0x00200000 143 #define CONFIG_SYS_MEMTEST_END 0x00400000 144 #define CONFIG_PANIC_HANG 145 146 /* DDR Setup */ 147 #define CONFIG_SYS_FSL_DDR3 148 #define CONFIG_DDR_SPD 149 #define CONFIG_SYS_SPD_BUS_NUM 0 150 #define SPD_EEPROM_ADDRESS 0x50 151 #define CONFIG_SYS_DDR_RAW_TIMING 152 153 /* DDR ECC Setup*/ 154 #define CONFIG_DDR_ECC 155 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 156 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 157 158 #define CONFIG_SYS_SDRAM_SIZE 512 159 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 161 162 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 163 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 164 165 #define CONFIG_SYS_CCSRBAR 0xffe00000 166 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 167 168 /* Platform SRAM setting */ 169 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 170 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 171 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 172 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 173 174 #ifdef CONFIG_SPL_BUILD 175 #define CONFIG_SYS_NO_FLASH 176 #endif 177 178 /* 179 * IFC Definitions 180 */ 181 /* NOR Flash on IFC */ 182 #define CONFIG_SYS_FLASH_BASE 0xec000000 183 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 184 185 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 186 187 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 188 #define CONFIG_SYS_MAX_FLASH_BANKS 1 189 190 #define CONFIG_SYS_FLASH_QUIET_TEST 191 #define CONFIG_FLASH_SHOW_PROGRESS 45 192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 194 195 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 196 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 197 CSPR_PORT_SIZE_16 | \ 198 CSPR_MSEL_NOR | \ 199 CSPR_V) 200 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 201 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 202 203 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 204 FTIM0_NOR_TEADC(0x5) | \ 205 FTIM0_NOR_TEAHC(0x5)) 206 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 207 FTIM1_NOR_TRAD_NOR(0x1A) |\ 208 FTIM1_NOR_TSEQRAD_NOR(0x13)) 209 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 210 FTIM2_NOR_TCH(0x4) | \ 211 FTIM2_NOR_TWPH(0x0E) | \ 212 FTIM2_NOR_TWP(0x1c)) 213 #define CONFIG_SYS_NOR_FTIM3 0x0 214 215 /* CFI for NOR Flash */ 216 #define CONFIG_FLASH_CFI_DRIVER 217 #define CONFIG_SYS_FLASH_CFI 218 #define CONFIG_SYS_FLASH_EMPTY_INFO 219 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 220 221 /* NAND Flash on IFC */ 222 #define CONFIG_NAND_FSL_IFC 223 #define CONFIG_SYS_NAND_BASE 0xff800000 224 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 225 226 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 227 228 #define CONFIG_SYS_MAX_NAND_DEVICE 1 229 #define CONFIG_CMD_NAND 230 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 231 232 /* 8Bit NAND Flash - K9F1G08U0B */ 233 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 234 | CSPR_PORT_SIZE_8 \ 235 | CSPR_MSEL_NAND \ 236 | CSPR_V) 237 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 238 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 239 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 240 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 241 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 242 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 243 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 244 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 245 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 246 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 247 FTIM0_NAND_TWP(0x0c) | \ 248 FTIM0_NAND_TWCHT(0x08) | \ 249 FTIM0_NAND_TWH(0x06)) 250 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 251 FTIM1_NAND_TWBE(0x1d) | \ 252 FTIM1_NAND_TRR(0x08) | \ 253 FTIM1_NAND_TRP(0x0c)) 254 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 255 FTIM2_NAND_TREH(0x0a) | \ 256 FTIM2_NAND_TWHRE(0x18)) 257 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 258 259 #define CONFIG_SYS_NAND_DDR_LAW 11 260 261 /* Set up IFC registers for boot location NOR/NAND */ 262 #ifdef CONFIG_NAND 263 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 264 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 265 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 266 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 267 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 268 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 269 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 270 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 271 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 272 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 273 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 274 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 275 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 276 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 277 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 278 #else 279 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 280 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 281 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 282 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 283 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 284 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 285 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 286 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 287 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 288 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 289 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 290 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 291 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 292 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 293 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 294 #endif 295 296 /* CPLD on IFC, selected by CS2 */ 297 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 298 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 299 | CONFIG_SYS_CPLD_BASE) 300 301 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 302 | CSPR_PORT_SIZE_8 \ 303 | CSPR_MSEL_GPCM \ 304 | CSPR_V) 305 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 306 #define CONFIG_SYS_CSOR2 0x0 307 /* CPLD Timing parameters for IFC CS2 */ 308 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 309 FTIM0_GPCM_TEADC(0x0e) | \ 310 FTIM0_GPCM_TEAHC(0x0e)) 311 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 312 FTIM1_GPCM_TRAD(0x1f)) 313 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 314 FTIM2_GPCM_TCH(0x8) | \ 315 FTIM2_GPCM_TWP(0x1f)) 316 #define CONFIG_SYS_CS2_FTIM3 0x0 317 318 #if defined(CONFIG_RAMBOOT_SPIFLASH) 319 #define CONFIG_SYS_RAMBOOT 320 #define CONFIG_SYS_EXTRA_ENV_RELOC 321 #endif 322 323 #define CONFIG_BOARD_EARLY_INIT_R 324 325 #define CONFIG_SYS_INIT_RAM_LOCK 326 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 327 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 328 329 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 330 - GENERATED_GBL_DATA_SIZE) 331 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 332 333 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 334 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 335 336 /* 337 * Config the L2 Cache as L2 SRAM 338 */ 339 #if defined(CONFIG_SPL_BUILD) 340 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 341 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 342 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 343 #define CONFIG_SYS_L2_SIZE (256 << 10) 344 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 345 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 346 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 347 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 348 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 349 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 350 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 351 #elif defined(CONFIG_NAND) 352 #ifdef CONFIG_TPL_BUILD 353 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 354 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 355 #define CONFIG_SYS_L2_SIZE (256 << 10) 356 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 357 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 358 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 359 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 360 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 361 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 362 #else 363 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 364 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 365 #define CONFIG_SYS_L2_SIZE (256 << 10) 366 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 367 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 368 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 369 #endif 370 #endif 371 #endif 372 373 /* Serial Port */ 374 #define CONFIG_CONS_INDEX 1 375 #define CONFIG_SYS_NS16550_SERIAL 376 #define CONFIG_SYS_NS16550_REG_SIZE 1 377 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 378 379 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 380 #define CONFIG_NS16550_MIN_FUNCTIONS 381 #endif 382 383 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 384 385 #define CONFIG_SYS_BAUDRATE_TABLE \ 386 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 387 388 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 389 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 390 391 #define CONFIG_SYS_I2C 392 #define CONFIG_SYS_I2C_FSL 393 #define CONFIG_SYS_FSL_I2C_SPEED 400000 394 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 395 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 396 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 397 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 398 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 399 400 /* I2C EEPROM */ 401 /* enable read and write access to EEPROM */ 402 #define CONFIG_CMD_EEPROM 403 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 404 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 405 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 406 407 /* eSPI - Enhanced SPI */ 408 #define CONFIG_SF_DEFAULT_SPEED 10000000 409 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 410 411 #ifdef CONFIG_TSEC_ENET 412 #define CONFIG_MII /* MII PHY management */ 413 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 414 #define CONFIG_TSEC1 1 415 #define CONFIG_TSEC1_NAME "eTSEC1" 416 #define CONFIG_TSEC2 1 417 #define CONFIG_TSEC2_NAME "eTSEC2" 418 419 /* Default mode is RGMII mode */ 420 #define TSEC1_PHY_ADDR 0 421 #define TSEC2_PHY_ADDR 2 422 423 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 424 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 425 426 #define CONFIG_ETHPRIME "eTSEC1" 427 428 #define CONFIG_PHY_GIGE 429 #endif /* CONFIG_TSEC_ENET */ 430 431 /* 432 * Environment 433 */ 434 #if defined(CONFIG_SYS_RAMBOOT) 435 #if defined(CONFIG_RAMBOOT_SPIFLASH) 436 #define CONFIG_ENV_IS_IN_SPI_FLASH 437 #define CONFIG_ENV_SPI_BUS 0 438 #define CONFIG_ENV_SPI_CS 0 439 #define CONFIG_ENV_SPI_MAX_HZ 10000000 440 #define CONFIG_ENV_SPI_MODE 0 441 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 442 #define CONFIG_ENV_SECT_SIZE 0x10000 443 #define CONFIG_ENV_SIZE 0x2000 444 #endif 445 #elif defined(CONFIG_NAND) 446 #define CONFIG_ENV_IS_IN_NAND 447 #ifdef CONFIG_TPL_BUILD 448 #define CONFIG_ENV_SIZE 0x2000 449 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 450 #else 451 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 452 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 453 #endif 454 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 455 #else 456 #define CONFIG_ENV_IS_IN_FLASH 457 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 458 #define CONFIG_ENV_SIZE 0x2000 459 #define CONFIG_ENV_SECT_SIZE 0x20000 460 #endif 461 462 #define CONFIG_LOADS_ECHO 463 #define CONFIG_SYS_LOADS_BAUD_CHANGE 464 465 /* 466 * Command line configuration. 467 */ 468 #define CONFIG_CMD_ERRATA 469 #define CONFIG_CMD_IRQ 470 #define CONFIG_CMD_REGINFO 471 472 /* Hash command with SHA acceleration supported in hardware */ 473 #ifdef CONFIG_FSL_CAAM 474 #define CONFIG_CMD_HASH 475 #define CONFIG_SHA_HW_ACCEL 476 #endif 477 478 /* 479 * Miscellaneous configurable options 480 */ 481 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 482 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 483 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 484 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 485 486 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 487 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 488 /* Print Buffer Size */ 489 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 490 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 491 492 /* 493 * For booting Linux, the board info and command line data 494 * have to be in the first 64 MB of memory, since this is 495 * the maximum mapped by the Linux kernel during initialization. 496 */ 497 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 498 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 499 500 /* 501 * Environment Configuration 502 */ 503 504 #ifdef CONFIG_TSEC_ENET 505 #define CONFIG_HAS_ETH0 506 #define CONFIG_HAS_ETH1 507 #endif 508 509 #define CONFIG_ROOTPATH "/opt/nfsroot" 510 #define CONFIG_BOOTFILE "uImage" 511 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 512 513 /* default location for tftp and bootm */ 514 #define CONFIG_LOADADDR 1000000 515 516 517 #define CONFIG_BAUDRATE 115200 518 519 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 520 521 #define CONFIG_EXTRA_ENV_SETTINGS \ 522 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 523 "netdev=eth0\0" \ 524 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 525 "loadaddr=1000000\0" \ 526 "consoledev=ttyS0\0" \ 527 "ramdiskaddr=2000000\0" \ 528 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 529 "fdtaddr=1e00000\0" \ 530 "fdtfile=name/of/device-tree.dtb\0" \ 531 "othbootargs=ramdisk_size=600000\0" \ 532 533 #define CONFIG_RAMBOOTCOMMAND \ 534 "setenv bootargs root=/dev/ram rw " \ 535 "console=$consoledev,$baudrate $othbootargs; " \ 536 "tftp $ramdiskaddr $ramdiskfile;" \ 537 "tftp $loadaddr $bootfile;" \ 538 "tftp $fdtaddr $fdtfile;" \ 539 "bootm $loadaddr $ramdiskaddr $fdtaddr" 540 541 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 542 543 #include <asm/fsl_secure_boot.h> 544 545 #endif /* __CONFIG_H */ 546