1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 23 #define CONFIG_SPL_SERIAL_SUPPORT 24 #define CONFIG_SPL_MMC_SUPPORT 25 #define CONFIG_SPL_MMC_MINIMAL 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 28 #define CONFIG_SPL_LIBGENERIC_SUPPORT 29 #define CONFIG_FSL_LAW /* Use common FSL init code */ 30 #define CONFIG_SYS_TEXT_BASE 0x11001000 31 #define CONFIG_SPL_TEXT_BASE 0xD0001000 32 #define CONFIG_SPL_PAD_TO 0x18000 33 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 34 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 35 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 36 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 37 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 40 #define CONFIG_SPL_MMC_BOOT 41 #ifdef CONFIG_SPL_BUILD 42 #define CONFIG_SPL_COMMON_INIT_DDR 43 #endif 44 #endif 45 46 #ifdef CONFIG_SPIFLASH 47 #ifdef CONFIG_SECURE_BOOT 48 #define CONFIG_RAMBOOT_SPIFLASH 49 #define CONFIG_SYS_TEXT_BASE 0x11000000 50 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 51 #else 52 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 53 #define CONFIG_SPL_SERIAL_SUPPORT 54 #define CONFIG_SPL_SPI_SUPPORT 55 #define CONFIG_SPL_SPI_FLASH_SUPPORT 56 #define CONFIG_SPL_SPI_FLASH_MINIMAL 57 #define CONFIG_SPL_FLUSH_IMAGE 58 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 59 #define CONFIG_SPL_LIBGENERIC_SUPPORT 60 #define CONFIG_FSL_LAW /* Use common FSL init code */ 61 #define CONFIG_SYS_TEXT_BASE 0x11001000 62 #define CONFIG_SPL_TEXT_BASE 0xD0001000 63 #define CONFIG_SPL_PAD_TO 0x18000 64 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 71 #define CONFIG_SPL_SPI_BOOT 72 #ifdef CONFIG_SPL_BUILD 73 #define CONFIG_SPL_COMMON_INIT_DDR 74 #endif 75 #endif 76 #endif 77 78 #ifdef CONFIG_NAND 79 #ifdef CONFIG_SECURE_BOOT 80 #define CONFIG_SPL_INIT_MINIMAL 81 #define CONFIG_SPL_SERIAL_SUPPORT 82 #define CONFIG_SPL_NAND_SUPPORT 83 #define CONFIG_SPL_NAND_BOOT 84 #define CONFIG_SPL_FLUSH_IMAGE 85 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 86 87 #define CONFIG_SYS_TEXT_BASE 0x00201000 88 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 89 #define CONFIG_SPL_MAX_SIZE 8192 90 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 91 #define CONFIG_SPL_RELOC_STACK 0x00100000 92 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 93 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 94 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 95 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 96 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 97 #else 98 #ifdef CONFIG_TPL_BUILD 99 #define CONFIG_SPL_NAND_BOOT 100 #define CONFIG_SPL_FLUSH_IMAGE 101 #define CONFIG_SPL_NAND_INIT 102 #define CONFIG_TPL_SERIAL_SUPPORT 103 #define CONFIG_TPL_LIBGENERIC_SUPPORT 104 #define CONFIG_TPL_NAND_SUPPORT 105 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 106 #define CONFIG_SPL_COMMON_INIT_DDR 107 #define CONFIG_SPL_MAX_SIZE (128 << 10) 108 #define CONFIG_SPL_TEXT_BASE 0xD0001000 109 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 110 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 111 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 112 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 113 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 114 #elif defined(CONFIG_SPL_BUILD) 115 #define CONFIG_SPL_INIT_MINIMAL 116 #define CONFIG_SPL_SERIAL_SUPPORT 117 #define CONFIG_SPL_NAND_SUPPORT 118 #define CONFIG_SPL_NAND_MINIMAL 119 #define CONFIG_SPL_FLUSH_IMAGE 120 #define CONFIG_SPL_TEXT_BASE 0xff800000 121 #define CONFIG_SPL_MAX_SIZE 8192 122 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 123 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 124 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 125 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 126 #endif 127 #define CONFIG_SPL_PAD_TO 0x20000 128 #define CONFIG_TPL_PAD_TO 0x20000 129 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 130 #define CONFIG_SYS_TEXT_BASE 0x11001000 131 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 132 #endif 133 #endif 134 135 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 136 #define CONFIG_RAMBOOT_NAND 137 #define CONFIG_SYS_TEXT_BASE 0x11000000 138 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 139 #endif 140 141 #ifndef CONFIG_SYS_TEXT_BASE 142 #define CONFIG_SYS_TEXT_BASE 0xeff40000 143 #endif 144 145 #ifndef CONFIG_RESET_VECTOR_ADDRESS 146 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 147 #endif 148 149 #ifdef CONFIG_SPL_BUILD 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 151 #else 152 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 153 #endif 154 155 /* High Level Configuration Options */ 156 #define CONFIG_BOOKE /* BOOKE */ 157 #define CONFIG_E500 /* BOOKE e500 family */ 158 #define CONFIG_FSL_IFC /* Enable IFC Support */ 159 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 160 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 161 162 #define CONFIG_PCI /* Enable PCI/PCIE */ 163 #if defined(CONFIG_PCI) 164 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 165 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 166 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 167 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 168 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 169 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 170 171 #define CONFIG_CMD_PCI 172 173 /* 174 * PCI Windows 175 * Memory space is mapped 1-1, but I/O space must start from 0. 176 */ 177 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 178 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 179 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 180 #ifdef CONFIG_PHYS_64BIT 181 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 182 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 183 #else 184 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 185 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 186 #endif 187 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 188 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 189 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 190 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 191 #ifdef CONFIG_PHYS_64BIT 192 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 193 #else 194 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 195 #endif 196 197 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 198 #if defined(CONFIG_P1010RDB_PA) 199 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 200 #elif defined(CONFIG_P1010RDB_PB) 201 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 202 #endif 203 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 204 #ifdef CONFIG_PHYS_64BIT 205 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 206 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 207 #else 208 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 209 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 210 #endif 211 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 212 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 213 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 214 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 215 #ifdef CONFIG_PHYS_64BIT 216 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 217 #else 218 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 219 #endif 220 221 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 222 223 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 224 #define CONFIG_DOS_PARTITION 225 #endif 226 227 #define CONFIG_FSL_LAW /* Use common FSL init code */ 228 #define CONFIG_TSEC_ENET 229 #define CONFIG_ENV_OVERWRITE 230 231 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 232 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 233 234 #define CONFIG_MISC_INIT_R 235 #define CONFIG_HWCONFIG 236 /* 237 * These can be toggled for performance analysis, otherwise use default. 238 */ 239 #define CONFIG_L2_CACHE /* toggle L2 cache */ 240 #define CONFIG_BTB /* toggle branch predition */ 241 242 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 243 244 #define CONFIG_ENABLE_36BIT_PHYS 245 246 #ifdef CONFIG_PHYS_64BIT 247 #define CONFIG_ADDR_MAP 1 248 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 249 #endif 250 251 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 252 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 253 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 254 255 /* DDR Setup */ 256 #define CONFIG_SYS_FSL_DDR3 257 #define CONFIG_SYS_DDR_RAW_TIMING 258 #define CONFIG_DDR_SPD 259 #define CONFIG_SYS_SPD_BUS_NUM 1 260 #define SPD_EEPROM_ADDRESS 0x52 261 262 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 263 264 #ifndef __ASSEMBLY__ 265 extern unsigned long get_sdram_size(void); 266 #endif 267 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 268 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 269 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 270 271 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 272 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 273 274 /* DDR3 Controller Settings */ 275 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 276 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 277 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 278 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 279 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 280 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 281 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 282 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 283 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 284 #define CONFIG_SYS_DDR_RCW_1 0x00000000 285 #define CONFIG_SYS_DDR_RCW_2 0x00000000 286 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 287 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 288 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 289 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 290 291 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 292 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 293 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 294 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 295 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 296 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 297 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 298 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 299 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 300 301 /* settings for DDR3 at 667MT/s */ 302 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 303 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 304 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 305 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 306 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 307 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 308 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 309 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 310 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 311 312 #define CONFIG_SYS_CCSRBAR 0xffe00000 313 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 314 315 /* Don't relocate CCSRBAR while in NAND_SPL */ 316 #ifdef CONFIG_SPL_BUILD 317 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 318 #endif 319 320 /* 321 * Memory map 322 * 323 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 324 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 325 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 326 * 327 * Localbus non-cacheable 328 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 329 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 330 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 331 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 332 */ 333 334 /* 335 * IFC Definitions 336 */ 337 /* NOR Flash on IFC */ 338 #ifdef CONFIG_SPL_BUILD 339 #define CONFIG_SYS_NO_FLASH 340 #endif 341 342 #define CONFIG_SYS_FLASH_BASE 0xee000000 343 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 344 345 #ifdef CONFIG_PHYS_64BIT 346 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 347 #else 348 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 349 #endif 350 351 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 352 CSPR_PORT_SIZE_16 | \ 353 CSPR_MSEL_NOR | \ 354 CSPR_V) 355 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 356 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 357 /* NOR Flash Timing Params */ 358 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 359 FTIM0_NOR_TEADC(0x5) | \ 360 FTIM0_NOR_TEAHC(0x5) 361 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 362 FTIM1_NOR_TRAD_NOR(0x0f) 363 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 364 FTIM2_NOR_TCH(0x4) | \ 365 FTIM2_NOR_TWP(0x1c) 366 #define CONFIG_SYS_NOR_FTIM3 0x0 367 368 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 369 #define CONFIG_SYS_FLASH_QUIET_TEST 370 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 371 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 372 373 #undef CONFIG_SYS_FLASH_CHECKSUM 374 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 375 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 376 377 /* CFI for NOR Flash */ 378 #define CONFIG_FLASH_CFI_DRIVER 379 #define CONFIG_SYS_FLASH_CFI 380 #define CONFIG_SYS_FLASH_EMPTY_INFO 381 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 382 383 /* NAND Flash on IFC */ 384 #define CONFIG_SYS_NAND_BASE 0xff800000 385 #ifdef CONFIG_PHYS_64BIT 386 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 387 #else 388 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 389 #endif 390 391 #define CONFIG_MTD_DEVICE 392 #define CONFIG_MTD_PARTITION 393 #define CONFIG_CMD_MTDPARTS 394 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 395 #define MTDPARTS_DEFAULT \ 396 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 397 398 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 399 | CSPR_PORT_SIZE_8 \ 400 | CSPR_MSEL_NAND \ 401 | CSPR_V) 402 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 403 404 #if defined(CONFIG_P1010RDB_PA) 405 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 406 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 407 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 408 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 409 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 410 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 411 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 412 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 413 414 #elif defined(CONFIG_P1010RDB_PB) 415 #define CONFIG_SYS_NAND_ONFI_DETECTION 416 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 417 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 418 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 419 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 420 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 421 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 422 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 423 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 424 #endif 425 426 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 427 #define CONFIG_SYS_MAX_NAND_DEVICE 1 428 #define CONFIG_CMD_NAND 429 430 #if defined(CONFIG_P1010RDB_PA) 431 /* NAND Flash Timing Params */ 432 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 433 FTIM0_NAND_TWP(0x0C) | \ 434 FTIM0_NAND_TWCHT(0x04) | \ 435 FTIM0_NAND_TWH(0x05) 436 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 437 FTIM1_NAND_TWBE(0x1d) | \ 438 FTIM1_NAND_TRR(0x07) | \ 439 FTIM1_NAND_TRP(0x0c) 440 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 441 FTIM2_NAND_TREH(0x05) | \ 442 FTIM2_NAND_TWHRE(0x0f) 443 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 444 445 #elif defined(CONFIG_P1010RDB_PB) 446 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 447 /* ONFI NAND Flash mode0 Timing Params */ 448 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 449 FTIM0_NAND_TWP(0x18) | \ 450 FTIM0_NAND_TWCHT(0x07) | \ 451 FTIM0_NAND_TWH(0x0a)) 452 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 453 FTIM1_NAND_TWBE(0x39) | \ 454 FTIM1_NAND_TRR(0x0e) | \ 455 FTIM1_NAND_TRP(0x18)) 456 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 457 FTIM2_NAND_TREH(0x0a) | \ 458 FTIM2_NAND_TWHRE(0x1e)) 459 #define CONFIG_SYS_NAND_FTIM3 0x0 460 #endif 461 462 #define CONFIG_SYS_NAND_DDR_LAW 11 463 464 /* Set up IFC registers for boot location NOR/NAND */ 465 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 466 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 467 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 468 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 469 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 470 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 471 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 472 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 473 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 474 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 475 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 476 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 477 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 478 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 479 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 480 #else 481 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 482 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 483 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 484 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 485 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 486 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 487 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 488 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 489 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 490 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 491 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 492 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 493 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 494 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 495 #endif 496 497 /* CPLD on IFC */ 498 #define CONFIG_SYS_CPLD_BASE 0xffb00000 499 500 #ifdef CONFIG_PHYS_64BIT 501 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 502 #else 503 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 504 #endif 505 506 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 507 | CSPR_PORT_SIZE_8 \ 508 | CSPR_MSEL_GPCM \ 509 | CSPR_V) 510 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 511 #define CONFIG_SYS_CSOR3 0x0 512 /* CPLD Timing parameters for IFC CS3 */ 513 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 514 FTIM0_GPCM_TEADC(0x0e) | \ 515 FTIM0_GPCM_TEAHC(0x0e)) 516 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 517 FTIM1_GPCM_TRAD(0x1f)) 518 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 519 FTIM2_GPCM_TCH(0x8) | \ 520 FTIM2_GPCM_TWP(0x1f)) 521 #define CONFIG_SYS_CS3_FTIM3 0x0 522 523 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 524 defined(CONFIG_RAMBOOT_NAND) 525 #define CONFIG_SYS_RAMBOOT 526 #define CONFIG_SYS_EXTRA_ENV_RELOC 527 #else 528 #undef CONFIG_SYS_RAMBOOT 529 #endif 530 531 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 532 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 533 #define CONFIG_A003399_NOR_WORKAROUND 534 #endif 535 #endif 536 537 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 538 #define CONFIG_BOARD_EARLY_INIT_R 539 540 #define CONFIG_SYS_INIT_RAM_LOCK 541 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 542 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 543 544 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 545 - GENERATED_GBL_DATA_SIZE) 546 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 547 548 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 549 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 550 551 /* 552 * Config the L2 Cache as L2 SRAM 553 */ 554 #if defined(CONFIG_SPL_BUILD) 555 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 556 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 557 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 558 #define CONFIG_SYS_L2_SIZE (256 << 10) 559 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 560 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 561 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 562 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 563 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 564 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 565 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 566 #elif defined(CONFIG_NAND) 567 #ifdef CONFIG_TPL_BUILD 568 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 569 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 570 #define CONFIG_SYS_L2_SIZE (256 << 10) 571 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 572 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 573 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 574 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 575 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 576 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 577 #else 578 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 579 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 580 #define CONFIG_SYS_L2_SIZE (256 << 10) 581 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 582 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 583 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 584 #endif 585 #endif 586 #endif 587 588 /* Serial Port */ 589 #define CONFIG_CONS_INDEX 1 590 #undef CONFIG_SERIAL_SOFTWARE_FIFO 591 #define CONFIG_SYS_NS16550_SERIAL 592 #define CONFIG_SYS_NS16550_REG_SIZE 1 593 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 594 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 595 #define CONFIG_NS16550_MIN_FUNCTIONS 596 #endif 597 598 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 599 600 #define CONFIG_SYS_BAUDRATE_TABLE \ 601 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 602 603 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 604 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 605 606 /* I2C */ 607 #define CONFIG_SYS_I2C 608 #define CONFIG_SYS_I2C_FSL 609 #define CONFIG_SYS_FSL_I2C_SPEED 400000 610 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 611 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 612 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 613 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 614 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 615 #define I2C_PCA9557_ADDR1 0x18 616 #define I2C_PCA9557_ADDR2 0x19 617 #define I2C_PCA9557_BUS_NUM 0 618 619 /* I2C EEPROM */ 620 #if defined(CONFIG_P1010RDB_PB) 621 #define CONFIG_ID_EEPROM 622 #ifdef CONFIG_ID_EEPROM 623 #define CONFIG_SYS_I2C_EEPROM_NXID 624 #endif 625 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 626 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 627 #define CONFIG_SYS_EEPROM_BUS_NUM 0 628 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 629 #endif 630 /* enable read and write access to EEPROM */ 631 #define CONFIG_CMD_EEPROM 632 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 633 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 634 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 635 636 /* RTC */ 637 #define CONFIG_RTC_PT7C4338 638 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 639 640 /* 641 * SPI interface will not be available in case of NAND boot SPI CS0 will be 642 * used for SLIC 643 */ 644 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 645 /* eSPI - Enhanced SPI */ 646 #define CONFIG_SF_DEFAULT_SPEED 10000000 647 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 648 #endif 649 650 #if defined(CONFIG_TSEC_ENET) 651 #define CONFIG_MII /* MII PHY management */ 652 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 653 #define CONFIG_TSEC1 1 654 #define CONFIG_TSEC1_NAME "eTSEC1" 655 #define CONFIG_TSEC2 1 656 #define CONFIG_TSEC2_NAME "eTSEC2" 657 #define CONFIG_TSEC3 1 658 #define CONFIG_TSEC3_NAME "eTSEC3" 659 660 #define TSEC1_PHY_ADDR 1 661 #define TSEC2_PHY_ADDR 0 662 #define TSEC3_PHY_ADDR 2 663 664 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 665 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 666 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 667 668 #define TSEC1_PHYIDX 0 669 #define TSEC2_PHYIDX 0 670 #define TSEC3_PHYIDX 0 671 672 #define CONFIG_ETHPRIME "eTSEC1" 673 674 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 675 676 /* TBI PHY configuration for SGMII mode */ 677 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 678 TBICR_PHY_RESET \ 679 | TBICR_ANEG_ENABLE \ 680 | TBICR_FULL_DUPLEX \ 681 | TBICR_SPEED1_SET \ 682 ) 683 684 #endif /* CONFIG_TSEC_ENET */ 685 686 /* SATA */ 687 #define CONFIG_FSL_SATA 688 #define CONFIG_FSL_SATA_V2 689 #define CONFIG_LIBATA 690 691 #ifdef CONFIG_FSL_SATA 692 #define CONFIG_SYS_SATA_MAX_DEVICE 2 693 #define CONFIG_SATA1 694 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 695 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 696 #define CONFIG_SATA2 697 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 698 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 699 700 #define CONFIG_CMD_SATA 701 #define CONFIG_LBA48 702 #endif /* #ifdef CONFIG_FSL_SATA */ 703 704 #define CONFIG_MMC 705 #ifdef CONFIG_MMC 706 #define CONFIG_DOS_PARTITION 707 #define CONFIG_FSL_ESDHC 708 #define CONFIG_GENERIC_MMC 709 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 710 #endif 711 712 #define CONFIG_HAS_FSL_DR_USB 713 714 #if defined(CONFIG_HAS_FSL_DR_USB) 715 #define CONFIG_USB_EHCI 716 717 #ifdef CONFIG_USB_EHCI 718 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 719 #define CONFIG_USB_EHCI_FSL 720 #endif 721 #endif 722 723 /* 724 * Environment 725 */ 726 #if defined(CONFIG_SDCARD) 727 #define CONFIG_ENV_IS_IN_MMC 728 #define CONFIG_FSL_FIXED_MMC_LOCATION 729 #define CONFIG_SYS_MMC_ENV_DEV 0 730 #define CONFIG_ENV_SIZE 0x2000 731 #elif defined(CONFIG_SPIFLASH) 732 #define CONFIG_ENV_IS_IN_SPI_FLASH 733 #define CONFIG_ENV_SPI_BUS 0 734 #define CONFIG_ENV_SPI_CS 0 735 #define CONFIG_ENV_SPI_MAX_HZ 10000000 736 #define CONFIG_ENV_SPI_MODE 0 737 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 738 #define CONFIG_ENV_SECT_SIZE 0x10000 739 #define CONFIG_ENV_SIZE 0x2000 740 #elif defined(CONFIG_NAND) 741 #define CONFIG_ENV_IS_IN_NAND 742 #ifdef CONFIG_TPL_BUILD 743 #define CONFIG_ENV_SIZE 0x2000 744 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 745 #else 746 #if defined(CONFIG_P1010RDB_PA) 747 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 748 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 749 #elif defined(CONFIG_P1010RDB_PB) 750 #define CONFIG_ENV_SIZE (16 * 1024) 751 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 752 #endif 753 #endif 754 #define CONFIG_ENV_OFFSET (1024 * 1024) 755 #elif defined(CONFIG_SYS_RAMBOOT) 756 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 757 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 758 #define CONFIG_ENV_SIZE 0x2000 759 #else 760 #define CONFIG_ENV_IS_IN_FLASH 761 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 762 #define CONFIG_ENV_SIZE 0x2000 763 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 764 #endif 765 766 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 767 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 768 769 /* 770 * Command line configuration. 771 */ 772 #define CONFIG_CMD_DATE 773 #define CONFIG_CMD_ERRATA 774 #define CONFIG_CMD_IRQ 775 #define CONFIG_CMD_REGINFO 776 777 #undef CONFIG_WATCHDOG /* watchdog disabled */ 778 779 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 780 || defined(CONFIG_FSL_SATA) 781 #define CONFIG_DOS_PARTITION 782 #endif 783 784 /* Hash command with SHA acceleration supported in hardware */ 785 #ifdef CONFIG_FSL_CAAM 786 #define CONFIG_CMD_HASH 787 #define CONFIG_SHA_HW_ACCEL 788 #endif 789 790 /* 791 * Miscellaneous configurable options 792 */ 793 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 794 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 795 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 796 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 797 798 #if defined(CONFIG_CMD_KGDB) 799 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 800 #else 801 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 802 #endif 803 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 804 /* Print Buffer Size */ 805 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 806 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 807 808 /* 809 * For booting Linux, the board info and command line data 810 * have to be in the first 64 MB of memory, since this is 811 * the maximum mapped by the Linux kernel during initialization. 812 */ 813 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 814 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 815 816 #if defined(CONFIG_CMD_KGDB) 817 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 818 #endif 819 820 /* 821 * Environment Configuration 822 */ 823 824 #if defined(CONFIG_TSEC_ENET) 825 #define CONFIG_HAS_ETH0 826 #define CONFIG_HAS_ETH1 827 #define CONFIG_HAS_ETH2 828 #endif 829 830 #define CONFIG_ROOTPATH "/opt/nfsroot" 831 #define CONFIG_BOOTFILE "uImage" 832 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 833 834 /* default location for tftp and bootm */ 835 #define CONFIG_LOADADDR 1000000 836 837 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 838 839 #define CONFIG_BAUDRATE 115200 840 841 #define CONFIG_EXTRA_ENV_SETTINGS \ 842 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 843 "netdev=eth0\0" \ 844 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 845 "loadaddr=1000000\0" \ 846 "consoledev=ttyS0\0" \ 847 "ramdiskaddr=2000000\0" \ 848 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 849 "fdtaddr=1e00000\0" \ 850 "fdtfile=p1010rdb.dtb\0" \ 851 "bdev=sda1\0" \ 852 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 853 "othbootargs=ramdisk_size=600000\0" \ 854 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 855 "console=$consoledev,$baudrate $othbootargs; " \ 856 "usb start;" \ 857 "fatload usb 0:2 $loadaddr $bootfile;" \ 858 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 859 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 860 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 861 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 862 "console=$consoledev,$baudrate $othbootargs; " \ 863 "usb start;" \ 864 "ext2load usb 0:4 $loadaddr $bootfile;" \ 865 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 866 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 867 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 868 CONFIG_BOOTMODE 869 870 #if defined(CONFIG_P1010RDB_PA) 871 #define CONFIG_BOOTMODE \ 872 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 873 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 874 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 875 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 876 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 877 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 878 879 #elif defined(CONFIG_P1010RDB_PB) 880 #define CONFIG_BOOTMODE \ 881 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 882 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 883 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 884 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 885 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 886 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 887 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 888 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 889 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 890 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 891 #endif 892 893 #define CONFIG_RAMBOOTCOMMAND \ 894 "setenv bootargs root=/dev/ram rw " \ 895 "console=$consoledev,$baudrate $othbootargs; " \ 896 "tftp $ramdiskaddr $ramdiskfile;" \ 897 "tftp $loadaddr $bootfile;" \ 898 "tftp $fdtaddr $fdtfile;" \ 899 "bootm $loadaddr $ramdiskaddr $fdtaddr" 900 901 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 902 903 #include <asm/fsl_secure_boot.h> 904 905 #endif /* __CONFIG_H */ 906