1 /* 2 * Copyright 2010-2012 Freescale Semiconductor, Inc. 3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> 4 * Timur Tabi <timur@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "../board/freescale/common/ics307_clk.h" 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 18 #define CONFIG_SPL_SERIAL_SUPPORT 19 #define CONFIG_SPL_MMC_SUPPORT 20 #define CONFIG_SPL_MMC_MINIMAL 21 #define CONFIG_SPL_FLUSH_IMAGE 22 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 23 #define CONFIG_SPL_LIBGENERIC_SUPPORT 24 #define CONFIG_FSL_LAW /* Use common FSL init code */ 25 #define CONFIG_SYS_TEXT_BASE 0x11001000 26 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 27 #define CONFIG_SPL_PAD_TO 0x20000 28 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 29 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 30 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 31 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 32 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 33 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 34 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 35 #define CONFIG_SPL_MMC_BOOT 36 #ifdef CONFIG_SPL_BUILD 37 #define CONFIG_SPL_COMMON_INIT_DDR 38 #endif 39 #endif 40 41 #ifdef CONFIG_SPIFLASH 42 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 43 #define CONFIG_SPL_SERIAL_SUPPORT 44 #define CONFIG_SPL_SPI_SUPPORT 45 #define CONFIG_SPL_SPI_FLASH_SUPPORT 46 #define CONFIG_SPL_SPI_FLASH_MINIMAL 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_SPL_LIBGENERIC_SUPPORT 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 #define CONFIG_SYS_TEXT_BASE 0x11001000 52 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 53 #define CONFIG_SPL_PAD_TO 0x20000 54 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 60 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 61 #define CONFIG_SPL_SPI_BOOT 62 #ifdef CONFIG_SPL_BUILD 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #endif 65 #endif 66 67 #define CONFIG_NAND_FSL_ELBC 68 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 69 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 70 71 #ifdef CONFIG_NAND 72 #ifdef CONFIG_TPL_BUILD 73 #define CONFIG_SPL_NAND_BOOT 74 #define CONFIG_SPL_FLUSH_IMAGE 75 #define CONFIG_SPL_NAND_INIT 76 #define CONFIG_TPL_SERIAL_SUPPORT 77 #define CONFIG_TPL_LIBGENERIC_SUPPORT 78 #define CONFIG_TPL_NAND_SUPPORT 79 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT 80 #define CONFIG_SPL_COMMON_INIT_DDR 81 #define CONFIG_SPL_MAX_SIZE (128 << 10) 82 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 85 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 86 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 87 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 88 #elif defined(CONFIG_SPL_BUILD) 89 #define CONFIG_SPL_INIT_MINIMAL 90 #define CONFIG_SPL_SERIAL_SUPPORT 91 #define CONFIG_SPL_NAND_SUPPORT 92 #define CONFIG_SPL_FLUSH_IMAGE 93 #define CONFIG_SPL_TEXT_BASE 0xff800000 94 #define CONFIG_SPL_MAX_SIZE 4096 95 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 96 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 97 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 98 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 99 #endif 100 #define CONFIG_SPL_PAD_TO 0x20000 101 #define CONFIG_TPL_PAD_TO 0x20000 102 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 103 #define CONFIG_SYS_TEXT_BASE 0x11001000 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 105 #endif 106 107 /* High Level Configuration Options */ 108 #define CONFIG_BOOKE /* BOOKE */ 109 #define CONFIG_E500 /* BOOKE e500 family */ 110 #define CONFIG_P1022 111 #define CONFIG_P1022DS 112 #define CONFIG_MP /* support multiple processors */ 113 114 #ifndef CONFIG_SYS_TEXT_BASE 115 #define CONFIG_SYS_TEXT_BASE 0xeff40000 116 #endif 117 118 #ifndef CONFIG_RESET_VECTOR_ADDRESS 119 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 120 #endif 121 122 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 123 #define CONFIG_PCI /* Enable PCI/PCIE */ 124 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 125 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 126 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ 127 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 128 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 129 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 130 131 #define CONFIG_ENABLE_36BIT_PHYS 132 133 #ifdef CONFIG_PHYS_64BIT 134 #define CONFIG_ADDR_MAP 135 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 136 #endif 137 138 #define CONFIG_FSL_LAW /* Use common FSL init code */ 139 140 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 141 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 142 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 143 144 /* 145 * These can be toggled for performance analysis, otherwise use default. 146 */ 147 #define CONFIG_L2_CACHE 148 #define CONFIG_BTB 149 150 #define CONFIG_SYS_MEMTEST_START 0x00000000 151 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 152 153 #define CONFIG_SYS_CCSRBAR 0xffe00000 154 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 155 156 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 157 SPL code*/ 158 #ifdef CONFIG_SPL_BUILD 159 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 160 #endif 161 162 /* DDR Setup */ 163 #define CONFIG_DDR_SPD 164 #define CONFIG_VERY_BIG_RAM 165 #define CONFIG_SYS_FSL_DDR3 166 167 #ifdef CONFIG_DDR_ECC 168 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 169 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 170 #endif 171 172 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 173 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 174 175 #define CONFIG_NUM_DDR_CONTROLLERS 1 176 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 177 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 178 179 /* I2C addresses of SPD EEPROMs */ 180 #define CONFIG_SYS_SPD_BUS_NUM 1 181 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 182 183 /* These are used when DDR doesn't use SPD. */ 184 #define CONFIG_SYS_SDRAM_SIZE 2048 185 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 186 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 187 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 188 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F 189 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 190 #define CONFIG_SYS_DDR_TIMING_3 0x00010000 191 #define CONFIG_SYS_DDR_TIMING_0 0x40110104 192 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 193 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca 194 #define CONFIG_SYS_DDR_MODE_1 0x00441221 195 #define CONFIG_SYS_DDR_MODE_2 0x00000000 196 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 197 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 198 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 199 #define CONFIG_SYS_DDR_CONTROL 0xc7000008 200 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 201 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 202 #define CONFIG_SYS_DDR_TIMING_5 0x02401400 203 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 204 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 205 206 /* 207 * Memory map 208 * 209 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 210 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable 211 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 212 * 213 * Localbus cacheable (TBD) 214 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 215 * 216 * Localbus non-cacheable 217 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 218 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 219 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable 220 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 221 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 222 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 223 */ 224 225 /* 226 * Local Bus Definitions 227 */ 228 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ 229 #ifdef CONFIG_PHYS_64BIT 230 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull 231 #else 232 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 233 #endif 234 235 #define CONFIG_FLASH_BR_PRELIM \ 236 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 237 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) 238 239 #ifdef CONFIG_NAND 240 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 241 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 242 #else 243 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 244 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 245 #endif 246 247 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 248 #define CONFIG_SYS_FLASH_QUIET_TEST 249 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 250 251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 252 #define CONFIG_SYS_MAX_FLASH_SECT 1024 253 254 #ifndef CONFIG_SYS_MONITOR_BASE 255 #ifdef CONFIG_SPL_BUILD 256 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 257 #else 258 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 259 #endif 260 #endif 261 262 #define CONFIG_FLASH_CFI_DRIVER 263 #define CONFIG_SYS_FLASH_CFI 264 #define CONFIG_SYS_FLASH_EMPTY_INFO 265 266 /* Nand Flash */ 267 #if defined(CONFIG_NAND_FSL_ELBC) 268 #define CONFIG_SYS_NAND_BASE 0xff800000 269 #ifdef CONFIG_PHYS_64BIT 270 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 271 #else 272 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 273 #endif 274 275 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 276 #define CONFIG_SYS_MAX_NAND_DEVICE 1 277 #define CONFIG_CMD_NAND 1 278 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 279 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE 280 281 /* NAND flash config */ 282 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 283 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 284 | BR_PS_8 /* Port Size = 8 bit */ \ 285 | BR_MS_FCM /* MSEL = FCM */ \ 286 | BR_V) /* valid */ 287 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ 288 | OR_FCM_PGS /* Large Page*/ \ 289 | OR_FCM_CSCT \ 290 | OR_FCM_CST \ 291 | OR_FCM_CHT \ 292 | OR_FCM_SCY_1 \ 293 | OR_FCM_TRLX \ 294 | OR_FCM_EHTR) 295 #ifdef CONFIG_NAND 296 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 297 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 298 #else 299 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 300 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 301 #endif 302 303 #endif /* CONFIG_NAND_FSL_ELBC */ 304 305 #define CONFIG_BOARD_EARLY_INIT_F 306 #define CONFIG_BOARD_EARLY_INIT_R 307 #define CONFIG_MISC_INIT_R 308 #define CONFIG_HWCONFIG 309 310 #define CONFIG_FSL_NGPIXIS 311 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 312 #ifdef CONFIG_PHYS_64BIT 313 #define PIXIS_BASE_PHYS 0xfffdf0000ull 314 #else 315 #define PIXIS_BASE_PHYS PIXIS_BASE 316 #endif 317 318 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 319 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) 320 321 #define PIXIS_LBMAP_SWITCH 7 322 #define PIXIS_LBMAP_MASK 0xF0 323 #define PIXIS_LBMAP_ALTBANK 0x20 324 #define PIXIS_SPD 0x07 325 #define PIXIS_SPD_SYSCLK_MASK 0x07 326 #define PIXIS_ELBC_SPI_MASK 0xc0 327 #define PIXIS_SPI 0x80 328 329 #define CONFIG_SYS_INIT_RAM_LOCK 330 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 331 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 332 333 #define CONFIG_SYS_GBL_DATA_OFFSET \ 334 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 335 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 336 337 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 338 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 339 340 /* 341 * Config the L2 Cache as L2 SRAM 342 */ 343 #if defined(CONFIG_SPL_BUILD) 344 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 345 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 346 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 347 #define CONFIG_SYS_L2_SIZE (256 << 10) 348 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 349 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 350 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 351 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 352 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 353 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 354 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 355 #elif defined(CONFIG_NAND) 356 #ifdef CONFIG_TPL_BUILD 357 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 358 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 359 #define CONFIG_SYS_L2_SIZE (256 << 10) 360 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 361 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 362 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 363 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 364 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 365 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 366 #else 367 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 368 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 369 #define CONFIG_SYS_L2_SIZE (256 << 10) 370 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 371 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 372 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 373 #endif 374 #endif 375 #endif 376 377 /* 378 * Serial Port 379 */ 380 #define CONFIG_CONS_INDEX 1 381 #define CONFIG_SYS_NS16550_SERIAL 382 #define CONFIG_SYS_NS16550_REG_SIZE 1 383 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 384 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 385 #define CONFIG_NS16550_MIN_FUNCTIONS 386 #endif 387 388 #define CONFIG_SYS_BAUDRATE_TABLE \ 389 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 390 391 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 392 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 393 394 /* Video */ 395 396 #ifdef CONFIG_FSL_DIU_FB 397 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 398 #define CONFIG_VIDEO 399 #define CONFIG_CMD_BMP 400 #define CONFIG_CFB_CONSOLE 401 #define CONFIG_VIDEO_SW_CURSOR 402 #define CONFIG_VGA_AS_SINGLE_DEVICE 403 #define CONFIG_VIDEO_LOGO 404 #define CONFIG_VIDEO_BMP_LOGO 405 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 406 /* 407 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 408 * disable empty flash sector detection, which is I/O-intensive. 409 */ 410 #undef CONFIG_SYS_FLASH_EMPTY_INFO 411 #endif 412 413 #ifndef CONFIG_FSL_DIU_FB 414 #endif 415 416 #ifdef CONFIG_ATI 417 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 418 #define CONFIG_VIDEO 419 #define CONFIG_BIOSEMU 420 #define CONFIG_VIDEO_SW_CURSOR 421 #define CONFIG_ATI_RADEON_FB 422 #define CONFIG_VIDEO_LOGO 423 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 424 #define CONFIG_CFB_CONSOLE 425 #define CONFIG_VGA_AS_SINGLE_DEVICE 426 #endif 427 428 /* I2C */ 429 #define CONFIG_SYS_I2C 430 #define CONFIG_SYS_I2C_FSL 431 #define CONFIG_SYS_FSL_I2C_SPEED 400000 432 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 433 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 434 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 435 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 437 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} 438 439 /* 440 * I2C2 EEPROM 441 */ 442 #define CONFIG_ID_EEPROM 443 #define CONFIG_SYS_I2C_EEPROM_NXID 444 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 445 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 446 #define CONFIG_SYS_EEPROM_BUS_NUM 1 447 448 /* 449 * eSPI - Enhanced SPI 450 */ 451 452 #define CONFIG_HARD_SPI 453 454 #define CONFIG_SF_DEFAULT_SPEED 10000000 455 #define CONFIG_SF_DEFAULT_MODE 0 456 457 /* 458 * General PCI 459 * Memory space is mapped 1-1, but I/O space must start from 0. 460 */ 461 462 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 463 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 464 #ifdef CONFIG_PHYS_64BIT 465 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 466 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 467 #else 468 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 469 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 470 #endif 471 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 472 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 473 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 476 #else 477 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 478 #endif 479 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 480 481 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 482 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 483 #ifdef CONFIG_PHYS_64BIT 484 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 485 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 486 #else 487 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 488 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 489 #endif 490 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 491 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 492 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 493 #ifdef CONFIG_PHYS_64BIT 494 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 495 #else 496 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 497 #endif 498 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 499 500 /* controller 3, Slot 1, tgtid 3, Base address b000 */ 501 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 502 #ifdef CONFIG_PHYS_64BIT 503 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 504 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 505 #else 506 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 507 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 508 #endif 509 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 510 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 511 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 512 #ifdef CONFIG_PHYS_64BIT 513 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 514 #else 515 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 516 #endif 517 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 518 519 #ifdef CONFIG_PCI 520 #define CONFIG_PCI_INDIRECT_BRIDGE 521 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 522 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 523 #endif 524 525 /* SATA */ 526 #define CONFIG_LIBATA 527 #define CONFIG_FSL_SATA 528 #define CONFIG_FSL_SATA_V2 529 530 #define CONFIG_SYS_SATA_MAX_DEVICE 2 531 #define CONFIG_SATA1 532 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 533 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 534 #define CONFIG_SATA2 535 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 536 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 537 538 #ifdef CONFIG_FSL_SATA 539 #define CONFIG_LBA48 540 #define CONFIG_CMD_SATA 541 #define CONFIG_DOS_PARTITION 542 #endif 543 544 #define CONFIG_MMC 545 #ifdef CONFIG_MMC 546 #define CONFIG_FSL_ESDHC 547 #define CONFIG_GENERIC_MMC 548 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 549 #endif 550 551 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 552 #define CONFIG_DOS_PARTITION 553 #endif 554 555 #define CONFIG_TSEC_ENET 556 #ifdef CONFIG_TSEC_ENET 557 558 #define CONFIG_TSECV2 559 560 #define CONFIG_MII /* MII PHY management */ 561 #define CONFIG_TSEC1 1 562 #define CONFIG_TSEC1_NAME "eTSEC1" 563 #define CONFIG_TSEC2 1 564 #define CONFIG_TSEC2_NAME "eTSEC2" 565 566 #define TSEC1_PHY_ADDR 1 567 #define TSEC2_PHY_ADDR 2 568 569 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 570 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 571 572 #define TSEC1_PHYIDX 0 573 #define TSEC2_PHYIDX 0 574 575 #define CONFIG_ETHPRIME "eTSEC1" 576 577 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 578 #endif 579 580 /* 581 * Dynamic MTD Partition support with mtdparts 582 */ 583 #define CONFIG_MTD_DEVICE 584 #define CONFIG_MTD_PARTITIONS 585 #define CONFIG_CMD_MTDPARTS 586 #define CONFIG_FLASH_CFI_MTD 587 #ifdef CONFIG_PHYS_64BIT 588 #define MTDIDS_DEFAULT "nor0=fe8000000.nor" 589 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ 590 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 591 "512k(dtb),768k(u-boot)" 592 #else 593 #define MTDIDS_DEFAULT "nor0=e8000000.nor" 594 #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ 595 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ 596 "512k(dtb),768k(u-boot)" 597 #endif 598 599 /* 600 * Environment 601 */ 602 #ifdef CONFIG_SPIFLASH 603 #define CONFIG_ENV_IS_IN_SPI_FLASH 604 #define CONFIG_ENV_SPI_BUS 0 605 #define CONFIG_ENV_SPI_CS 0 606 #define CONFIG_ENV_SPI_MAX_HZ 10000000 607 #define CONFIG_ENV_SPI_MODE 0 608 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 609 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 610 #define CONFIG_ENV_SECT_SIZE 0x10000 611 #elif defined(CONFIG_SDCARD) 612 #define CONFIG_ENV_IS_IN_MMC 613 #define CONFIG_FSL_FIXED_MMC_LOCATION 614 #define CONFIG_ENV_SIZE 0x2000 615 #define CONFIG_SYS_MMC_ENV_DEV 0 616 #elif defined(CONFIG_NAND) 617 #ifdef CONFIG_TPL_BUILD 618 #define CONFIG_ENV_SIZE 0x2000 619 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 620 #else 621 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 622 #endif 623 #define CONFIG_ENV_IS_IN_NAND 624 #define CONFIG_ENV_OFFSET (1024 * 1024) 625 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 626 #elif defined(CONFIG_SYS_RAMBOOT) 627 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 628 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 629 #define CONFIG_ENV_SIZE 0x2000 630 #else 631 #define CONFIG_ENV_IS_IN_FLASH 632 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 633 #define CONFIG_ENV_SIZE 0x2000 634 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 635 #endif 636 637 #define CONFIG_LOADS_ECHO 638 #define CONFIG_SYS_LOADS_BAUD_CHANGE 639 640 /* 641 * Command line configuration. 642 */ 643 #define CONFIG_CMD_ERRATA 644 #define CONFIG_CMD_IRQ 645 #define CONFIG_CMD_REGINFO 646 647 #ifdef CONFIG_PCI 648 #define CONFIG_CMD_PCI 649 #endif 650 651 /* 652 * USB 653 */ 654 #define CONFIG_HAS_FSL_DR_USB 655 #ifdef CONFIG_HAS_FSL_DR_USB 656 #define CONFIG_USB_EHCI 657 658 #ifdef CONFIG_USB_EHCI 659 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 660 #define CONFIG_USB_EHCI_FSL 661 #endif 662 #endif 663 664 /* 665 * Miscellaneous configurable options 666 */ 667 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 668 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 669 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 670 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 671 #ifdef CONFIG_CMD_KGDB 672 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 673 #else 674 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 675 #endif 676 /* Print Buffer Size */ 677 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 678 #define CONFIG_SYS_MAXARGS 16 679 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 680 681 /* 682 * For booting Linux, the board info and command line data 683 * have to be in the first 64 MB of memory, since this is 684 * the maximum mapped by the Linux kernel during initialization. 685 */ 686 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 687 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 688 689 #ifdef CONFIG_CMD_KGDB 690 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 691 #endif 692 693 /* 694 * Environment Configuration 695 */ 696 697 #define CONFIG_HOSTNAME p1022ds 698 #define CONFIG_ROOTPATH "/opt/nfsroot" 699 #define CONFIG_BOOTFILE "uImage" 700 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 701 702 #define CONFIG_LOADADDR 1000000 703 704 705 #define CONFIG_BAUDRATE 115200 706 707 #define CONFIG_EXTRA_ENV_SETTINGS \ 708 "netdev=eth0\0" \ 709 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 710 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 711 "tftpflash=tftpboot $loadaddr $uboot && " \ 712 "protect off $ubootaddr +$filesize && " \ 713 "erase $ubootaddr +$filesize && " \ 714 "cp.b $loadaddr $ubootaddr $filesize && " \ 715 "protect on $ubootaddr +$filesize && " \ 716 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 717 "consoledev=ttyS0\0" \ 718 "ramdiskaddr=2000000\0" \ 719 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 720 "fdtaddr=1e00000\0" \ 721 "fdtfile=p1022ds.dtb\0" \ 722 "bdev=sda3\0" \ 723 "hwconfig=esdhc;audclk:12\0" 724 725 #define CONFIG_HDBOOT \ 726 "setenv bootargs root=/dev/$bdev rw " \ 727 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 728 "tftp $loadaddr $bootfile;" \ 729 "tftp $fdtaddr $fdtfile;" \ 730 "bootm $loadaddr - $fdtaddr" 731 732 #define CONFIG_NFSBOOTCOMMAND \ 733 "setenv bootargs root=/dev/nfs rw " \ 734 "nfsroot=$serverip:$rootpath " \ 735 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 736 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 737 "tftp $loadaddr $bootfile;" \ 738 "tftp $fdtaddr $fdtfile;" \ 739 "bootm $loadaddr - $fdtaddr" 740 741 #define CONFIG_RAMBOOTCOMMAND \ 742 "setenv bootargs root=/dev/ram rw " \ 743 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 744 "tftp $ramdiskaddr $ramdiskfile;" \ 745 "tftp $loadaddr $bootfile;" \ 746 "tftp $fdtaddr $fdtfile;" \ 747 "bootm $loadaddr $ramdiskaddr $fdtaddr" 748 749 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 750 751 #endif 752