1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * Configuration settings for the Freescale i.MX6SX Sabresd board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "mx6_common.h" 13 14 #ifdef CONFIG_SPL 15 #define CONFIG_SPL_MMC_SUPPORT 16 #include "imx6_spl.h" 17 #endif 18 19 /* Size of malloc() pool */ 20 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) 21 22 #define CONFIG_BOARD_EARLY_INIT_F 23 24 #define CONFIG_MXC_UART 25 #define CONFIG_MXC_UART_BASE UART1_BASE 26 27 #ifdef CONFIG_IMX_BOOTAUX 28 /* Set to QSPI2 B flash at default */ 29 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 30 31 #define UPDATE_M4_ENV \ 32 "m4image=m4_qspi.bin\0" \ 33 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ 34 "update_m4_from_sd=" \ 35 "if sf probe 1:0; then " \ 36 "if run loadm4image; then " \ 37 "setexpr fw_sz ${filesize} + 0xffff; " \ 38 "setexpr fw_sz ${fw_sz} / 0x10000; " \ 39 "setexpr fw_sz ${fw_sz} * 0x10000; " \ 40 "sf erase 0x0 ${fw_sz}; " \ 41 "sf write ${loadaddr} 0x0 ${filesize}; " \ 42 "fi; " \ 43 "fi\0" \ 44 "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" 45 #else 46 #define UPDATE_M4_ENV "" 47 #endif 48 49 #define CONFIG_EXTRA_ENV_SETTINGS \ 50 UPDATE_M4_ENV \ 51 "script=boot.scr\0" \ 52 "image=zImage\0" \ 53 "console=ttymxc0\0" \ 54 "fdt_high=0xffffffff\0" \ 55 "initrd_high=0xffffffff\0" \ 56 "fdt_file=imx6sx-sdb.dtb\0" \ 57 "fdt_addr=0x88000000\0" \ 58 "boot_fdt=try\0" \ 59 "ip_dyn=yes\0" \ 60 "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ 61 "mmcdev=2\0" \ 62 "mmcpart=1\0" \ 63 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ 64 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 65 "root=${mmcroot}\0" \ 66 "loadbootscript=" \ 67 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 68 "bootscript=echo Running bootscript from mmc ...; " \ 69 "source\0" \ 70 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 71 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 72 "mmcboot=echo Booting from mmc ...; " \ 73 "run mmcargs; " \ 74 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 75 "if run loadfdt; then " \ 76 "bootz ${loadaddr} - ${fdt_addr}; " \ 77 "else " \ 78 "if test ${boot_fdt} = try; then " \ 79 "bootz; " \ 80 "else " \ 81 "echo WARN: Cannot load the DT; " \ 82 "fi; " \ 83 "fi; " \ 84 "else " \ 85 "bootz; " \ 86 "fi;\0" \ 87 "netargs=setenv bootargs console=${console},${baudrate} " \ 88 "root=/dev/nfs " \ 89 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 90 "netboot=echo Booting from net ...; " \ 91 "run netargs; " \ 92 "if test ${ip_dyn} = yes; then " \ 93 "setenv get_cmd dhcp; " \ 94 "else " \ 95 "setenv get_cmd tftp; " \ 96 "fi; " \ 97 "${get_cmd} ${image}; " \ 98 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 99 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 100 "bootz ${loadaddr} - ${fdt_addr}; " \ 101 "else " \ 102 "if test ${boot_fdt} = try; then " \ 103 "bootz; " \ 104 "else " \ 105 "echo WARN: Cannot load the DT; " \ 106 "fi; " \ 107 "fi; " \ 108 "else " \ 109 "bootz; " \ 110 "fi;\0" 111 112 #define CONFIG_BOOTCOMMAND \ 113 "mmc dev ${mmcdev};" \ 114 "mmc dev ${mmcdev}; if mmc rescan; then " \ 115 "if run loadbootscript; then " \ 116 "run bootscript; " \ 117 "else " \ 118 "if run loadimage; then " \ 119 "run mmcboot; " \ 120 "else run netboot; " \ 121 "fi; " \ 122 "fi; " \ 123 "else run netboot; fi" 124 125 /* Miscellaneous configurable options */ 126 #define CONFIG_SYS_MEMTEST_START 0x80000000 127 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) 128 129 #define CONFIG_STACKSIZE SZ_128K 130 131 /* Physical Memory Map */ 132 #define CONFIG_NR_DRAM_BANKS 1 133 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 134 135 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 136 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 137 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 138 139 #define CONFIG_SYS_INIT_SP_OFFSET \ 140 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 141 #define CONFIG_SYS_INIT_SP_ADDR \ 142 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 143 144 /* MMC Configuration */ 145 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR 146 147 /* I2C Configs */ 148 #define CONFIG_SYS_I2C 149 #define CONFIG_SYS_I2C_MXC 150 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 151 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 152 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 153 #define CONFIG_SYS_I2C_SPEED 100000 154 155 /* PMIC */ 156 #define CONFIG_POWER 157 #define CONFIG_POWER_I2C 158 #define CONFIG_POWER_PFUZE100 159 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 160 161 /* Network */ 162 #define CONFIG_FEC_MXC 163 #define CONFIG_MII 164 165 #define IMX_FEC_BASE ENET_BASE_ADDR 166 #define CONFIG_FEC_MXC_PHYADDR 0x1 167 168 #define CONFIG_FEC_XCV_TYPE RGMII 169 #define CONFIG_ETHPRIME "FEC" 170 171 #define CONFIG_PHYLIB 172 #define CONFIG_PHY_ATHEROS 173 174 #ifdef CONFIG_CMD_USB 175 #define CONFIG_USB_EHCI 176 #define CONFIG_USB_EHCI_MX6 177 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 178 #define CONFIG_USB_HOST_ETHER 179 #define CONFIG_USB_ETHER_ASIX 180 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 181 #define CONFIG_MXC_USB_FLAGS 0 182 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 183 #endif 184 185 #define CONFIG_CMD_PCI 186 #ifdef CONFIG_CMD_PCI 187 #define CONFIG_PCI 188 #define CONFIG_PCI_PNP 189 #define CONFIG_PCI_SCAN_SHOW 190 #define CONFIG_PCIE_IMX 191 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) 192 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) 193 #endif 194 195 #define CONFIG_IMX_THERMAL 196 197 #ifdef CONFIG_FSL_QSPI 198 #define CONFIG_SYS_FSL_QSPI_LE 199 #define CONFIG_SYS_FSL_QSPI_AHB 200 #ifdef CONFIG_MX6SX_SABRESD_REVA 201 #define FSL_QSPI_FLASH_SIZE SZ_16M 202 #else 203 #define FSL_QSPI_FLASH_SIZE SZ_32M 204 #endif 205 #define FSL_QSPI_FLASH_NUM 2 206 #endif 207 208 #ifndef CONFIG_SPL_BUILD 209 #define CONFIG_VIDEO 210 #ifdef CONFIG_VIDEO 211 #define CONFIG_CFB_CONSOLE 212 #define CONFIG_VIDEO_MXS 213 #define CONFIG_VIDEO_LOGO 214 #define CONFIG_VIDEO_SW_CURSOR 215 #define CONFIG_VGA_AS_SINGLE_DEVICE 216 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 217 #define CONFIG_SPLASH_SCREEN 218 #define CONFIG_SPLASH_SCREEN_ALIGN 219 #define CONFIG_CMD_BMP 220 #define CONFIG_BMP_16BPP 221 #define CONFIG_VIDEO_BMP_RLE8 222 #define CONFIG_VIDEO_BMP_LOGO 223 #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR 224 #endif 225 #endif 226 227 #define CONFIG_ENV_OFFSET (8 * SZ_64K) 228 #define CONFIG_ENV_SIZE SZ_8K 229 #define CONFIG_ENV_IS_IN_MMC 230 231 #define CONFIG_SYS_FSL_USDHC_NUM 3 232 #if defined(CONFIG_ENV_IS_IN_MMC) 233 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ 234 #endif 235 236 #endif /* __CONFIG_H */ 237