1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_FSL_LSCH2 13 #define CONFIG_LS1043A 14 #define CONFIG_MP 15 #define CONFIG_SYS_FSL_CLK 16 #define CONFIG_GICV2 17 18 #include <asm/arch/config.h> 19 #ifdef CONFIG_SYS_FSL_SRDS_1 20 #define CONFIG_SYS_HAS_SERDES 21 #endif 22 23 /* Link Definitions */ 24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 25 26 #define CONFIG_SUPPORT_RAW_INITRD 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 #define CONFIG_BOARD_EARLY_INIT_F 1 30 31 #ifndef CONFIG_SYS_FSL_DDR4 32 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 33 #endif 34 35 #define CONFIG_VERY_BIG_RAM 36 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 37 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 39 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 40 41 #define CPU_RELEASE_ADDR secondary_boot_func 42 43 /* Generic Timer Definitions */ 44 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 45 46 /* Size of malloc() pool */ 47 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 48 49 /* Serial Port */ 50 #define CONFIG_CONS_INDEX 1 51 #define CONFIG_SYS_NS16550_SERIAL 52 #define CONFIG_SYS_NS16550_REG_SIZE 1 53 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 54 55 #define CONFIG_BAUDRATE 115200 56 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 57 58 /* SD boot SPL */ 59 #ifdef CONFIG_SD_BOOT 60 #define CONFIG_SPL_FRAMEWORK 61 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 62 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 63 #define CONFIG_SPL_WATCHDOG_SUPPORT 64 #define CONFIG_SPL_SERIAL_SUPPORT 65 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 66 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 67 68 #define CONFIG_SPL_TEXT_BASE 0x10000000 69 #define CONFIG_SPL_MAX_SIZE 0x1d000 70 #define CONFIG_SPL_STACK 0x1001e000 71 #define CONFIG_SPL_PAD_TO 0x1d000 72 73 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 74 CONFIG_SYS_MONITOR_LEN) 75 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 76 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 77 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 78 #define CONFIG_SYS_MONITOR_LEN 0xa0000 79 #endif 80 81 /* NAND SPL */ 82 #ifdef CONFIG_NAND_BOOT 83 #define CONFIG_SPL_PBL_PAD 84 #define CONFIG_SPL_FRAMEWORK 85 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 86 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 87 #define CONFIG_SPL_WATCHDOG_SUPPORT 88 #define CONFIG_SPL_SERIAL_SUPPORT 89 #define CONFIG_SPL_TEXT_BASE 0x10000000 90 #define CONFIG_SPL_MAX_SIZE 0x1a000 91 #define CONFIG_SPL_STACK 0x1001d000 92 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 93 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 94 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 95 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 96 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 97 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 98 #define CONFIG_SYS_MONITOR_LEN 0xa0000 99 #endif 100 101 /* IFC */ 102 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 103 #define CONFIG_FSL_IFC 104 /* 105 * CONFIG_SYS_FLASH_BASE has the final address (core view) 106 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 107 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 108 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 109 */ 110 #define CONFIG_SYS_FLASH_BASE 0x60000000 111 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 112 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 113 114 #ifndef CONFIG_SYS_NO_FLASH 115 #define CONFIG_FLASH_CFI_DRIVER 116 #define CONFIG_SYS_FLASH_CFI 117 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 118 #define CONFIG_SYS_FLASH_QUIET_TEST 119 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 120 #endif 121 #endif 122 123 /* I2C */ 124 #define CONFIG_SYS_I2C 125 #define CONFIG_SYS_I2C_MXC 126 #define CONFIG_SYS_I2C_MXC_I2C1 127 #define CONFIG_SYS_I2C_MXC_I2C2 128 #define CONFIG_SYS_I2C_MXC_I2C3 129 #define CONFIG_SYS_I2C_MXC_I2C4 130 131 /* PCIe */ 132 #define CONFIG_PCI /* Enable PCI/PCIE */ 133 #define CONFIG_PCIE1 /* PCIE controller 1 */ 134 #define CONFIG_PCIE2 /* PCIE controller 2 */ 135 #define CONFIG_PCIE3 /* PCIE controller 3 */ 136 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 137 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 138 139 #define CONFIG_SYS_PCI_64BIT 140 141 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 142 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 143 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 144 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 145 146 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 147 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 148 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 149 150 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 151 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 152 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 153 154 #ifdef CONFIG_PCI 155 #define CONFIG_NET_MULTI 156 #define CONFIG_PCI_PNP 157 #define CONFIG_E1000 158 #define CONFIG_PCI_SCAN_SHOW 159 #define CONFIG_CMD_PCI 160 #endif 161 162 /* Command line configuration */ 163 #define CONFIG_CMD_ENV 164 #define CONFIG_MENU 165 #define CONFIG_CMD_PXE 166 167 /* MMC */ 168 #define CONFIG_MMC 169 #ifdef CONFIG_MMC 170 #define CONFIG_FSL_ESDHC 171 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 172 #define CONFIG_GENERIC_MMC 173 #define CONFIG_DOS_PARTITION 174 #endif 175 176 /* DSPI */ 177 #define CONFIG_FSL_DSPI 178 #ifdef CONFIG_FSL_DSPI 179 #define CONFIG_DM_SPI_FLASH 180 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 181 #define CONFIG_SPI_FLASH_SST /* cs1 */ 182 #define CONFIG_SPI_FLASH_EON /* cs2 */ 183 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 184 #define CONFIG_SF_DEFAULT_BUS 1 185 #define CONFIG_SF_DEFAULT_CS 0 186 #endif 187 #endif 188 189 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 190 191 /* FMan ucode */ 192 #define CONFIG_SYS_DPAA_FMAN 193 #ifdef CONFIG_SYS_DPAA_FMAN 194 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 195 196 #ifdef CONFIG_NAND_BOOT 197 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 198 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 199 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 200 #elif defined(CONFIG_SD_BOOT) 201 /* 202 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 203 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 204 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 205 */ 206 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 207 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 208 #elif defined(CONFIG_QSPI_BOOT) 209 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 210 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 211 #define CONFIG_ENV_SPI_BUS 0 212 #define CONFIG_ENV_SPI_CS 0 213 #define CONFIG_ENV_SPI_MAX_HZ 1000000 214 #define CONFIG_ENV_SPI_MODE 0x03 215 #else 216 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 217 /* FMan fireware Pre-load address */ 218 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 219 #endif 220 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 221 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 222 #endif 223 224 /* Miscellaneous configurable options */ 225 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 226 #define CONFIG_ARCH_EARLY_INIT_R 227 #define CONFIG_BOARD_LATE_INIT 228 229 #define CONFIG_HWCONFIG 230 #define HWCONFIG_BUFFER_SIZE 128 231 232 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 233 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 234 "5m(kernel),1m(dtb),9m(file_system)" 235 #else 236 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 237 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 238 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 239 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 240 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 241 "40m(nor_bank4_fit);7e800000.flash:" \ 242 "1m(nand_uboot),1m(nand_uboot_env)," \ 243 "20m(nand_fit);spi0.0:1m(uboot)," \ 244 "5m(kernel),1m(dtb),9m(file_system)" 245 #endif 246 247 /* Initial environment variables */ 248 #define CONFIG_EXTRA_ENV_SETTINGS \ 249 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 250 "loadaddr=0x80100000\0" \ 251 "fdt_high=0xffffffffffffffff\0" \ 252 "initrd_high=0xffffffffffffffff\0" \ 253 "kernel_start=0x61100000\0" \ 254 "kernel_load=0xa0000000\0" \ 255 "kernel_size=0x2800000\0" \ 256 "console=ttyS0,115200\0" \ 257 "mtdparts=" MTDPARTS_DEFAULT "\0" 258 259 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 260 "earlycon=uart8250,mmio,0x21c0500 " \ 261 MTDPARTS_DEFAULT 262 263 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 264 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 265 "e0000 f00000 && bootm $kernel_load" 266 #else 267 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 268 "$kernel_size && bootm $kernel_load" 269 #endif 270 271 /* Monitor Command Prompt */ 272 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 273 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 274 sizeof(CONFIG_SYS_PROMPT) + 16) 275 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 276 #define CONFIG_SYS_LONGHELP 277 #define CONFIG_CMDLINE_EDITING 1 278 #define CONFIG_AUTO_COMPLETE 279 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 280 281 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 282 283 /* Hash command with SHA acceleration supported in hardware */ 284 #ifdef CONFIG_FSL_CAAM 285 #define CONFIG_CMD_HASH 286 #define CONFIG_SHA_HW_ACCEL 287 #endif 288 289 #endif /* __LS1043A_COMMON_H */ 290