1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_USB_EHCI 18 #if defined(CONFIG_PPC_T2080) 19 #define CONFIG_T2080QDS 20 #define CONFIG_FSL_SATA_V2 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */ 24 #elif defined(CONFIG_PPC_T2081) 25 #define CONFIG_T2081QDS 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 30 #define CONFIG_E500 /* BOOKE e500 family */ 31 #define CONFIG_E500MC /* BOOKE e500mc family */ 32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_MP /* support multiple processors */ 34 #define CONFIG_ENABLE_36BIT_PHYS 35 36 #ifdef CONFIG_PHYS_64BIT 37 #define CONFIG_ADDR_MAP 1 38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_IFC /* Enable IFC Support */ 44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 50 #if defined(CONFIG_PPC_T2080) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 52 #elif defined(CONFIG_PPC_T2081) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 54 #endif 55 56 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 57 #define CONFIG_SPL_SERIAL_SUPPORT 58 #define CONFIG_SPL_FLUSH_IMAGE 59 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 60 #define CONFIG_FSL_LAW /* Use common FSL init code */ 61 #define CONFIG_SYS_TEXT_BASE 0x00201000 62 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 63 #define CONFIG_SPL_PAD_TO 0x40000 64 #define CONFIG_SPL_MAX_SIZE 0x28000 65 #define RESET_VECTOR_OFFSET 0x27FFC 66 #define BOOT_PAGE_OFFSET 0x27000 67 #ifdef CONFIG_SPL_BUILD 68 #define CONFIG_SPL_SKIP_RELOCATE 69 #define CONFIG_SPL_COMMON_INIT_DDR 70 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 71 #define CONFIG_SYS_NO_FLASH 72 #endif 73 74 #ifdef CONFIG_NAND 75 #define CONFIG_SPL_NAND_SUPPORT 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 77 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 78 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 81 #define CONFIG_SPL_NAND_BOOT 82 #endif 83 84 #ifdef CONFIG_SPIFLASH 85 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 86 #define CONFIG_SPL_SPI_SUPPORT 87 #define CONFIG_SPL_SPI_FLASH_SUPPORT 88 #define CONFIG_SPL_SPI_FLASH_MINIMAL 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 93 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 94 #ifndef CONFIG_SPL_BUILD 95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 96 #endif 97 #define CONFIG_SPL_SPI_BOOT 98 #endif 99 100 #ifdef CONFIG_SDCARD 101 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 102 #define CONFIG_SPL_MMC_SUPPORT 103 #define CONFIG_SPL_MMC_MINIMAL 104 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 105 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 106 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 107 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 108 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 109 #ifndef CONFIG_SPL_BUILD 110 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 111 #endif 112 #define CONFIG_SPL_MMC_BOOT 113 #endif 114 115 #endif /* CONFIG_RAMBOOT_PBL */ 116 117 #define CONFIG_SRIO_PCIE_BOOT_MASTER 118 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 119 /* Set 1M boot space */ 120 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 121 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 122 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 123 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 124 #define CONFIG_SYS_NO_FLASH 125 #endif 126 127 #ifndef CONFIG_SYS_TEXT_BASE 128 #define CONFIG_SYS_TEXT_BASE 0xeff40000 129 #endif 130 131 #ifndef CONFIG_RESET_VECTOR_ADDRESS 132 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 133 #endif 134 135 /* 136 * These can be toggled for performance analysis, otherwise use default. 137 */ 138 #define CONFIG_SYS_CACHE_STASHING 139 #define CONFIG_BTB /* toggle branch predition */ 140 #define CONFIG_DDR_ECC 141 #ifdef CONFIG_DDR_ECC 142 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 143 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 144 #endif 145 146 #ifndef CONFIG_SYS_NO_FLASH 147 #define CONFIG_FLASH_CFI_DRIVER 148 #define CONFIG_SYS_FLASH_CFI 149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 150 #endif 151 152 #if defined(CONFIG_SPIFLASH) 153 #define CONFIG_SYS_EXTRA_ENV_RELOC 154 #define CONFIG_ENV_IS_IN_SPI_FLASH 155 #define CONFIG_ENV_SPI_BUS 0 156 #define CONFIG_ENV_SPI_CS 0 157 #define CONFIG_ENV_SPI_MAX_HZ 10000000 158 #define CONFIG_ENV_SPI_MODE 0 159 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 160 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 161 #define CONFIG_ENV_SECT_SIZE 0x10000 162 #elif defined(CONFIG_SDCARD) 163 #define CONFIG_SYS_EXTRA_ENV_RELOC 164 #define CONFIG_ENV_IS_IN_MMC 165 #define CONFIG_SYS_MMC_ENV_DEV 0 166 #define CONFIG_ENV_SIZE 0x2000 167 #define CONFIG_ENV_OFFSET (512 * 0x800) 168 #elif defined(CONFIG_NAND) 169 #define CONFIG_SYS_EXTRA_ENV_RELOC 170 #define CONFIG_ENV_IS_IN_NAND 171 #define CONFIG_ENV_SIZE 0x2000 172 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 173 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 174 #define CONFIG_ENV_IS_IN_REMOTE 175 #define CONFIG_ENV_ADDR 0xffe20000 176 #define CONFIG_ENV_SIZE 0x2000 177 #elif defined(CONFIG_ENV_IS_NOWHERE) 178 #define CONFIG_ENV_SIZE 0x2000 179 #else 180 #define CONFIG_ENV_IS_IN_FLASH 181 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 182 #define CONFIG_ENV_SIZE 0x2000 183 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 184 #endif 185 186 #ifndef __ASSEMBLY__ 187 unsigned long get_board_sys_clk(void); 188 unsigned long get_board_ddr_clk(void); 189 #endif 190 191 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 192 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 193 194 /* 195 * Config the L3 Cache as L3 SRAM 196 */ 197 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 198 #define CONFIG_SYS_L3_SIZE (512 << 10) 199 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 200 #ifdef CONFIG_RAMBOOT_PBL 201 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 202 #endif 203 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 204 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 205 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 206 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 207 208 #define CONFIG_SYS_DCSRBAR 0xf0000000 209 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 210 211 /* EEPROM */ 212 #define CONFIG_ID_EEPROM 213 #define CONFIG_SYS_I2C_EEPROM_NXID 214 #define CONFIG_SYS_EEPROM_BUS_NUM 0 215 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 217 218 /* 219 * DDR Setup 220 */ 221 #define CONFIG_VERY_BIG_RAM 222 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 223 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 224 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 225 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 226 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 227 #define CONFIG_DDR_SPD 228 #define CONFIG_SYS_FSL_DDR3 229 #define CONFIG_FSL_DDR_INTERACTIVE 230 #define CONFIG_SYS_SPD_BUS_NUM 0 231 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 232 #define SPD_EEPROM_ADDRESS1 0x51 233 #define SPD_EEPROM_ADDRESS2 0x52 234 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 235 #define CTRL_INTLV_PREFERED cacheline 236 237 /* 238 * IFC Definitions 239 */ 240 #define CONFIG_SYS_FLASH_BASE 0xe0000000 241 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 242 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 243 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 244 + 0x8000000) | \ 245 CSPR_PORT_SIZE_16 | \ 246 CSPR_MSEL_NOR | \ 247 CSPR_V) 248 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 249 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 250 CSPR_PORT_SIZE_16 | \ 251 CSPR_MSEL_NOR | \ 252 CSPR_V) 253 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 254 /* NOR Flash Timing Params */ 255 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 256 257 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 258 FTIM0_NOR_TEADC(0x5) | \ 259 FTIM0_NOR_TEAHC(0x5)) 260 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 261 FTIM1_NOR_TRAD_NOR(0x1A) |\ 262 FTIM1_NOR_TSEQRAD_NOR(0x13)) 263 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 264 FTIM2_NOR_TCH(0x4) | \ 265 FTIM2_NOR_TWPH(0x0E) | \ 266 FTIM2_NOR_TWP(0x1c)) 267 #define CONFIG_SYS_NOR_FTIM3 0x0 268 269 #define CONFIG_SYS_FLASH_QUIET_TEST 270 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 271 272 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 273 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 274 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 275 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 276 277 #define CONFIG_SYS_FLASH_EMPTY_INFO 278 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 279 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 280 281 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 282 #define QIXIS_BASE 0xffdf0000 283 #define QIXIS_LBMAP_SWITCH 6 284 #define QIXIS_LBMAP_MASK 0x0f 285 #define QIXIS_LBMAP_SHIFT 0 286 #define QIXIS_LBMAP_DFLTBANK 0x00 287 #define QIXIS_LBMAP_ALTBANK 0x04 288 #define QIXIS_LBMAP_NAND 0x09 289 #define QIXIS_LBMAP_SD 0x00 290 #define QIXIS_RCW_SRC_NAND 0x104 291 #define QIXIS_RCW_SRC_SD 0x040 292 #define QIXIS_RST_CTL_RESET 0x83 293 #define QIXIS_RST_FORCE_MEM 0x1 294 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 295 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 296 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 297 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 298 299 #define CONFIG_SYS_CSPR3_EXT (0xf) 300 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 301 | CSPR_PORT_SIZE_8 \ 302 | CSPR_MSEL_GPCM \ 303 | CSPR_V) 304 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 305 #define CONFIG_SYS_CSOR3 0x0 306 /* QIXIS Timing parameters for IFC CS3 */ 307 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 308 FTIM0_GPCM_TEADC(0x0e) | \ 309 FTIM0_GPCM_TEAHC(0x0e)) 310 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 311 FTIM1_GPCM_TRAD(0x3f)) 312 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 313 FTIM2_GPCM_TCH(0x8) | \ 314 FTIM2_GPCM_TWP(0x1f)) 315 #define CONFIG_SYS_CS3_FTIM3 0x0 316 317 /* NAND Flash on IFC */ 318 #define CONFIG_NAND_FSL_IFC 319 #define CONFIG_SYS_NAND_BASE 0xff800000 320 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 321 322 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 323 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 324 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 325 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 326 | CSPR_V) 327 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 328 329 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 330 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 331 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 332 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 333 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 334 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 335 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 336 337 #define CONFIG_SYS_NAND_ONFI_DETECTION 338 339 /* ONFI NAND Flash mode0 Timing Params */ 340 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 341 FTIM0_NAND_TWP(0x18) | \ 342 FTIM0_NAND_TWCHT(0x07) | \ 343 FTIM0_NAND_TWH(0x0a)) 344 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 345 FTIM1_NAND_TWBE(0x39) | \ 346 FTIM1_NAND_TRR(0x0e) | \ 347 FTIM1_NAND_TRP(0x18)) 348 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 349 FTIM2_NAND_TREH(0x0a) | \ 350 FTIM2_NAND_TWHRE(0x1e)) 351 #define CONFIG_SYS_NAND_FTIM3 0x0 352 353 #define CONFIG_SYS_NAND_DDR_LAW 11 354 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 355 #define CONFIG_SYS_MAX_NAND_DEVICE 1 356 #define CONFIG_CMD_NAND 357 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 358 359 #if defined(CONFIG_NAND) 360 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 361 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 362 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 363 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 364 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 365 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 366 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 367 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 368 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 369 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 370 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 371 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 372 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 373 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 374 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 375 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 376 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 377 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 378 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 379 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 380 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 381 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 382 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 383 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 384 #else 385 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 386 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 387 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 388 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 389 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 390 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 391 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 392 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 393 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 394 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 395 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 396 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 397 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 398 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 399 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 400 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 401 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 402 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 403 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 404 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 405 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 406 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 407 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 408 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 409 #endif 410 411 #if defined(CONFIG_RAMBOOT_PBL) 412 #define CONFIG_SYS_RAMBOOT 413 #endif 414 415 #ifdef CONFIG_SPL_BUILD 416 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 417 #else 418 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 419 #endif 420 421 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 422 #define CONFIG_MISC_INIT_R 423 #define CONFIG_HWCONFIG 424 425 /* define to use L1 as initial stack */ 426 #define CONFIG_L1_INIT_RAM 427 #define CONFIG_SYS_INIT_RAM_LOCK 428 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 431 /* The assembler doesn't like typecast */ 432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 433 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 434 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 435 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 436 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 437 GENERATED_GBL_DATA_SIZE) 438 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 439 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 440 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 441 442 /* 443 * Serial Port 444 */ 445 #define CONFIG_CONS_INDEX 1 446 #define CONFIG_SYS_NS16550_SERIAL 447 #define CONFIG_SYS_NS16550_REG_SIZE 1 448 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 449 #define CONFIG_SYS_BAUDRATE_TABLE \ 450 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 451 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 452 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 453 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 454 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 455 456 /* 457 * I2C 458 */ 459 #define CONFIG_SYS_I2C 460 #define CONFIG_SYS_I2C_FSL 461 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 462 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 463 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 464 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 465 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 466 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 467 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 468 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 469 #define CONFIG_SYS_FSL_I2C_SPEED 100000 470 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 471 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 472 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 473 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 474 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 475 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 476 #define I2C_MUX_CH_DEFAULT 0x8 477 478 #define I2C_MUX_CH_VOL_MONITOR 0xa 479 480 /* Voltage monitor on channel 2*/ 481 #define I2C_VOL_MONITOR_ADDR 0x40 482 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 483 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 484 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 485 486 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 487 #ifndef CONFIG_SPL_BUILD 488 #define CONFIG_VID 489 #endif 490 #define CONFIG_VOL_MONITOR_IR36021_SET 491 #define CONFIG_VOL_MONITOR_IR36021_READ 492 /* The lowest and highest voltage allowed for T208xQDS */ 493 #define VDD_MV_MIN 819 494 #define VDD_MV_MAX 1212 495 496 /* 497 * RapidIO 498 */ 499 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 500 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 501 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 502 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 503 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 504 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 505 /* 506 * for slave u-boot IMAGE instored in master memory space, 507 * PHYS must be aligned based on the SIZE 508 */ 509 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 513 /* 514 * for slave UCODE and ENV instored in master memory space, 515 * PHYS must be aligned based on the SIZE 516 */ 517 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 518 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 519 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 520 521 /* slave core release by master*/ 522 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 523 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 524 525 /* 526 * SRIO_PCIE_BOOT - SLAVE 527 */ 528 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 529 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 530 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 531 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 532 #endif 533 534 /* 535 * eSPI - Enhanced SPI 536 */ 537 #ifdef CONFIG_SPI_FLASH 538 #ifndef CONFIG_SPL_BUILD 539 #endif 540 541 #define CONFIG_SPI_FLASH_BAR 542 #define CONFIG_SF_DEFAULT_SPEED 10000000 543 #define CONFIG_SF_DEFAULT_MODE 0 544 #endif 545 546 /* 547 * General PCI 548 * Memory space is mapped 1-1, but I/O space must start from 0. 549 */ 550 #define CONFIG_PCI /* Enable PCI/PCIE */ 551 #define CONFIG_PCIE1 /* PCIE controller 1 */ 552 #define CONFIG_PCIE2 /* PCIE controller 2 */ 553 #define CONFIG_PCIE3 /* PCIE controller 3 */ 554 #define CONFIG_PCIE4 /* PCIE controller 4 */ 555 #define CONFIG_FSL_PCIE_RESET 556 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 557 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 558 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 559 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 560 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 561 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 562 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 563 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 564 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 565 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 566 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 567 568 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 569 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 570 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 571 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 572 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 573 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 574 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 575 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 576 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 577 578 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 579 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 580 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 581 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 582 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 583 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 584 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 585 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 586 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 587 588 /* controller 4, Base address 203000 */ 589 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 590 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 591 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 592 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 593 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 594 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 595 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 596 597 #ifdef CONFIG_PCI 598 #define CONFIG_PCI_INDIRECT_BRIDGE 599 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 600 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 601 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 602 #define CONFIG_DOS_PARTITION 603 #endif 604 605 /* Qman/Bman */ 606 #ifndef CONFIG_NOBQFMAN 607 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 608 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 609 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 610 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 611 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 612 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 613 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 614 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 615 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 616 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 617 CONFIG_SYS_BMAN_CENA_SIZE) 618 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 619 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 620 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 621 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 622 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 623 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 624 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 625 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 626 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 627 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 628 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 629 CONFIG_SYS_QMAN_CENA_SIZE) 630 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 631 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 632 633 #define CONFIG_SYS_DPAA_FMAN 634 #define CONFIG_SYS_DPAA_PME 635 #define CONFIG_SYS_PMAN 636 #define CONFIG_SYS_DPAA_DCE 637 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 638 #define CONFIG_SYS_INTERLAKEN 639 640 /* Default address of microcode for the Linux Fman driver */ 641 #if defined(CONFIG_SPIFLASH) 642 /* 643 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 644 * env, so we got 0x110000. 645 */ 646 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 647 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 648 #elif defined(CONFIG_SDCARD) 649 /* 650 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 651 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 652 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 653 */ 654 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 655 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 656 #elif defined(CONFIG_NAND) 657 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 658 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 659 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 660 /* 661 * Slave has no ucode locally, it can fetch this from remote. When implementing 662 * in two corenet boards, slave's ucode could be stored in master's memory 663 * space, the address can be mapped from slave TLB->slave LAW-> 664 * slave SRIO or PCIE outbound window->master inbound window-> 665 * master LAW->the ucode address in master's memory space. 666 */ 667 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 668 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 669 #else 670 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 671 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 672 #endif 673 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 674 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 675 #endif /* CONFIG_NOBQFMAN */ 676 677 #ifdef CONFIG_SYS_DPAA_FMAN 678 #define CONFIG_FMAN_ENET 679 #define CONFIG_PHYLIB_10G 680 #define CONFIG_PHY_VITESSE 681 #define CONFIG_PHY_REALTEK 682 #define CONFIG_PHY_TERANETICS 683 #define RGMII_PHY1_ADDR 0x1 684 #define RGMII_PHY2_ADDR 0x2 685 #define FM1_10GEC1_PHY_ADDR 0x3 686 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 687 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 688 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 689 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 690 #endif 691 692 #ifdef CONFIG_FMAN_ENET 693 #define CONFIG_MII /* MII PHY management */ 694 #define CONFIG_ETHPRIME "FM1@DTSEC3" 695 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 696 #endif 697 698 /* 699 * SATA 700 */ 701 #ifdef CONFIG_FSL_SATA_V2 702 #define CONFIG_LIBATA 703 #define CONFIG_FSL_SATA 704 #define CONFIG_SYS_SATA_MAX_DEVICE 2 705 #define CONFIG_SATA1 706 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 707 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 708 #define CONFIG_SATA2 709 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 710 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 711 #define CONFIG_LBA48 712 #define CONFIG_CMD_SATA 713 #define CONFIG_DOS_PARTITION 714 #endif 715 716 /* 717 * USB 718 */ 719 #ifdef CONFIG_USB_EHCI 720 #define CONFIG_USB_EHCI_FSL 721 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 722 #define CONFIG_HAS_FSL_DR_USB 723 #endif 724 725 /* 726 * SDHC 727 */ 728 #ifdef CONFIG_MMC 729 #define CONFIG_FSL_ESDHC 730 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 731 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 732 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 733 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 734 #define CONFIG_GENERIC_MMC 735 #define CONFIG_DOS_PARTITION 736 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 737 #endif 738 739 /* 740 * Dynamic MTD Partition support with mtdparts 741 */ 742 #ifndef CONFIG_SYS_NO_FLASH 743 #define CONFIG_MTD_DEVICE 744 #define CONFIG_MTD_PARTITIONS 745 #define CONFIG_CMD_MTDPARTS 746 #define CONFIG_FLASH_CFI_MTD 747 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 748 "spi0=spife110000.0" 749 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 750 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 751 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 752 "1m(uboot),5m(kernel),128k(dtb),-(user)" 753 #endif 754 755 /* 756 * Environment 757 */ 758 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 759 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 760 761 /* 762 * Command line configuration. 763 */ 764 #define CONFIG_CMD_ERRATA 765 #define CONFIG_CMD_IRQ 766 #define CONFIG_CMD_REGINFO 767 768 #ifdef CONFIG_PCI 769 #define CONFIG_CMD_PCI 770 #endif 771 772 /* Hash command with SHA acceleration supported in hardware */ 773 #ifdef CONFIG_FSL_CAAM 774 #define CONFIG_CMD_HASH 775 #define CONFIG_SHA_HW_ACCEL 776 #endif 777 778 /* 779 * Miscellaneous configurable options 780 */ 781 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 782 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 783 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 784 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 785 #ifdef CONFIG_CMD_KGDB 786 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 787 #else 788 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 789 #endif 790 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 791 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 792 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 793 794 /* 795 * For booting Linux, the board info and command line data 796 * have to be in the first 64 MB of memory, since this is 797 * the maximum mapped by the Linux kernel during initialization. 798 */ 799 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 800 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 801 802 #ifdef CONFIG_CMD_KGDB 803 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 804 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 805 #endif 806 807 /* 808 * Environment Configuration 809 */ 810 #define CONFIG_ROOTPATH "/opt/nfsroot" 811 #define CONFIG_BOOTFILE "uImage" 812 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 813 814 /* default location for tftp and bootm */ 815 #define CONFIG_LOADADDR 1000000 816 #define CONFIG_BAUDRATE 115200 817 #define __USB_PHY_TYPE utmi 818 819 #define CONFIG_EXTRA_ENV_SETTINGS \ 820 "hwconfig=fsl_ddr:" \ 821 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 822 "bank_intlv=auto;" \ 823 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 824 "netdev=eth0\0" \ 825 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 826 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 827 "tftpflash=tftpboot $loadaddr $uboot && " \ 828 "protect off $ubootaddr +$filesize && " \ 829 "erase $ubootaddr +$filesize && " \ 830 "cp.b $loadaddr $ubootaddr $filesize && " \ 831 "protect on $ubootaddr +$filesize && " \ 832 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 833 "consoledev=ttyS0\0" \ 834 "ramdiskaddr=2000000\0" \ 835 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 836 "fdtaddr=1e00000\0" \ 837 "fdtfile=t2080qds/t2080qds.dtb\0" \ 838 "bdev=sda3\0" 839 840 /* 841 * For emulation this causes u-boot to jump to the start of the 842 * proof point app code automatically 843 */ 844 #define CONFIG_PROOF_POINTS \ 845 "setenv bootargs root=/dev/$bdev rw " \ 846 "console=$consoledev,$baudrate $othbootargs;" \ 847 "cpu 1 release 0x29000000 - - -;" \ 848 "cpu 2 release 0x29000000 - - -;" \ 849 "cpu 3 release 0x29000000 - - -;" \ 850 "cpu 4 release 0x29000000 - - -;" \ 851 "cpu 5 release 0x29000000 - - -;" \ 852 "cpu 6 release 0x29000000 - - -;" \ 853 "cpu 7 release 0x29000000 - - -;" \ 854 "go 0x29000000" 855 856 #define CONFIG_HVBOOT \ 857 "setenv bootargs config-addr=0x60000000; " \ 858 "bootm 0x01000000 - 0x00f00000" 859 860 #define CONFIG_ALU \ 861 "setenv bootargs root=/dev/$bdev rw " \ 862 "console=$consoledev,$baudrate $othbootargs;" \ 863 "cpu 1 release 0x01000000 - - -;" \ 864 "cpu 2 release 0x01000000 - - -;" \ 865 "cpu 3 release 0x01000000 - - -;" \ 866 "cpu 4 release 0x01000000 - - -;" \ 867 "cpu 5 release 0x01000000 - - -;" \ 868 "cpu 6 release 0x01000000 - - -;" \ 869 "cpu 7 release 0x01000000 - - -;" \ 870 "go 0x01000000" 871 872 #define CONFIG_LINUX \ 873 "setenv bootargs root=/dev/ram rw " \ 874 "console=$consoledev,$baudrate $othbootargs;" \ 875 "setenv ramdiskaddr 0x02000000;" \ 876 "setenv fdtaddr 0x00c00000;" \ 877 "setenv loadaddr 0x1000000;" \ 878 "bootm $loadaddr $ramdiskaddr $fdtaddr" 879 880 #define CONFIG_HDBOOT \ 881 "setenv bootargs root=/dev/$bdev rw " \ 882 "console=$consoledev,$baudrate $othbootargs;" \ 883 "tftp $loadaddr $bootfile;" \ 884 "tftp $fdtaddr $fdtfile;" \ 885 "bootm $loadaddr - $fdtaddr" 886 887 #define CONFIG_NFSBOOTCOMMAND \ 888 "setenv bootargs root=/dev/nfs rw " \ 889 "nfsroot=$serverip:$rootpath " \ 890 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 891 "console=$consoledev,$baudrate $othbootargs;" \ 892 "tftp $loadaddr $bootfile;" \ 893 "tftp $fdtaddr $fdtfile;" \ 894 "bootm $loadaddr - $fdtaddr" 895 896 #define CONFIG_RAMBOOTCOMMAND \ 897 "setenv bootargs root=/dev/ram rw " \ 898 "console=$consoledev,$baudrate $othbootargs;" \ 899 "tftp $ramdiskaddr $ramdiskfile;" \ 900 "tftp $loadaddr $bootfile;" \ 901 "tftp $fdtaddr $fdtfile;" \ 902 "bootm $loadaddr $ramdiskaddr $fdtaddr" 903 904 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 905 906 #include <asm/fsl_secure_boot.h> 907 908 #endif /* __T208xQDS_H */ 909