1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 46 #define CONFIG_SPL_SERIAL_SUPPORT 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_SPL_LIBGENERIC_SUPPORT 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 #define CONFIG_SYS_TEXT_BASE 0x00201000 52 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 53 #define CONFIG_SPL_PAD_TO 0x40000 54 #define CONFIG_SPL_MAX_SIZE 0x28000 55 #define RESET_VECTOR_OFFSET 0x27FFC 56 #define BOOT_PAGE_OFFSET 0x27000 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_SKIP_RELOCATE 59 #define CONFIG_SPL_COMMON_INIT_DDR 60 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 61 #define CONFIG_SYS_NO_FLASH 62 #endif 63 64 #ifdef CONFIG_NAND 65 #define CONFIG_SPL_NAND_SUPPORT 66 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 67 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 68 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 69 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 70 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 71 #define CONFIG_SPL_NAND_BOOT 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 76 #define CONFIG_SPL_SPI_SUPPORT 77 #define CONFIG_SPL_SPI_FLASH_SUPPORT 78 #define CONFIG_SPL_SPI_FLASH_MINIMAL 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 84 #ifndef CONFIG_SPL_BUILD 85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 86 #endif 87 #define CONFIG_SPL_SPI_BOOT 88 #endif 89 90 #ifdef CONFIG_SDCARD 91 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 92 #define CONFIG_SPL_MMC_SUPPORT 93 #define CONFIG_SPL_MMC_MINIMAL 94 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 95 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 96 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 97 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 98 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 99 #ifndef CONFIG_SPL_BUILD 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #endif 102 #define CONFIG_SPL_MMC_BOOT 103 #endif 104 105 #endif /* CONFIG_RAMBOOT_PBL */ 106 107 #define CONFIG_SRIO_PCIE_BOOT_MASTER 108 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 109 /* Set 1M boot space */ 110 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 111 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 112 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 113 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 114 #define CONFIG_SYS_NO_FLASH 115 #endif 116 117 #ifndef CONFIG_SYS_TEXT_BASE 118 #define CONFIG_SYS_TEXT_BASE 0xeff40000 119 #endif 120 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 123 #endif 124 125 /* 126 * These can be toggled for performance analysis, otherwise use default. 127 */ 128 #define CONFIG_SYS_CACHE_STASHING 129 #define CONFIG_BTB /* toggle branch predition */ 130 #define CONFIG_DDR_ECC 131 #ifdef CONFIG_DDR_ECC 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 134 #endif 135 136 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 137 #define CONFIG_SYS_MEMTEST_END 0x00400000 138 #define CONFIG_SYS_ALT_MEMTEST 139 140 #ifndef CONFIG_SYS_NO_FLASH 141 #define CONFIG_FLASH_CFI_DRIVER 142 #define CONFIG_SYS_FLASH_CFI 143 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 144 #endif 145 146 #if defined(CONFIG_SPIFLASH) 147 #define CONFIG_SYS_EXTRA_ENV_RELOC 148 #define CONFIG_ENV_IS_IN_SPI_FLASH 149 #define CONFIG_ENV_SPI_BUS 0 150 #define CONFIG_ENV_SPI_CS 0 151 #define CONFIG_ENV_SPI_MAX_HZ 10000000 152 #define CONFIG_ENV_SPI_MODE 0 153 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 154 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 155 #define CONFIG_ENV_SECT_SIZE 0x10000 156 #elif defined(CONFIG_SDCARD) 157 #define CONFIG_SYS_EXTRA_ENV_RELOC 158 #define CONFIG_ENV_IS_IN_MMC 159 #define CONFIG_SYS_MMC_ENV_DEV 0 160 #define CONFIG_ENV_SIZE 0x2000 161 #define CONFIG_ENV_OFFSET (512 * 0x800) 162 #elif defined(CONFIG_NAND) 163 #define CONFIG_SYS_EXTRA_ENV_RELOC 164 #define CONFIG_ENV_IS_IN_NAND 165 #define CONFIG_ENV_SIZE 0x2000 166 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 167 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 168 #define CONFIG_ENV_IS_IN_REMOTE 169 #define CONFIG_ENV_ADDR 0xffe20000 170 #define CONFIG_ENV_SIZE 0x2000 171 #elif defined(CONFIG_ENV_IS_NOWHERE) 172 #define CONFIG_ENV_SIZE 0x2000 173 #else 174 #define CONFIG_ENV_IS_IN_FLASH 175 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 176 #define CONFIG_ENV_SIZE 0x2000 177 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 178 #endif 179 180 #ifndef __ASSEMBLY__ 181 unsigned long get_board_sys_clk(void); 182 unsigned long get_board_ddr_clk(void); 183 #endif 184 185 #define CONFIG_SYS_CLK_FREQ 66660000 186 #define CONFIG_DDR_CLK_FREQ 133330000 187 188 /* 189 * Config the L3 Cache as L3 SRAM 190 */ 191 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 192 #define CONFIG_SYS_L3_SIZE (512 << 10) 193 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 194 #ifdef CONFIG_RAMBOOT_PBL 195 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 196 #endif 197 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 198 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 199 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 200 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 201 202 #define CONFIG_SYS_DCSRBAR 0xf0000000 203 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 204 205 /* EEPROM */ 206 #define CONFIG_ID_EEPROM 207 #define CONFIG_SYS_I2C_EEPROM_NXID 208 #define CONFIG_SYS_EEPROM_BUS_NUM 0 209 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 211 212 /* 213 * DDR Setup 214 */ 215 #define CONFIG_VERY_BIG_RAM 216 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 217 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 218 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 219 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 220 #define CONFIG_DDR_SPD 221 #define CONFIG_SYS_FSL_DDR3 222 #undef CONFIG_FSL_DDR_INTERACTIVE 223 #define CONFIG_SYS_SPD_BUS_NUM 0 224 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 225 #define SPD_EEPROM_ADDRESS1 0x51 226 #define SPD_EEPROM_ADDRESS2 0x52 227 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 228 #define CTRL_INTLV_PREFERED cacheline 229 230 /* 231 * IFC Definitions 232 */ 233 #define CONFIG_SYS_FLASH_BASE 0xe8000000 234 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 235 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 236 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 237 CSPR_PORT_SIZE_16 | \ 238 CSPR_MSEL_NOR | \ 239 CSPR_V) 240 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 241 242 /* NOR Flash Timing Params */ 243 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 244 245 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 246 FTIM0_NOR_TEADC(0x5) | \ 247 FTIM0_NOR_TEAHC(0x5)) 248 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 249 FTIM1_NOR_TRAD_NOR(0x1A) |\ 250 FTIM1_NOR_TSEQRAD_NOR(0x13)) 251 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 252 FTIM2_NOR_TCH(0x4) | \ 253 FTIM2_NOR_TWPH(0x0E) | \ 254 FTIM2_NOR_TWP(0x1c)) 255 #define CONFIG_SYS_NOR_FTIM3 0x0 256 257 #define CONFIG_SYS_FLASH_QUIET_TEST 258 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 259 260 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 261 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 262 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 263 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 264 #define CONFIG_SYS_FLASH_EMPTY_INFO 265 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 266 267 /* CPLD on IFC */ 268 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 269 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 270 #define CONFIG_SYS_CSPR2_EXT (0xf) 271 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 272 | CSPR_PORT_SIZE_8 \ 273 | CSPR_MSEL_GPCM \ 274 | CSPR_V) 275 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 276 #define CONFIG_SYS_CSOR2 0x0 277 278 /* CPLD Timing parameters for IFC CS2 */ 279 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 280 FTIM0_GPCM_TEADC(0x0e) | \ 281 FTIM0_GPCM_TEAHC(0x0e)) 282 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 283 FTIM1_GPCM_TRAD(0x1f)) 284 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 285 FTIM2_GPCM_TCH(0x8) | \ 286 FTIM2_GPCM_TWP(0x1f)) 287 #define CONFIG_SYS_CS2_FTIM3 0x0 288 289 /* NAND Flash on IFC */ 290 #define CONFIG_NAND_FSL_IFC 291 #define CONFIG_SYS_NAND_BASE 0xff800000 292 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 293 294 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 295 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 296 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 297 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 298 | CSPR_V) 299 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 300 301 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 302 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 303 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 304 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 305 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 306 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 307 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 308 309 #define CONFIG_SYS_NAND_ONFI_DETECTION 310 311 /* ONFI NAND Flash mode0 Timing Params */ 312 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 313 FTIM0_NAND_TWP(0x18) | \ 314 FTIM0_NAND_TWCHT(0x07) | \ 315 FTIM0_NAND_TWH(0x0a)) 316 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 317 FTIM1_NAND_TWBE(0x39) | \ 318 FTIM1_NAND_TRR(0x0e) | \ 319 FTIM1_NAND_TRP(0x18)) 320 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 321 FTIM2_NAND_TREH(0x0a) | \ 322 FTIM2_NAND_TWHRE(0x1e)) 323 #define CONFIG_SYS_NAND_FTIM3 0x0 324 325 #define CONFIG_SYS_NAND_DDR_LAW 11 326 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 327 #define CONFIG_SYS_MAX_NAND_DEVICE 1 328 #define CONFIG_CMD_NAND 329 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 330 331 #if defined(CONFIG_NAND) 332 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 333 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 334 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 335 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 336 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 337 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 338 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 339 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 340 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 341 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 342 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #else 349 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 357 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 358 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 359 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 360 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 361 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 362 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 363 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 364 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 365 #endif 366 367 #if defined(CONFIG_RAMBOOT_PBL) 368 #define CONFIG_SYS_RAMBOOT 369 #endif 370 371 #ifdef CONFIG_SPL_BUILD 372 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 373 #else 374 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 375 #endif 376 377 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 378 #define CONFIG_MISC_INIT_R 379 #define CONFIG_HWCONFIG 380 381 /* define to use L1 as initial stack */ 382 #define CONFIG_L1_INIT_RAM 383 #define CONFIG_SYS_INIT_RAM_LOCK 384 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 387 /* The assembler doesn't like typecast */ 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 389 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 390 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 391 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 392 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 393 GENERATED_GBL_DATA_SIZE) 394 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 395 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 396 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 397 398 /* 399 * Serial Port 400 */ 401 #define CONFIG_CONS_INDEX 1 402 #define CONFIG_SYS_NS16550_SERIAL 403 #define CONFIG_SYS_NS16550_REG_SIZE 1 404 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 405 #define CONFIG_SYS_BAUDRATE_TABLE \ 406 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 407 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 408 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 409 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 410 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 411 412 /* 413 * I2C 414 */ 415 #define CONFIG_SYS_I2C 416 #define CONFIG_SYS_I2C_FSL 417 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 419 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 420 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 421 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 422 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 423 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 424 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 425 #define CONFIG_SYS_FSL_I2C_SPEED 100000 426 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 427 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 428 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 429 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 430 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 431 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 432 #define I2C_MUX_CH_DEFAULT 0x8 433 434 #define I2C_MUX_CH_VOL_MONITOR 0xa 435 436 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 437 #ifndef CONFIG_SPL_BUILD 438 #define CONFIG_VID 439 #endif 440 #define CONFIG_VOL_MONITOR_IR36021_SET 441 #define CONFIG_VOL_MONITOR_IR36021_READ 442 /* The lowest and highest voltage allowed for T208xRDB */ 443 #define VDD_MV_MIN 819 444 #define VDD_MV_MAX 1212 445 446 /* 447 * RapidIO 448 */ 449 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 450 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 451 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 452 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 453 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 454 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 455 /* 456 * for slave u-boot IMAGE instored in master memory space, 457 * PHYS must be aligned based on the SIZE 458 */ 459 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 460 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 461 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 462 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 463 /* 464 * for slave UCODE and ENV instored in master memory space, 465 * PHYS must be aligned based on the SIZE 466 */ 467 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 468 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 469 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 470 471 /* slave core release by master*/ 472 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 473 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 474 475 /* 476 * SRIO_PCIE_BOOT - SLAVE 477 */ 478 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 479 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 480 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 481 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 482 #endif 483 484 /* 485 * eSPI - Enhanced SPI 486 */ 487 #ifdef CONFIG_SPI_FLASH 488 #define CONFIG_SPI_FLASH_BAR 489 #define CONFIG_SF_DEFAULT_SPEED 10000000 490 #define CONFIG_SF_DEFAULT_MODE 0 491 #endif 492 493 /* 494 * General PCI 495 * Memory space is mapped 1-1, but I/O space must start from 0. 496 */ 497 #define CONFIG_PCI /* Enable PCI/PCIE */ 498 #define CONFIG_PCIE1 /* PCIE controller 1 */ 499 #define CONFIG_PCIE2 /* PCIE controller 2 */ 500 #define CONFIG_PCIE3 /* PCIE controller 3 */ 501 #define CONFIG_PCIE4 /* PCIE controller 4 */ 502 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 503 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 504 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 505 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 506 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 507 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 508 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 509 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 510 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 511 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 512 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 513 514 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 515 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 516 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 517 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 518 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 519 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 520 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 521 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 522 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 523 524 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 525 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 526 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 527 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 528 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 529 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 530 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 531 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 532 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 533 534 /* controller 4, Base address 203000 */ 535 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 536 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 537 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 538 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 539 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 540 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 541 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 542 543 #ifdef CONFIG_PCI 544 #define CONFIG_PCI_INDIRECT_BRIDGE 545 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 546 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 547 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 548 #define CONFIG_DOS_PARTITION 549 #endif 550 551 /* Qman/Bman */ 552 #ifndef CONFIG_NOBQFMAN 553 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 554 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 555 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 556 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 557 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 558 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 559 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 560 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 561 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 562 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 563 CONFIG_SYS_BMAN_CENA_SIZE) 564 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 565 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 566 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 567 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 568 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 569 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 570 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 571 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 572 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 573 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 574 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 575 CONFIG_SYS_QMAN_CENA_SIZE) 576 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 577 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 578 579 #define CONFIG_SYS_DPAA_FMAN 580 #define CONFIG_SYS_DPAA_PME 581 #define CONFIG_SYS_PMAN 582 #define CONFIG_SYS_DPAA_DCE 583 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 584 #define CONFIG_SYS_INTERLAKEN 585 586 /* Default address of microcode for the Linux Fman driver */ 587 #if defined(CONFIG_SPIFLASH) 588 /* 589 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 590 * env, so we got 0x110000. 591 */ 592 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 593 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 594 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 595 #define CONFIG_CORTINA_FW_ADDR 0x120000 596 597 #elif defined(CONFIG_SDCARD) 598 /* 599 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 600 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 601 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 602 */ 603 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 604 #define CONFIG_SYS_CORTINA_FW_IN_MMC 605 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 606 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 607 608 #elif defined(CONFIG_NAND) 609 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 610 #define CONFIG_SYS_CORTINA_FW_IN_NAND 611 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 612 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 613 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 614 /* 615 * Slave has no ucode locally, it can fetch this from remote. When implementing 616 * in two corenet boards, slave's ucode could be stored in master's memory 617 * space, the address can be mapped from slave TLB->slave LAW-> 618 * slave SRIO or PCIE outbound window->master inbound window-> 619 * master LAW->the ucode address in master's memory space. 620 */ 621 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 622 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 623 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 624 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 625 #else 626 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 627 #define CONFIG_SYS_CORTINA_FW_IN_NOR 628 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 629 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 630 #endif 631 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 632 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 633 #endif /* CONFIG_NOBQFMAN */ 634 635 #ifdef CONFIG_SYS_DPAA_FMAN 636 #define CONFIG_FMAN_ENET 637 #define CONFIG_PHYLIB_10G 638 #define CONFIG_PHY_AQUANTIA 639 #define CONFIG_PHY_CORTINA 640 #define CONFIG_PHY_REALTEK 641 #define CONFIG_CORTINA_FW_LENGTH 0x40000 642 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 643 #define RGMII_PHY2_ADDR 0x02 644 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 645 #define CORTINA_PHY_ADDR2 0x0d 646 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 647 #define FM1_10GEC4_PHY_ADDR 0x01 648 #endif 649 650 #ifdef CONFIG_FMAN_ENET 651 #define CONFIG_MII /* MII PHY management */ 652 #define CONFIG_ETHPRIME "FM1@DTSEC3" 653 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 654 #endif 655 656 /* 657 * SATA 658 */ 659 #ifdef CONFIG_FSL_SATA_V2 660 #define CONFIG_LIBATA 661 #define CONFIG_FSL_SATA 662 #define CONFIG_SYS_SATA_MAX_DEVICE 2 663 #define CONFIG_SATA1 664 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 665 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 666 #define CONFIG_SATA2 667 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 668 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 669 #define CONFIG_LBA48 670 #define CONFIG_CMD_SATA 671 #define CONFIG_DOS_PARTITION 672 #endif 673 674 /* 675 * USB 676 */ 677 #ifdef CONFIG_USB_EHCI 678 #define CONFIG_USB_EHCI_FSL 679 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 680 #define CONFIG_HAS_FSL_DR_USB 681 #endif 682 683 /* 684 * SDHC 685 */ 686 #ifdef CONFIG_MMC 687 #define CONFIG_FSL_ESDHC 688 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 689 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 690 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 691 #define CONFIG_GENERIC_MMC 692 #define CONFIG_DOS_PARTITION 693 #endif 694 695 /* 696 * Dynamic MTD Partition support with mtdparts 697 */ 698 #ifndef CONFIG_SYS_NO_FLASH 699 #define CONFIG_MTD_DEVICE 700 #define CONFIG_MTD_PARTITIONS 701 #define CONFIG_CMD_MTDPARTS 702 #define CONFIG_FLASH_CFI_MTD 703 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 704 "spi0=spife110000.1" 705 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 706 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 707 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 708 "1m(uboot),5m(kernel),128k(dtb),-(user)" 709 #endif 710 711 /* 712 * Environment 713 */ 714 715 /* 716 * Command line configuration. 717 */ 718 #define CONFIG_CMD_ERRATA 719 #define CONFIG_CMD_REGINFO 720 721 #ifdef CONFIG_PCI 722 #define CONFIG_CMD_PCI 723 #endif 724 725 /* Hash command with SHA acceleration supported in hardware */ 726 #ifdef CONFIG_FSL_CAAM 727 #define CONFIG_CMD_HASH 728 #define CONFIG_SHA_HW_ACCEL 729 #endif 730 731 /* 732 * Miscellaneous configurable options 733 */ 734 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 735 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 736 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 737 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 738 #ifdef CONFIG_CMD_KGDB 739 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 740 #else 741 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 742 #endif 743 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 744 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 745 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 746 747 /* 748 * For booting Linux, the board info and command line data 749 * have to be in the first 64 MB of memory, since this is 750 * the maximum mapped by the Linux kernel during initialization. 751 */ 752 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 753 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 754 755 #ifdef CONFIG_CMD_KGDB 756 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 757 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 758 #endif 759 760 /* 761 * Environment Configuration 762 */ 763 #define CONFIG_ROOTPATH "/opt/nfsroot" 764 #define CONFIG_BOOTFILE "uImage" 765 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 766 767 /* default location for tftp and bootm */ 768 #define CONFIG_LOADADDR 1000000 769 #define CONFIG_BAUDRATE 115200 770 #define __USB_PHY_TYPE utmi 771 772 #define CONFIG_EXTRA_ENV_SETTINGS \ 773 "hwconfig=fsl_ddr:" \ 774 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 775 "bank_intlv=auto;" \ 776 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 777 "netdev=eth0\0" \ 778 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 779 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 780 "tftpflash=tftpboot $loadaddr $uboot && " \ 781 "protect off $ubootaddr +$filesize && " \ 782 "erase $ubootaddr +$filesize && " \ 783 "cp.b $loadaddr $ubootaddr $filesize && " \ 784 "protect on $ubootaddr +$filesize && " \ 785 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 786 "consoledev=ttyS0\0" \ 787 "ramdiskaddr=2000000\0" \ 788 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 789 "fdtaddr=1e00000\0" \ 790 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 791 "bdev=sda3\0" 792 793 /* 794 * For emulation this causes u-boot to jump to the start of the 795 * proof point app code automatically 796 */ 797 #define CONFIG_PROOF_POINTS \ 798 "setenv bootargs root=/dev/$bdev rw " \ 799 "console=$consoledev,$baudrate $othbootargs;" \ 800 "cpu 1 release 0x29000000 - - -;" \ 801 "cpu 2 release 0x29000000 - - -;" \ 802 "cpu 3 release 0x29000000 - - -;" \ 803 "cpu 4 release 0x29000000 - - -;" \ 804 "cpu 5 release 0x29000000 - - -;" \ 805 "cpu 6 release 0x29000000 - - -;" \ 806 "cpu 7 release 0x29000000 - - -;" \ 807 "go 0x29000000" 808 809 #define CONFIG_HVBOOT \ 810 "setenv bootargs config-addr=0x60000000; " \ 811 "bootm 0x01000000 - 0x00f00000" 812 813 #define CONFIG_ALU \ 814 "setenv bootargs root=/dev/$bdev rw " \ 815 "console=$consoledev,$baudrate $othbootargs;" \ 816 "cpu 1 release 0x01000000 - - -;" \ 817 "cpu 2 release 0x01000000 - - -;" \ 818 "cpu 3 release 0x01000000 - - -;" \ 819 "cpu 4 release 0x01000000 - - -;" \ 820 "cpu 5 release 0x01000000 - - -;" \ 821 "cpu 6 release 0x01000000 - - -;" \ 822 "cpu 7 release 0x01000000 - - -;" \ 823 "go 0x01000000" 824 825 #define CONFIG_LINUX \ 826 "setenv bootargs root=/dev/ram rw " \ 827 "console=$consoledev,$baudrate $othbootargs;" \ 828 "setenv ramdiskaddr 0x02000000;" \ 829 "setenv fdtaddr 0x00c00000;" \ 830 "setenv loadaddr 0x1000000;" \ 831 "bootm $loadaddr $ramdiskaddr $fdtaddr" 832 833 #define CONFIG_HDBOOT \ 834 "setenv bootargs root=/dev/$bdev rw " \ 835 "console=$consoledev,$baudrate $othbootargs;" \ 836 "tftp $loadaddr $bootfile;" \ 837 "tftp $fdtaddr $fdtfile;" \ 838 "bootm $loadaddr - $fdtaddr" 839 840 #define CONFIG_NFSBOOTCOMMAND \ 841 "setenv bootargs root=/dev/nfs rw " \ 842 "nfsroot=$serverip:$rootpath " \ 843 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "tftp $loadaddr $bootfile;" \ 846 "tftp $fdtaddr $fdtfile;" \ 847 "bootm $loadaddr - $fdtaddr" 848 849 #define CONFIG_RAMBOOTCOMMAND \ 850 "setenv bootargs root=/dev/ram rw " \ 851 "console=$consoledev,$baudrate $othbootargs;" \ 852 "tftp $ramdiskaddr $ramdiskfile;" \ 853 "tftp $loadaddr $bootfile;" \ 854 "tftp $fdtaddr $fdtfile;" \ 855 "bootm $loadaddr $ramdiskaddr $fdtaddr" 856 857 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 858 859 #include <asm/fsl_secure_boot.h> 860 861 #endif /* __T2080RDB_H */ 862