1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_PCIE4 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 24 #ifndef CONFIG_SDCARD 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LIBGENERIC_SUPPORT 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_SYS_TEXT_BASE 0x00201000 35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 36 #define CONFIG_SPL_PAD_TO 0x40000 37 #define CONFIG_SPL_MAX_SIZE 0x28000 38 #define RESET_VECTOR_OFFSET 0x27FFC 39 #define BOOT_PAGE_OFFSET 0x27000 40 41 #ifdef CONFIG_SDCARD 42 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 43 #define CONFIG_SPL_MMC_SUPPORT 44 #define CONFIG_SPL_MMC_MINIMAL 45 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 46 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 47 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 48 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 49 #ifndef CONFIG_SPL_BUILD 50 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 51 #endif 52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 53 #define CONFIG_SPL_MMC_BOOT 54 #endif 55 56 #ifdef CONFIG_SPL_BUILD 57 #define CONFIG_SPL_SKIP_RELOCATE 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 60 #define CONFIG_SYS_NO_FLASH 61 #endif 62 63 #endif 64 #endif /* CONFIG_RAMBOOT_PBL */ 65 66 #define CONFIG_DDR_ECC 67 68 #define CONFIG_CMD_REGINFO 69 70 /* High Level Configuration Options */ 71 #define CONFIG_BOOKE 72 #define CONFIG_E500 /* BOOKE e500 family */ 73 #define CONFIG_E500MC /* BOOKE e500mc family */ 74 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 75 #define CONFIG_MP /* support multiple processors */ 76 77 #ifndef CONFIG_SYS_TEXT_BASE 78 #define CONFIG_SYS_TEXT_BASE 0xeff40000 79 #endif 80 81 #ifndef CONFIG_RESET_VECTOR_ADDRESS 82 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 83 #endif 84 85 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 86 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 87 #define CONFIG_FSL_IFC /* Enable IFC Support */ 88 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 89 #define CONFIG_PCI /* Enable PCI/PCIE */ 90 #define CONFIG_PCIE1 /* PCIE controller 1 */ 91 #define CONFIG_PCIE2 /* PCIE controller 2 */ 92 #define CONFIG_PCIE3 /* PCIE controller 3 */ 93 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 94 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 95 96 #define CONFIG_FSL_LAW /* Use common FSL init code */ 97 98 #define CONFIG_ENV_OVERWRITE 99 100 /* 101 * These can be toggled for performance analysis, otherwise use default. 102 */ 103 #define CONFIG_SYS_CACHE_STASHING 104 #define CONFIG_BTB /* toggle branch predition */ 105 #ifdef CONFIG_DDR_ECC 106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 107 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 108 #endif 109 110 #define CONFIG_ENABLE_36BIT_PHYS 111 112 #define CONFIG_ADDR_MAP 113 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 114 115 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 116 #define CONFIG_SYS_MEMTEST_END 0x00400000 117 #define CONFIG_SYS_ALT_MEMTEST 118 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 119 120 /* 121 * Config the L3 Cache as L3 SRAM 122 */ 123 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 124 #define CONFIG_SYS_L3_SIZE (512 << 10) 125 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 126 #ifdef CONFIG_RAMBOOT_PBL 127 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 128 #endif 129 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 130 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 131 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 132 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 133 134 #define CONFIG_SYS_DCSRBAR 0xf0000000 135 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 136 137 /* 138 * DDR Setup 139 */ 140 #define CONFIG_VERY_BIG_RAM 141 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 142 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 143 144 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 145 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 146 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 147 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 148 149 #define CONFIG_DDR_SPD 150 #define CONFIG_SYS_FSL_DDR3 151 152 /* 153 * IFC Definitions 154 */ 155 #define CONFIG_SYS_FLASH_BASE 0xe0000000 156 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 157 158 #ifdef CONFIG_SPL_BUILD 159 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 160 #else 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 162 #endif 163 164 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 165 #define CONFIG_MISC_INIT_R 166 167 #define CONFIG_HWCONFIG 168 169 /* define to use L1 as initial stack */ 170 #define CONFIG_L1_INIT_RAM 171 #define CONFIG_SYS_INIT_RAM_LOCK 172 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 175 /* The assembler doesn't like typecast */ 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 177 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 178 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 179 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 180 181 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 182 GENERATED_GBL_DATA_SIZE) 183 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 184 185 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 186 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 187 188 /* Serial Port - controlled on board with jumper J8 189 * open - index 2 190 * shorted - index 1 191 */ 192 #define CONFIG_CONS_INDEX 1 193 #define CONFIG_SYS_NS16550_SERIAL 194 #define CONFIG_SYS_NS16550_REG_SIZE 1 195 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 196 197 #define CONFIG_SYS_BAUDRATE_TABLE \ 198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 199 200 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 201 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 202 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 203 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 204 205 /* I2C */ 206 #define CONFIG_SYS_I2C 207 #define CONFIG_SYS_I2C_FSL 208 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 209 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 210 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 211 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 212 213 /* 214 * General PCI 215 * Memory space is mapped 1-1, but I/O space must start from 0. 216 */ 217 218 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 219 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 220 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 221 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 222 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 223 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 224 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 225 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 226 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 227 228 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 229 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 230 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 231 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 232 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 233 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 234 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 235 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 236 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 237 238 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 239 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 240 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 241 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 242 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 243 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 244 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 245 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 246 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 247 248 /* controller 4, Base address 203000 */ 249 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 250 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 251 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 252 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 253 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 254 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 255 256 #ifdef CONFIG_PCI 257 #define CONFIG_PCI_INDIRECT_BRIDGE 258 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 259 260 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 261 #define CONFIG_DOS_PARTITION 262 #endif /* CONFIG_PCI */ 263 264 /* SATA */ 265 #ifdef CONFIG_FSL_SATA_V2 266 #define CONFIG_LIBATA 267 #define CONFIG_FSL_SATA 268 269 #define CONFIG_SYS_SATA_MAX_DEVICE 2 270 #define CONFIG_SATA1 271 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 272 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 273 #define CONFIG_SATA2 274 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 275 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 276 277 #define CONFIG_LBA48 278 #define CONFIG_CMD_SATA 279 #define CONFIG_DOS_PARTITION 280 #endif 281 282 #ifdef CONFIG_FMAN_ENET 283 #define CONFIG_MII /* MII PHY management */ 284 #define CONFIG_ETHPRIME "FM1@DTSEC1" 285 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 286 #endif 287 288 /* 289 * Environment 290 */ 291 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 292 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 293 294 /* 295 * Command line configuration. 296 */ 297 #define CONFIG_CMD_ERRATA 298 #define CONFIG_CMD_IRQ 299 300 #ifdef CONFIG_PCI 301 #define CONFIG_CMD_PCI 302 #endif 303 304 /* 305 * Miscellaneous configurable options 306 */ 307 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 308 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 309 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 310 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 311 #ifdef CONFIG_CMD_KGDB 312 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 313 #else 314 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 315 #endif 316 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 317 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 318 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 319 320 /* 321 * For booting Linux, the board info and command line data 322 * have to be in the first 64 MB of memory, since this is 323 * the maximum mapped by the Linux kernel during initialization. 324 */ 325 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 326 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 327 328 #ifdef CONFIG_CMD_KGDB 329 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 330 #endif 331 332 /* 333 * Environment Configuration 334 */ 335 #define CONFIG_ROOTPATH "/opt/nfsroot" 336 #define CONFIG_BOOTFILE "uImage" 337 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 338 339 /* default location for tftp and bootm */ 340 #define CONFIG_LOADADDR 1000000 341 342 #define CONFIG_BAUDRATE 115200 343 344 #define CONFIG_HVBOOT \ 345 "setenv bootargs config-addr=0x60000000; " \ 346 "bootm 0x01000000 - 0x00f00000" 347 348 #ifdef CONFIG_SYS_NO_FLASH 349 #ifndef CONFIG_RAMBOOT_PBL 350 #define CONFIG_ENV_IS_NOWHERE 351 #endif 352 #else 353 #define CONFIG_FLASH_CFI_DRIVER 354 #define CONFIG_SYS_FLASH_CFI 355 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 356 #endif 357 358 #if defined(CONFIG_SPIFLASH) 359 #define CONFIG_SYS_EXTRA_ENV_RELOC 360 #define CONFIG_ENV_IS_IN_SPI_FLASH 361 #define CONFIG_ENV_SPI_BUS 0 362 #define CONFIG_ENV_SPI_CS 0 363 #define CONFIG_ENV_SPI_MAX_HZ 10000000 364 #define CONFIG_ENV_SPI_MODE 0 365 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 366 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 367 #define CONFIG_ENV_SECT_SIZE 0x10000 368 #elif defined(CONFIG_SDCARD) 369 #define CONFIG_SYS_EXTRA_ENV_RELOC 370 #define CONFIG_ENV_IS_IN_MMC 371 #define CONFIG_SYS_MMC_ENV_DEV 0 372 #define CONFIG_ENV_SIZE 0x2000 373 #define CONFIG_ENV_OFFSET (512 * 0x800) 374 #elif defined(CONFIG_NAND) 375 #define CONFIG_SYS_EXTRA_ENV_RELOC 376 #define CONFIG_ENV_IS_IN_NAND 377 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 378 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 379 #elif defined(CONFIG_ENV_IS_NOWHERE) 380 #define CONFIG_ENV_SIZE 0x2000 381 #else 382 #define CONFIG_ENV_IS_IN_FLASH 383 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 384 #define CONFIG_ENV_SIZE 0x2000 385 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 386 #endif 387 388 #define CONFIG_SYS_CLK_FREQ 66666666 389 #define CONFIG_DDR_CLK_FREQ 133333333 390 391 #ifndef __ASSEMBLY__ 392 unsigned long get_board_sys_clk(void); 393 unsigned long get_board_ddr_clk(void); 394 #endif 395 396 /* 397 * DDR Setup 398 */ 399 #define CONFIG_SYS_SPD_BUS_NUM 0 400 #define SPD_EEPROM_ADDRESS1 0x52 401 #define SPD_EEPROM_ADDRESS2 0x54 402 #define SPD_EEPROM_ADDRESS3 0x56 403 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 404 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 405 406 /* 407 * IFC Definitions 408 */ 409 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 410 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 411 + 0x8000000) | \ 412 CSPR_PORT_SIZE_16 | \ 413 CSPR_MSEL_NOR | \ 414 CSPR_V) 415 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 416 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 417 CSPR_PORT_SIZE_16 | \ 418 CSPR_MSEL_NOR | \ 419 CSPR_V) 420 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 421 /* NOR Flash Timing Params */ 422 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 423 424 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 425 FTIM0_NOR_TEADC(0x5) | \ 426 FTIM0_NOR_TEAHC(0x5)) 427 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 428 FTIM1_NOR_TRAD_NOR(0x1A) |\ 429 FTIM1_NOR_TSEQRAD_NOR(0x13)) 430 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 431 FTIM2_NOR_TCH(0x4) | \ 432 FTIM2_NOR_TWPH(0x0E) | \ 433 FTIM2_NOR_TWP(0x1c)) 434 #define CONFIG_SYS_NOR_FTIM3 0x0 435 436 #define CONFIG_SYS_FLASH_QUIET_TEST 437 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 438 439 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 440 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 441 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 442 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 443 444 #define CONFIG_SYS_FLASH_EMPTY_INFO 445 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 446 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 447 448 /* NAND Flash on IFC */ 449 #define CONFIG_NAND_FSL_IFC 450 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 451 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 452 #define CONFIG_SYS_NAND_BASE 0xff800000 453 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 454 455 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 456 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 457 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 458 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 459 | CSPR_V) 460 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 461 462 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 463 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 464 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 465 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 466 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 467 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 468 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 469 470 #define CONFIG_SYS_NAND_ONFI_DETECTION 471 472 /* ONFI NAND Flash mode0 Timing Params */ 473 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 474 FTIM0_NAND_TWP(0x18) | \ 475 FTIM0_NAND_TWCHT(0x07) | \ 476 FTIM0_NAND_TWH(0x0a)) 477 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 478 FTIM1_NAND_TWBE(0x39) | \ 479 FTIM1_NAND_TRR(0x0e) | \ 480 FTIM1_NAND_TRP(0x18)) 481 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 482 FTIM2_NAND_TREH(0x0a) | \ 483 FTIM2_NAND_TWHRE(0x1e)) 484 #define CONFIG_SYS_NAND_FTIM3 0x0 485 486 #define CONFIG_SYS_NAND_DDR_LAW 11 487 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 488 #define CONFIG_SYS_MAX_NAND_DEVICE 1 489 #define CONFIG_CMD_NAND 490 491 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 492 493 #if defined(CONFIG_NAND) 494 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 495 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 496 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 497 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 498 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 499 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 500 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 501 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 502 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 503 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 504 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 505 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 506 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 507 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 508 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 509 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 510 #else 511 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 512 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 513 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 514 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 515 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 516 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 517 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 518 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 519 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 520 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 521 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 522 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 523 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 524 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 525 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 526 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 527 #endif 528 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 529 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 530 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 531 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 532 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 533 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 534 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 535 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 536 537 /* CPLD on IFC */ 538 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 539 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 540 #define CONFIG_SYS_CSPR3_EXT (0xf) 541 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 542 | CSPR_PORT_SIZE_8 \ 543 | CSPR_MSEL_GPCM \ 544 | CSPR_V) 545 546 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 547 #define CONFIG_SYS_CSOR3 0x0 548 549 /* CPLD Timing parameters for IFC CS3 */ 550 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 551 FTIM0_GPCM_TEADC(0x0e) | \ 552 FTIM0_GPCM_TEAHC(0x0e)) 553 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 554 FTIM1_GPCM_TRAD(0x1f)) 555 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 556 FTIM2_GPCM_TCH(0x8) | \ 557 FTIM2_GPCM_TWP(0x1f)) 558 #define CONFIG_SYS_CS3_FTIM3 0x0 559 560 #if defined(CONFIG_RAMBOOT_PBL) 561 #define CONFIG_SYS_RAMBOOT 562 #endif 563 564 /* I2C */ 565 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 566 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 567 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 568 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 569 570 #define I2C_MUX_CH_DEFAULT 0x8 571 #define I2C_MUX_CH_VOL_MONITOR 0xa 572 #define I2C_MUX_CH_VSC3316_FS 0xc 573 #define I2C_MUX_CH_VSC3316_BS 0xd 574 575 /* Voltage monitor on channel 2*/ 576 #define I2C_VOL_MONITOR_ADDR 0x40 577 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 578 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 579 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 580 581 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 582 #ifndef CONFIG_SPL_BUILD 583 #define CONFIG_VID 584 #endif 585 #define CONFIG_VOL_MONITOR_IR36021_SET 586 #define CONFIG_VOL_MONITOR_IR36021_READ 587 /* The lowest and highest voltage allowed for T4240RDB */ 588 #define VDD_MV_MIN 819 589 #define VDD_MV_MAX 1212 590 591 /* 592 * eSPI - Enhanced SPI 593 */ 594 #define CONFIG_SF_DEFAULT_SPEED 10000000 595 #define CONFIG_SF_DEFAULT_MODE 0 596 597 /* Qman/Bman */ 598 #ifndef CONFIG_NOBQFMAN 599 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 600 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 601 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 602 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 603 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 604 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 605 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 606 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 607 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 608 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 609 CONFIG_SYS_BMAN_CENA_SIZE) 610 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 611 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 612 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 613 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 614 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 615 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 616 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 617 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 618 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 619 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 620 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 621 CONFIG_SYS_QMAN_CENA_SIZE) 622 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 623 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 624 625 #define CONFIG_SYS_DPAA_FMAN 626 #define CONFIG_SYS_DPAA_PME 627 #define CONFIG_SYS_PMAN 628 #define CONFIG_SYS_DPAA_DCE 629 #define CONFIG_SYS_DPAA_RMAN 630 #define CONFIG_SYS_INTERLAKEN 631 632 /* Default address of microcode for the Linux Fman driver */ 633 #if defined(CONFIG_SPIFLASH) 634 /* 635 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 636 * env, so we got 0x110000. 637 */ 638 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 639 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 640 #elif defined(CONFIG_SDCARD) 641 /* 642 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 643 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 644 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 645 */ 646 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 647 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 648 #elif defined(CONFIG_NAND) 649 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 650 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 651 #else 652 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 653 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 654 #endif 655 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 656 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 657 #endif /* CONFIG_NOBQFMAN */ 658 659 #ifdef CONFIG_SYS_DPAA_FMAN 660 #define CONFIG_FMAN_ENET 661 #define CONFIG_PHYLIB_10G 662 #define CONFIG_PHY_VITESSE 663 #define CONFIG_PHY_CORTINA 664 #define CONFIG_SYS_CORTINA_FW_IN_NOR 665 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 666 #define CONFIG_CORTINA_FW_LENGTH 0x40000 667 #define CONFIG_PHY_TERANETICS 668 #define SGMII_PHY_ADDR1 0x0 669 #define SGMII_PHY_ADDR2 0x1 670 #define SGMII_PHY_ADDR3 0x2 671 #define SGMII_PHY_ADDR4 0x3 672 #define SGMII_PHY_ADDR5 0x4 673 #define SGMII_PHY_ADDR6 0x5 674 #define SGMII_PHY_ADDR7 0x6 675 #define SGMII_PHY_ADDR8 0x7 676 #define FM1_10GEC1_PHY_ADDR 0x10 677 #define FM1_10GEC2_PHY_ADDR 0x11 678 #define FM2_10GEC1_PHY_ADDR 0x12 679 #define FM2_10GEC2_PHY_ADDR 0x13 680 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 681 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 682 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 683 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 684 #endif 685 686 /* SATA */ 687 #ifdef CONFIG_FSL_SATA_V2 688 #define CONFIG_LIBATA 689 #define CONFIG_FSL_SATA 690 691 #define CONFIG_SYS_SATA_MAX_DEVICE 2 692 #define CONFIG_SATA1 693 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 694 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 695 #define CONFIG_SATA2 696 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 697 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 698 699 #define CONFIG_LBA48 700 #define CONFIG_CMD_SATA 701 #define CONFIG_DOS_PARTITION 702 #endif 703 704 #ifdef CONFIG_FMAN_ENET 705 #define CONFIG_MII /* MII PHY management */ 706 #define CONFIG_ETHPRIME "FM1@DTSEC1" 707 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 708 #endif 709 710 /* 711 * USB 712 */ 713 #define CONFIG_USB_EHCI 714 #define CONFIG_USB_EHCI_FSL 715 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 716 #define CONFIG_HAS_FSL_DR_USB 717 718 #define CONFIG_MMC 719 720 #ifdef CONFIG_MMC 721 #define CONFIG_FSL_ESDHC 722 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 723 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 724 #define CONFIG_GENERIC_MMC 725 #define CONFIG_DOS_PARTITION 726 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 727 #endif 728 729 /* Hash command with SHA acceleration supported in hardware */ 730 #ifdef CONFIG_FSL_CAAM 731 #define CONFIG_CMD_HASH 732 #define CONFIG_SHA_HW_ACCEL 733 #endif 734 735 736 #define __USB_PHY_TYPE utmi 737 738 /* 739 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 740 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 741 * interleaving. It can be cacheline, page, bank, superbank. 742 * See doc/README.fsl-ddr for details. 743 */ 744 #ifdef CONFIG_PPC_T4240 745 #define CTRL_INTLV_PREFERED 3way_4KB 746 #else 747 #define CTRL_INTLV_PREFERED cacheline 748 #endif 749 750 #define CONFIG_EXTRA_ENV_SETTINGS \ 751 "hwconfig=fsl_ddr:" \ 752 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 753 "bank_intlv=auto;" \ 754 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 755 "netdev=eth0\0" \ 756 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 757 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 758 "tftpflash=tftpboot $loadaddr $uboot && " \ 759 "protect off $ubootaddr +$filesize && " \ 760 "erase $ubootaddr +$filesize && " \ 761 "cp.b $loadaddr $ubootaddr $filesize && " \ 762 "protect on $ubootaddr +$filesize && " \ 763 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 764 "consoledev=ttyS0\0" \ 765 "ramdiskaddr=2000000\0" \ 766 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 767 "fdtaddr=1e00000\0" \ 768 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 769 "bdev=sda3\0" 770 771 #define CONFIG_HVBOOT \ 772 "setenv bootargs config-addr=0x60000000; " \ 773 "bootm 0x01000000 - 0x00f00000" 774 775 #define CONFIG_LINUX \ 776 "setenv bootargs root=/dev/ram rw " \ 777 "console=$consoledev,$baudrate $othbootargs;" \ 778 "setenv ramdiskaddr 0x02000000;" \ 779 "setenv fdtaddr 0x00c00000;" \ 780 "setenv loadaddr 0x1000000;" \ 781 "bootm $loadaddr $ramdiskaddr $fdtaddr" 782 783 #define CONFIG_HDBOOT \ 784 "setenv bootargs root=/dev/$bdev rw " \ 785 "console=$consoledev,$baudrate $othbootargs;" \ 786 "tftp $loadaddr $bootfile;" \ 787 "tftp $fdtaddr $fdtfile;" \ 788 "bootm $loadaddr - $fdtaddr" 789 790 #define CONFIG_NFSBOOTCOMMAND \ 791 "setenv bootargs root=/dev/nfs rw " \ 792 "nfsroot=$serverip:$rootpath " \ 793 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 794 "console=$consoledev,$baudrate $othbootargs;" \ 795 "tftp $loadaddr $bootfile;" \ 796 "tftp $fdtaddr $fdtfile;" \ 797 "bootm $loadaddr - $fdtaddr" 798 799 #define CONFIG_RAMBOOTCOMMAND \ 800 "setenv bootargs root=/dev/ram rw " \ 801 "console=$consoledev,$baudrate $othbootargs;" \ 802 "tftp $ramdiskaddr $ramdiskfile;" \ 803 "tftp $loadaddr $bootfile;" \ 804 "tftp $fdtaddr $fdtfile;" \ 805 "bootm $loadaddr $ramdiskaddr $fdtaddr" 806 807 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 808 809 #include <asm/fsl_secure_boot.h> 810 811 #endif /* __CONFIG_H */ 812