1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_BSC9132QDS 17 #define CONFIG_BSC9132 18 #endif 19 20 #define CONFIG_MISC_INIT_R 21 22 #ifdef CONFIG_SDCARD 23 #define CONFIG_RAMBOOT_SDCARD 24 #define CONFIG_SYS_RAMBOOT 25 #define CONFIG_SYS_EXTRA_ENV_RELOC 26 #define CONFIG_SYS_TEXT_BASE 0x11000000 27 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 28 #endif 29 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 30 #ifdef CONFIG_SPIFLASH 31 #define CONFIG_RAMBOOT_SPIFLASH 32 #define CONFIG_SYS_RAMBOOT 33 #define CONFIG_SYS_EXTRA_ENV_RELOC 34 #define CONFIG_SYS_TEXT_BASE 0x11000000 35 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 36 #endif 37 #ifdef CONFIG_NAND_SECBOOT 38 #define CONFIG_RAMBOOT_NAND 39 #define CONFIG_SYS_RAMBOOT 40 #define CONFIG_SYS_EXTRA_ENV_RELOC 41 #define CONFIG_SYS_TEXT_BASE 0x11000000 42 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 43 #endif 44 45 #ifdef CONFIG_NAND 46 #define CONFIG_SPL_INIT_MINIMAL 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_NAND_BOOT 49 #define CONFIG_SPL_FLUSH_IMAGE 50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 51 52 #define CONFIG_SYS_TEXT_BASE 0x00201000 53 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 54 #define CONFIG_SPL_MAX_SIZE 8192 55 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 56 #define CONFIG_SPL_RELOC_STACK 0x00100000 57 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 58 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 59 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 60 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 62 #endif 63 64 #ifndef CONFIG_SYS_TEXT_BASE 65 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 66 #endif 67 68 #ifndef CONFIG_RESET_VECTOR_ADDRESS 69 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 70 #endif 71 72 #ifdef CONFIG_SPL_BUILD 73 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 74 #else 75 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 76 #endif 77 78 /* High Level Configuration Options */ 79 #define CONFIG_BOOKE /* BOOKE */ 80 #define CONFIG_E500 /* BOOKE e500 family */ 81 #define CONFIG_FSL_IFC /* Enable IFC Support */ 82 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 83 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 84 85 #define CONFIG_PCI /* Enable PCI/PCIE */ 86 #if defined(CONFIG_PCI) 87 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 89 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 90 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 92 93 #define CONFIG_CMD_PCI 94 95 /* 96 * PCI Windows 97 * Memory space is mapped 1-1, but I/O space must start from 0. 98 */ 99 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 100 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 101 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 102 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 103 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 104 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 105 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 106 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 107 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 108 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 109 110 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 111 112 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 113 #define CONFIG_DOS_PARTITION 114 #endif 115 116 #define CONFIG_FSL_LAW /* Use common FSL init code */ 117 #define CONFIG_ENV_OVERWRITE 118 #define CONFIG_TSEC_ENET /* ethernet */ 119 120 #if defined(CONFIG_SYS_CLK_100_DDR_100) 121 #define CONFIG_SYS_CLK_FREQ 100000000 122 #define CONFIG_DDR_CLK_FREQ 100000000 123 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 124 #define CONFIG_SYS_CLK_FREQ 100000000 125 #define CONFIG_DDR_CLK_FREQ 133000000 126 #endif 127 128 #define CONFIG_MP 129 130 #define CONFIG_HWCONFIG 131 /* 132 * These can be toggled for performance analysis, otherwise use default. 133 */ 134 #define CONFIG_L2_CACHE /* toggle L2 cache */ 135 #define CONFIG_BTB /* enable branch predition */ 136 137 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 138 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 139 140 /* DDR Setup */ 141 #define CONFIG_SYS_FSL_DDR3 142 #define CONFIG_SYS_SPD_BUS_NUM 0 143 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 144 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 145 #define CONFIG_FSL_DDR_INTERACTIVE 146 147 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 148 149 #define CONFIG_SYS_SDRAM_SIZE (1024) 150 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 151 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 152 153 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 154 155 /* DDR3 Controller Settings */ 156 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 157 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 158 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 159 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 160 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 161 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 162 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 163 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 164 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 165 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 166 167 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 168 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 169 #define CONFIG_SYS_DDR_RCW_1 0x00000000 170 #define CONFIG_SYS_DDR_RCW_2 0x00000000 171 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 172 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 173 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 174 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 175 176 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 177 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 178 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 179 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 180 181 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 182 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 183 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 184 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 185 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 186 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 187 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 188 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 189 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 190 191 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 192 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 193 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 194 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 195 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 196 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 197 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 198 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 199 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 200 201 /*FIXME: the following params are constant w.r.t diff freq 202 combinations. this should be removed later 203 */ 204 #if CONFIG_DDR_CLK_FREQ == 100000000 205 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 206 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 207 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 208 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 209 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 210 #elif CONFIG_DDR_CLK_FREQ == 133000000 211 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 212 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 213 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 214 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 215 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 216 #else 217 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 218 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 219 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 220 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 221 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 222 #endif 223 224 /* relocated CCSRBAR */ 225 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 226 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 227 228 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 229 230 /* DSP CCSRBAR */ 231 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 232 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 233 234 /* 235 * IFC Definitions 236 */ 237 /* NOR Flash on IFC */ 238 239 #ifdef CONFIG_SPL_BUILD 240 #define CONFIG_SYS_NO_FLASH 241 #endif 242 #define CONFIG_SYS_FLASH_BASE 0x88000000 243 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 244 245 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 246 247 #define CONFIG_SYS_NOR_CSPR 0x88000101 248 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 249 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 250 /* NOR Flash Timing Params */ 251 252 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 253 | FTIM0_NOR_TEADC(0x03) \ 254 | FTIM0_NOR_TAVDS(0x00) \ 255 | FTIM0_NOR_TEAHC(0x0f)) 256 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 257 | FTIM1_NOR_TRAD_NOR(0x09) \ 258 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 259 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 260 | FTIM2_NOR_TCH(0x4) \ 261 | FTIM2_NOR_TWPH(0x7) \ 262 | FTIM2_NOR_TWP(0x1e)) 263 #define CONFIG_SYS_NOR_FTIM3 0x0 264 265 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 266 #define CONFIG_SYS_FLASH_QUIET_TEST 267 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 268 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 269 270 #undef CONFIG_SYS_FLASH_CHECKSUM 271 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 272 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 273 274 /* CFI for NOR Flash */ 275 #define CONFIG_FLASH_CFI_DRIVER 276 #define CONFIG_SYS_FLASH_CFI 277 #define CONFIG_SYS_FLASH_EMPTY_INFO 278 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 279 280 /* NAND Flash on IFC */ 281 #define CONFIG_SYS_NAND_BASE 0xff800000 282 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 283 284 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 285 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 286 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 287 | CSPR_V) 288 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 289 290 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 291 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 292 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 293 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 294 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 295 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 296 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 297 298 /* NAND Flash Timing Params */ 299 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 300 | FTIM0_NAND_TWP(0x05) \ 301 | FTIM0_NAND_TWCHT(0x02) \ 302 | FTIM0_NAND_TWH(0x04)) 303 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 304 | FTIM1_NAND_TWBE(0x1e) \ 305 | FTIM1_NAND_TRR(0x07) \ 306 | FTIM1_NAND_TRP(0x05)) 307 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 308 | FTIM2_NAND_TREH(0x04) \ 309 | FTIM2_NAND_TWHRE(0x11)) 310 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 311 312 #define CONFIG_SYS_NAND_DDR_LAW 11 313 314 /* NAND */ 315 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 316 #define CONFIG_SYS_MAX_NAND_DEVICE 1 317 #define CONFIG_CMD_NAND 318 319 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 320 321 #ifndef CONFIG_SPL_BUILD 322 #define CONFIG_FSL_QIXIS 323 #endif 324 #ifdef CONFIG_FSL_QIXIS 325 #define CONFIG_SYS_FPGA_BASE 0xffb00000 326 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 327 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 328 #define QIXIS_LBMAP_SWITCH 9 329 #define QIXIS_LBMAP_MASK 0x07 330 #define QIXIS_LBMAP_SHIFT 0 331 #define QIXIS_LBMAP_DFLTBANK 0x00 332 #define QIXIS_LBMAP_ALTBANK 0x04 333 #define QIXIS_RST_CTL_RESET 0x83 334 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 335 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 336 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 337 338 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 339 340 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 341 | CSPR_PORT_SIZE_8 \ 342 | CSPR_MSEL_GPCM \ 343 | CSPR_V) 344 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 345 #define CONFIG_SYS_CSOR2 0x0 346 /* CPLD Timing parameters for IFC CS3 */ 347 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 348 FTIM0_GPCM_TEADC(0x0e) | \ 349 FTIM0_GPCM_TEAHC(0x0e)) 350 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 351 FTIM1_GPCM_TRAD(0x1f)) 352 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 353 FTIM2_GPCM_TCH(0x8) | \ 354 FTIM2_GPCM_TWP(0x1f)) 355 #define CONFIG_SYS_CS2_FTIM3 0x0 356 #endif 357 358 /* Set up IFC registers for boot location NOR/NAND */ 359 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 360 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 361 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 362 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 363 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 364 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 365 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 366 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 367 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 368 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 369 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 370 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 371 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 372 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 373 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 374 #else 375 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 376 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 377 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 378 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 379 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 380 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 381 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 382 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 383 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 384 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 385 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 386 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 387 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 388 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 389 #endif 390 391 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 392 #define CONFIG_BOARD_EARLY_INIT_R 393 394 #define CONFIG_SYS_INIT_RAM_LOCK 395 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 396 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 397 398 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 399 - GENERATED_GBL_DATA_SIZE) 400 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 401 402 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 403 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 404 405 /* Serial Port */ 406 #define CONFIG_CONS_INDEX 1 407 #undef CONFIG_SERIAL_SOFTWARE_FIFO 408 #define CONFIG_SYS_NS16550_SERIAL 409 #define CONFIG_SYS_NS16550_REG_SIZE 1 410 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 411 #ifdef CONFIG_SPL_BUILD 412 #define CONFIG_NS16550_MIN_FUNCTIONS 413 #endif 414 415 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 416 417 #define CONFIG_SYS_BAUDRATE_TABLE \ 418 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 419 420 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 421 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 422 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 423 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 424 425 #define CONFIG_SYS_I2C 426 #define CONFIG_SYS_I2C_FSL 427 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 428 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 429 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 430 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 431 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 432 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 433 434 /* I2C EEPROM */ 435 #define CONFIG_ID_EEPROM 436 #ifdef CONFIG_ID_EEPROM 437 #define CONFIG_SYS_I2C_EEPROM_NXID 438 #endif 439 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 440 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 441 #define CONFIG_SYS_EEPROM_BUS_NUM 0 442 443 /* enable read and write access to EEPROM */ 444 #define CONFIG_CMD_EEPROM 445 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 446 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 447 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 448 449 /* I2C FPGA */ 450 #define CONFIG_I2C_FPGA 451 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 452 453 #define CONFIG_RTC_DS3231 454 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 455 456 /* 457 * SPI interface will not be available in case of NAND boot SPI CS0 will be 458 * used for SLIC 459 */ 460 /* eSPI - Enhanced SPI */ 461 #ifdef CONFIG_FSL_ESPI 462 #define CONFIG_SF_DEFAULT_SPEED 10000000 463 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 464 #endif 465 466 #if defined(CONFIG_TSEC_ENET) 467 468 #define CONFIG_MII /* MII PHY management */ 469 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 470 #define CONFIG_TSEC1 1 471 #define CONFIG_TSEC1_NAME "eTSEC1" 472 #define CONFIG_TSEC2 1 473 #define CONFIG_TSEC2_NAME "eTSEC2" 474 475 #define TSEC1_PHY_ADDR 0 476 #define TSEC2_PHY_ADDR 1 477 478 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 479 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 480 481 #define TSEC1_PHYIDX 0 482 #define TSEC2_PHYIDX 0 483 484 #define CONFIG_ETHPRIME "eTSEC1" 485 486 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 487 488 /* TBI PHY configuration for SGMII mode */ 489 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 490 TBICR_PHY_RESET \ 491 | TBICR_ANEG_ENABLE \ 492 | TBICR_FULL_DUPLEX \ 493 | TBICR_SPEED1_SET \ 494 ) 495 496 #endif /* CONFIG_TSEC_ENET */ 497 498 #define CONFIG_MMC 499 #ifdef CONFIG_MMC 500 #define CONFIG_DOS_PARTITION 501 #define CONFIG_FSL_ESDHC 502 #define CONFIG_GENERIC_MMC 503 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 504 #endif 505 506 #define CONFIG_USB_EHCI /* USB */ 507 #ifdef CONFIG_USB_EHCI 508 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 509 #define CONFIG_USB_EHCI_FSL 510 #define CONFIG_HAS_FSL_DR_USB 511 #endif 512 513 /* 514 * Environment 515 */ 516 #if defined(CONFIG_RAMBOOT_SDCARD) 517 #define CONFIG_ENV_IS_IN_MMC 518 #define CONFIG_FSL_FIXED_MMC_LOCATION 519 #define CONFIG_SYS_MMC_ENV_DEV 0 520 #define CONFIG_ENV_SIZE 0x2000 521 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 522 #define CONFIG_ENV_IS_IN_SPI_FLASH 523 #define CONFIG_ENV_SPI_BUS 0 524 #define CONFIG_ENV_SPI_CS 0 525 #define CONFIG_ENV_SPI_MAX_HZ 10000000 526 #define CONFIG_ENV_SPI_MODE 0 527 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 528 #define CONFIG_ENV_SECT_SIZE 0x10000 529 #define CONFIG_ENV_SIZE 0x2000 530 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 531 #define CONFIG_ENV_IS_IN_NAND 532 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 533 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 534 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 535 #elif defined(CONFIG_SYS_RAMBOOT) 536 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 537 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 538 #define CONFIG_ENV_SIZE 0x2000 539 #else 540 #define CONFIG_ENV_IS_IN_FLASH 541 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 542 #define CONFIG_ENV_SIZE 0x2000 543 #define CONFIG_ENV_SECT_SIZE 0x20000 544 #endif 545 546 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 547 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 548 549 /* 550 * Command line configuration. 551 */ 552 #define CONFIG_CMD_DATE 553 #define CONFIG_CMD_ERRATA 554 #define CONFIG_CMD_IRQ 555 #define CONFIG_CMD_REGINFO 556 557 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 558 #define CONFIG_DOS_PARTITION 559 #endif 560 561 /* Hash command with SHA acceleration supported in hardware */ 562 #ifdef CONFIG_FSL_CAAM 563 #define CONFIG_CMD_HASH 564 #define CONFIG_SHA_HW_ACCEL 565 #endif 566 567 /* 568 * Miscellaneous configurable options 569 */ 570 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 571 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 572 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 573 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 574 575 #if defined(CONFIG_CMD_KGDB) 576 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 577 #else 578 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 579 #endif 580 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 581 /* Print Buffer Size */ 582 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 583 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 584 585 /* 586 * For booting Linux, the board info and command line data 587 * have to be in the first 64 MB of memory, since this is 588 * the maximum mapped by the Linux kernel during initialization. 589 */ 590 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 591 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 592 593 #if defined(CONFIG_CMD_KGDB) 594 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 595 #endif 596 597 /* 598 * Dynamic MTD Partition support with mtdparts 599 */ 600 #ifndef CONFIG_SYS_NO_FLASH 601 #define CONFIG_MTD_DEVICE 602 #define CONFIG_MTD_PARTITIONS 603 #define CONFIG_CMD_MTDPARTS 604 #define CONFIG_FLASH_CFI_MTD 605 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 606 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 607 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 608 "8m(kernel),512k(dtb),-(fs)" 609 #endif 610 /* 611 * Override partitions in device tree using info 612 * in "mtdparts" environment variable 613 */ 614 #ifdef CONFIG_CMD_MTDPARTS 615 #define CONFIG_FDT_FIXUP_PARTITIONS 616 #endif 617 618 /* 619 * Environment Configuration 620 */ 621 622 #if defined(CONFIG_TSEC_ENET) 623 #define CONFIG_HAS_ETH0 624 #define CONFIG_HAS_ETH1 625 #endif 626 627 #define CONFIG_HOSTNAME BSC9132qds 628 #define CONFIG_ROOTPATH "/opt/nfsroot" 629 #define CONFIG_BOOTFILE "uImage" 630 #define CONFIG_UBOOTPATH "u-boot.bin" 631 632 #define CONFIG_BAUDRATE 115200 633 634 #ifdef CONFIG_SDCARD 635 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 636 #else 637 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 638 #endif 639 640 #define CONFIG_EXTRA_ENV_SETTINGS \ 641 "netdev=eth0\0" \ 642 "uboot=" CONFIG_UBOOTPATH "\0" \ 643 "loadaddr=1000000\0" \ 644 "bootfile=uImage\0" \ 645 "consoledev=ttyS0\0" \ 646 "ramdiskaddr=2000000\0" \ 647 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 648 "fdtaddr=1e00000\0" \ 649 "fdtfile=bsc9132qds.dtb\0" \ 650 "bdev=sda1\0" \ 651 CONFIG_DEF_HWCONFIG\ 652 "othbootargs=mem=880M ramdisk_size=600000 " \ 653 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 654 "isolcpus=0\0" \ 655 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 656 "console=$consoledev,$baudrate $othbootargs; " \ 657 "usb start;" \ 658 "ext2load usb 0:4 $loadaddr $bootfile;" \ 659 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 660 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 661 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 662 "debug_halt_off=mw ff7e0e30 0xf0000000;" 663 664 #define CONFIG_NFSBOOTCOMMAND \ 665 "setenv bootargs root=/dev/nfs rw " \ 666 "nfsroot=$serverip:$rootpath " \ 667 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 668 "console=$consoledev,$baudrate $othbootargs;" \ 669 "tftp $loadaddr $bootfile;" \ 670 "tftp $fdtaddr $fdtfile;" \ 671 "bootm $loadaddr - $fdtaddr" 672 673 #define CONFIG_HDBOOT \ 674 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 675 "console=$consoledev,$baudrate $othbootargs;" \ 676 "usb start;" \ 677 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 678 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 679 "bootm $loadaddr - $fdtaddr" 680 681 #define CONFIG_RAMBOOTCOMMAND \ 682 "setenv bootargs root=/dev/ram rw " \ 683 "console=$consoledev,$baudrate $othbootargs; " \ 684 "tftp $ramdiskaddr $ramdiskfile;" \ 685 "tftp $loadaddr $bootfile;" \ 686 "tftp $fdtaddr $fdtfile;" \ 687 "bootm $loadaddr $ramdiskaddr $fdtaddr" 688 689 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 690 691 #include <asm/fsl_secure_boot.h> 692 693 #endif /* __CONFIG_H */ 694