1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #include <asm/config_mpc85xx.h> 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 21 #ifndef CONFIG_SECURE_BOOT 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #else 24 #define CONFIG_SYS_FSL_PBL_PBI \ 25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 26 #endif 27 28 #ifdef CONFIG_T1040RDB 29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 30 #endif 31 #ifdef CONFIG_T1042RDB_PI 32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 33 #endif 34 #ifdef CONFIG_T1042RDB 35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 36 #endif 37 #ifdef CONFIG_T1040D4RDB 38 #define CONFIG_SYS_FSL_PBL_RCW \ 39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 40 #endif 41 #ifdef CONFIG_T1042D4RDB 42 #define CONFIG_SYS_FSL_PBL_RCW \ 43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 44 #endif 45 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_SERIAL_SUPPORT 48 #define CONFIG_SPL_FLUSH_IMAGE 49 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 50 #define CONFIG_SPL_LIBGENERIC_SUPPORT 51 #define CONFIG_FSL_LAW /* Use common FSL init code */ 52 #define CONFIG_SYS_TEXT_BASE 0x30001000 53 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 54 #define CONFIG_SPL_PAD_TO 0x40000 55 #define CONFIG_SPL_MAX_SIZE 0x28000 56 #ifdef CONFIG_SPL_BUILD 57 #define CONFIG_SPL_SKIP_RELOCATE 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 60 #define CONFIG_SYS_NO_FLASH 61 #endif 62 #define RESET_VECTOR_OFFSET 0x27FFC 63 #define BOOT_PAGE_OFFSET 0x27000 64 65 #ifdef CONFIG_NAND 66 #define CONFIG_SPL_NAND_SUPPORT 67 #ifdef CONFIG_SECURE_BOOT 68 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 69 /* 70 * HDR would be appended at end of image and copied to DDR along 71 * with U-Boot image. 72 */ 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 74 CONFIG_U_BOOT_HDR_SIZE) 75 #else 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 77 #endif 78 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 79 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 80 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 82 #define CONFIG_SPL_NAND_BOOT 83 #endif 84 85 #ifdef CONFIG_SPIFLASH 86 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 87 #define CONFIG_SPL_SPI_SUPPORT 88 #define CONFIG_SPL_SPI_FLASH_SUPPORT 89 #define CONFIG_SPL_SPI_FLASH_MINIMAL 90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 95 #ifndef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #endif 98 #define CONFIG_SPL_SPI_BOOT 99 #endif 100 101 #ifdef CONFIG_SDCARD 102 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 103 #define CONFIG_SPL_MMC_SUPPORT 104 #define CONFIG_SPL_MMC_MINIMAL 105 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 106 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 107 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 108 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 109 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 110 #ifndef CONFIG_SPL_BUILD 111 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 112 #endif 113 #define CONFIG_SPL_MMC_BOOT 114 #endif 115 116 #endif 117 118 /* High Level Configuration Options */ 119 #define CONFIG_BOOKE 120 #define CONFIG_E500MC /* BOOKE e500mc family */ 121 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 122 #define CONFIG_MP /* support multiple processors */ 123 124 /* support deep sleep */ 125 #define CONFIG_DEEP_SLEEP 126 #if defined(CONFIG_DEEP_SLEEP) 127 #define CONFIG_BOARD_EARLY_INIT_F 128 #define CONFIG_SILENT_CONSOLE 129 #endif 130 131 #ifndef CONFIG_SYS_TEXT_BASE 132 #define CONFIG_SYS_TEXT_BASE 0xeff40000 133 #endif 134 135 #ifndef CONFIG_RESET_VECTOR_ADDRESS 136 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 137 #endif 138 139 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 140 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 141 #define CONFIG_FSL_IFC /* Enable IFC Support */ 142 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 143 #define CONFIG_PCI /* Enable PCI/PCIE */ 144 #define CONFIG_PCI_INDIRECT_BRIDGE 145 #define CONFIG_PCIE1 /* PCIE controller 1 */ 146 #define CONFIG_PCIE2 /* PCIE controller 2 */ 147 #define CONFIG_PCIE3 /* PCIE controller 3 */ 148 #define CONFIG_PCIE4 /* PCIE controller 4 */ 149 150 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 151 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 152 153 #define CONFIG_FSL_LAW /* Use common FSL init code */ 154 155 #define CONFIG_ENV_OVERWRITE 156 157 #ifndef CONFIG_SYS_NO_FLASH 158 #define CONFIG_FLASH_CFI_DRIVER 159 #define CONFIG_SYS_FLASH_CFI 160 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 161 #endif 162 163 #if defined(CONFIG_SPIFLASH) 164 #define CONFIG_SYS_EXTRA_ENV_RELOC 165 #define CONFIG_ENV_IS_IN_SPI_FLASH 166 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 167 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 168 #define CONFIG_ENV_SECT_SIZE 0x10000 169 #elif defined(CONFIG_SDCARD) 170 #define CONFIG_SYS_EXTRA_ENV_RELOC 171 #define CONFIG_ENV_IS_IN_MMC 172 #define CONFIG_SYS_MMC_ENV_DEV 0 173 #define CONFIG_ENV_SIZE 0x2000 174 #define CONFIG_ENV_OFFSET (512 * 0x800) 175 #elif defined(CONFIG_NAND) 176 #ifdef CONFIG_SECURE_BOOT 177 #define CONFIG_RAMBOOT_NAND 178 #define CONFIG_BOOTSCRIPT_COPY_RAM 179 #endif 180 #define CONFIG_SYS_EXTRA_ENV_RELOC 181 #define CONFIG_ENV_IS_IN_NAND 182 #define CONFIG_ENV_SIZE 0x2000 183 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 184 #else 185 #define CONFIG_ENV_IS_IN_FLASH 186 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 187 #define CONFIG_ENV_SIZE 0x2000 188 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 189 #endif 190 191 #define CONFIG_SYS_CLK_FREQ 100000000 192 #define CONFIG_DDR_CLK_FREQ 66666666 193 194 /* 195 * These can be toggled for performance analysis, otherwise use default. 196 */ 197 #define CONFIG_SYS_CACHE_STASHING 198 #define CONFIG_BACKSIDE_L2_CACHE 199 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 200 #define CONFIG_BTB /* toggle branch predition */ 201 #define CONFIG_DDR_ECC 202 #ifdef CONFIG_DDR_ECC 203 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 204 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 205 #endif 206 207 #define CONFIG_ENABLE_36BIT_PHYS 208 209 #define CONFIG_ADDR_MAP 210 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 211 212 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 213 #define CONFIG_SYS_MEMTEST_END 0x00400000 214 #define CONFIG_SYS_ALT_MEMTEST 215 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 216 217 /* 218 * Config the L3 Cache as L3 SRAM 219 */ 220 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 221 /* 222 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 223 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 224 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 225 */ 226 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 227 #define CONFIG_SYS_L3_SIZE 256 << 10 228 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 229 #ifdef CONFIG_RAMBOOT_PBL 230 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 231 #endif 232 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 233 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 234 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 235 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 236 237 #define CONFIG_SYS_DCSRBAR 0xf0000000 238 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 239 240 /* 241 * DDR Setup 242 */ 243 #define CONFIG_VERY_BIG_RAM 244 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 245 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 246 247 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 248 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 249 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 250 251 #define CONFIG_DDR_SPD 252 #ifndef CONFIG_SYS_FSL_DDR4 253 #define CONFIG_SYS_FSL_DDR3 254 #endif 255 256 #define CONFIG_SYS_SPD_BUS_NUM 0 257 #define SPD_EEPROM_ADDRESS 0x51 258 259 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 260 261 /* 262 * IFC Definitions 263 */ 264 #define CONFIG_SYS_FLASH_BASE 0xe8000000 265 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 266 267 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 268 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 269 CSPR_PORT_SIZE_16 | \ 270 CSPR_MSEL_NOR | \ 271 CSPR_V) 272 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 273 274 /* 275 * TDM Definition 276 */ 277 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 278 279 /* NOR Flash Timing Params */ 280 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 281 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 282 FTIM0_NOR_TEADC(0x5) | \ 283 FTIM0_NOR_TEAHC(0x5)) 284 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 285 FTIM1_NOR_TRAD_NOR(0x1A) |\ 286 FTIM1_NOR_TSEQRAD_NOR(0x13)) 287 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 288 FTIM2_NOR_TCH(0x4) | \ 289 FTIM2_NOR_TWPH(0x0E) | \ 290 FTIM2_NOR_TWP(0x1c)) 291 #define CONFIG_SYS_NOR_FTIM3 0x0 292 293 #define CONFIG_SYS_FLASH_QUIET_TEST 294 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 295 296 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 297 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 298 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 299 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 300 301 #define CONFIG_SYS_FLASH_EMPTY_INFO 302 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 303 304 /* CPLD on IFC */ 305 #define CPLD_LBMAP_MASK 0x3F 306 #define CPLD_BANK_SEL_MASK 0x07 307 #define CPLD_BANK_OVERRIDE 0x40 308 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 309 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 310 #define CPLD_LBMAP_RESET 0xFF 311 #define CPLD_LBMAP_SHIFT 0x03 312 313 #if defined(CONFIG_T1042RDB_PI) 314 #define CPLD_DIU_SEL_DFP 0x80 315 #elif defined(CONFIG_T1042D4RDB) 316 #define CPLD_DIU_SEL_DFP 0xc0 317 #endif 318 319 #if defined(CONFIG_T1040D4RDB) 320 #define CPLD_INT_MASK_ALL 0xFF 321 #define CPLD_INT_MASK_THERM 0x80 322 #define CPLD_INT_MASK_DVI_DFP 0x40 323 #define CPLD_INT_MASK_QSGMII1 0x20 324 #define CPLD_INT_MASK_QSGMII2 0x10 325 #define CPLD_INT_MASK_SGMI1 0x08 326 #define CPLD_INT_MASK_SGMI2 0x04 327 #define CPLD_INT_MASK_TDMR1 0x02 328 #define CPLD_INT_MASK_TDMR2 0x01 329 #endif 330 331 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 332 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 333 #define CONFIG_SYS_CSPR2_EXT (0xf) 334 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 335 | CSPR_PORT_SIZE_8 \ 336 | CSPR_MSEL_GPCM \ 337 | CSPR_V) 338 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 339 #define CONFIG_SYS_CSOR2 0x0 340 /* CPLD Timing parameters for IFC CS2 */ 341 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 342 FTIM0_GPCM_TEADC(0x0e) | \ 343 FTIM0_GPCM_TEAHC(0x0e)) 344 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 345 FTIM1_GPCM_TRAD(0x1f)) 346 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 347 FTIM2_GPCM_TCH(0x8) | \ 348 FTIM2_GPCM_TWP(0x1f)) 349 #define CONFIG_SYS_CS2_FTIM3 0x0 350 351 /* NAND Flash on IFC */ 352 #define CONFIG_NAND_FSL_IFC 353 #define CONFIG_SYS_NAND_BASE 0xff800000 354 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 355 356 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 357 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 358 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 359 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 360 | CSPR_V) 361 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 362 363 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 364 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 365 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 366 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 367 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 368 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 369 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 370 371 #define CONFIG_SYS_NAND_ONFI_DETECTION 372 373 /* ONFI NAND Flash mode0 Timing Params */ 374 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 375 FTIM0_NAND_TWP(0x18) | \ 376 FTIM0_NAND_TWCHT(0x07) | \ 377 FTIM0_NAND_TWH(0x0a)) 378 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 379 FTIM1_NAND_TWBE(0x39) | \ 380 FTIM1_NAND_TRR(0x0e) | \ 381 FTIM1_NAND_TRP(0x18)) 382 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 383 FTIM2_NAND_TREH(0x0a) | \ 384 FTIM2_NAND_TWHRE(0x1e)) 385 #define CONFIG_SYS_NAND_FTIM3 0x0 386 387 #define CONFIG_SYS_NAND_DDR_LAW 11 388 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 389 #define CONFIG_SYS_MAX_NAND_DEVICE 1 390 #define CONFIG_CMD_NAND 391 392 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 393 394 #if defined(CONFIG_NAND) 395 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 396 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 397 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 398 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 399 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 400 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 401 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 402 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 403 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 404 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 405 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 406 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 407 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 408 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 409 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 410 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 411 #else 412 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 413 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 414 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 415 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 416 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 417 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 418 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 419 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 420 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 421 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 422 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 423 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 424 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 425 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 426 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 427 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 428 #endif 429 430 #ifdef CONFIG_SPL_BUILD 431 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 432 #else 433 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 434 #endif 435 436 #if defined(CONFIG_RAMBOOT_PBL) 437 #define CONFIG_SYS_RAMBOOT 438 #endif 439 440 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 441 #if defined(CONFIG_NAND) 442 #define CONFIG_A008044_WORKAROUND 443 #endif 444 #endif 445 446 #define CONFIG_BOARD_EARLY_INIT_R 447 #define CONFIG_MISC_INIT_R 448 449 #define CONFIG_HWCONFIG 450 451 /* define to use L1 as initial stack */ 452 #define CONFIG_L1_INIT_RAM 453 #define CONFIG_SYS_INIT_RAM_LOCK 454 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 457 /* The assembler doesn't like typecast */ 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 459 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 460 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 461 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 462 463 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 464 GENERATED_GBL_DATA_SIZE) 465 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 466 467 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 468 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 469 470 /* Serial Port - controlled on board with jumper J8 471 * open - index 2 472 * shorted - index 1 473 */ 474 #define CONFIG_CONS_INDEX 1 475 #define CONFIG_SYS_NS16550_SERIAL 476 #define CONFIG_SYS_NS16550_REG_SIZE 1 477 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 478 479 #define CONFIG_SYS_BAUDRATE_TABLE \ 480 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 481 482 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 483 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 484 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 485 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 486 #ifndef CONFIG_SPL_BUILD 487 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 488 #endif 489 490 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 491 /* Video */ 492 #define CONFIG_FSL_DIU_FB 493 494 #ifdef CONFIG_FSL_DIU_FB 495 #define CONFIG_FSL_DIU_CH7301 496 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 497 #define CONFIG_VIDEO 498 #define CONFIG_CMD_BMP 499 #define CONFIG_CFB_CONSOLE 500 #define CONFIG_CFB_CONSOLE_ANSI 501 #define CONFIG_VIDEO_SW_CURSOR 502 #define CONFIG_VGA_AS_SINGLE_DEVICE 503 #define CONFIG_VIDEO_LOGO 504 #define CONFIG_VIDEO_BMP_LOGO 505 #endif 506 #endif 507 508 /* I2C */ 509 #define CONFIG_SYS_I2C 510 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 511 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 512 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 513 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 514 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 515 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 516 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 518 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 519 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 520 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 521 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 522 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 523 524 /* I2C bus multiplexer */ 525 #define I2C_MUX_PCA_ADDR 0x70 526 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 527 #define I2C_MUX_CH_DEFAULT 0x8 528 #endif 529 530 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 531 /* LDI/DVI Encoder for display */ 532 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 533 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 534 535 /* 536 * RTC configuration 537 */ 538 #define RTC 539 #define CONFIG_RTC_DS1337 1 540 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 541 542 /*DVI encoder*/ 543 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 544 #endif 545 546 /* 547 * eSPI - Enhanced SPI 548 */ 549 #define CONFIG_SPI_FLASH_BAR 550 #define CONFIG_SF_DEFAULT_SPEED 10000000 551 #define CONFIG_SF_DEFAULT_MODE 0 552 #define CONFIG_ENV_SPI_BUS 0 553 #define CONFIG_ENV_SPI_CS 0 554 #define CONFIG_ENV_SPI_MAX_HZ 10000000 555 #define CONFIG_ENV_SPI_MODE 0 556 557 /* 558 * General PCI 559 * Memory space is mapped 1-1, but I/O space must start from 0. 560 */ 561 562 #ifdef CONFIG_PCI 563 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 564 #ifdef CONFIG_PCIE1 565 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 566 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 567 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 568 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 569 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 570 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 571 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 572 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 573 #endif 574 575 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 576 #ifdef CONFIG_PCIE2 577 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 578 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 579 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 580 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 581 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 582 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 583 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 584 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 585 #endif 586 587 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 588 #ifdef CONFIG_PCIE3 589 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 590 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 591 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 592 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 593 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 594 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 595 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 596 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 597 #endif 598 599 /* controller 4, Base address 203000 */ 600 #ifdef CONFIG_PCIE4 601 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 602 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 603 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 604 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 605 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 606 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 607 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 608 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 609 #endif 610 611 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 612 613 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 614 #define CONFIG_DOS_PARTITION 615 #endif /* CONFIG_PCI */ 616 617 /* SATA */ 618 #define CONFIG_FSL_SATA_V2 619 #ifdef CONFIG_FSL_SATA_V2 620 #define CONFIG_LIBATA 621 #define CONFIG_FSL_SATA 622 623 #define CONFIG_SYS_SATA_MAX_DEVICE 1 624 #define CONFIG_SATA1 625 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 626 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 627 628 #define CONFIG_LBA48 629 #define CONFIG_CMD_SATA 630 #define CONFIG_DOS_PARTITION 631 #endif 632 633 /* 634 * USB 635 */ 636 #define CONFIG_HAS_FSL_DR_USB 637 638 #ifdef CONFIG_HAS_FSL_DR_USB 639 #define CONFIG_USB_EHCI 640 641 #ifdef CONFIG_USB_EHCI 642 #define CONFIG_USB_EHCI_FSL 643 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 644 #endif 645 #endif 646 647 #define CONFIG_MMC 648 649 #ifdef CONFIG_MMC 650 #define CONFIG_FSL_ESDHC 651 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 652 #define CONFIG_GENERIC_MMC 653 #define CONFIG_DOS_PARTITION 654 #endif 655 656 /* Qman/Bman */ 657 #ifndef CONFIG_NOBQFMAN 658 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 659 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 660 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 661 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 662 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 663 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 664 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 665 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 666 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 667 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 668 CONFIG_SYS_BMAN_CENA_SIZE) 669 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 670 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 671 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 672 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 673 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 674 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 675 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 676 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 677 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 678 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 679 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 680 CONFIG_SYS_QMAN_CENA_SIZE) 681 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 682 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 683 684 #define CONFIG_SYS_DPAA_FMAN 685 #define CONFIG_SYS_DPAA_PME 686 687 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 688 #define CONFIG_QE 689 #define CONFIG_U_QE 690 #endif 691 692 /* Default address of microcode for the Linux Fman driver */ 693 #if defined(CONFIG_SPIFLASH) 694 /* 695 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 696 * env, so we got 0x110000. 697 */ 698 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 699 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 700 #elif defined(CONFIG_SDCARD) 701 /* 702 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 703 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 704 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 705 */ 706 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 707 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 708 #elif defined(CONFIG_NAND) 709 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 710 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 711 #else 712 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 713 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 714 #endif 715 716 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 717 #if defined(CONFIG_SPIFLASH) 718 #define CONFIG_SYS_QE_FW_ADDR 0x130000 719 #elif defined(CONFIG_SDCARD) 720 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 721 #elif defined(CONFIG_NAND) 722 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 723 #else 724 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 725 #endif 726 #endif 727 728 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 729 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 730 #endif /* CONFIG_NOBQFMAN */ 731 732 #ifdef CONFIG_SYS_DPAA_FMAN 733 #define CONFIG_FMAN_ENET 734 #define CONFIG_PHY_VITESSE 735 #define CONFIG_PHY_REALTEK 736 #endif 737 738 #ifdef CONFIG_FMAN_ENET 739 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 740 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 741 #elif defined(CONFIG_T1040D4RDB) 742 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 743 #elif defined(CONFIG_T1042D4RDB) 744 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 745 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 746 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 747 #endif 748 749 #ifdef CONFIG_T104XD4RDB 750 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 751 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 752 #else 753 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 754 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 755 #endif 756 757 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 758 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 759 #define CONFIG_VSC9953 760 #define CONFIG_CMD_ETHSW 761 #ifdef CONFIG_T1040RDB 762 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 763 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 764 #else 765 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 766 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 767 #endif 768 #endif 769 770 #define CONFIG_MII /* MII PHY management */ 771 #define CONFIG_ETHPRIME "FM1@DTSEC4" 772 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 773 #endif 774 775 /* 776 * Environment 777 */ 778 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 779 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 780 781 /* 782 * Command line configuration. 783 */ 784 #ifdef CONFIG_T1042RDB_PI 785 #define CONFIG_CMD_DATE 786 #endif 787 #define CONFIG_CMD_ERRATA 788 #define CONFIG_CMD_IRQ 789 #define CONFIG_CMD_REGINFO 790 791 #ifdef CONFIG_PCI 792 #define CONFIG_CMD_PCI 793 #endif 794 795 /* Hash command with SHA acceleration supported in hardware */ 796 #ifdef CONFIG_FSL_CAAM 797 #define CONFIG_CMD_HASH 798 #define CONFIG_SHA_HW_ACCEL 799 #endif 800 801 /* 802 * Miscellaneous configurable options 803 */ 804 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 805 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 806 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 807 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 808 #ifdef CONFIG_CMD_KGDB 809 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 810 #else 811 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 812 #endif 813 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 814 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 815 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 816 817 /* 818 * For booting Linux, the board info and command line data 819 * have to be in the first 64 MB of memory, since this is 820 * the maximum mapped by the Linux kernel during initialization. 821 */ 822 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 823 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 824 825 #ifdef CONFIG_CMD_KGDB 826 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 827 #endif 828 829 /* 830 * Dynamic MTD Partition support with mtdparts 831 */ 832 #ifndef CONFIG_SYS_NO_FLASH 833 #define CONFIG_MTD_DEVICE 834 #define CONFIG_MTD_PARTITIONS 835 #define CONFIG_CMD_MTDPARTS 836 #define CONFIG_FLASH_CFI_MTD 837 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 838 "spi0=spife110000.0" 839 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 840 "128k(dtb),96m(fs),-(user);"\ 841 "fff800000.flash:2m(uboot),9m(kernel),"\ 842 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 843 "2m(uboot),9m(kernel),128k(dtb),-(user)" 844 #endif 845 846 /* 847 * Environment Configuration 848 */ 849 #define CONFIG_ROOTPATH "/opt/nfsroot" 850 #define CONFIG_BOOTFILE "uImage" 851 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 852 853 /* default location for tftp and bootm */ 854 #define CONFIG_LOADADDR 1000000 855 856 857 #define CONFIG_BAUDRATE 115200 858 859 #define __USB_PHY_TYPE utmi 860 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 861 862 #ifdef CONFIG_T1040RDB 863 #define FDTFILE "t1040rdb/t1040rdb.dtb" 864 #elif defined(CONFIG_T1042RDB_PI) 865 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 866 #elif defined(CONFIG_T1042RDB) 867 #define FDTFILE "t1042rdb/t1042rdb.dtb" 868 #elif defined(CONFIG_T1040D4RDB) 869 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 870 #elif defined(CONFIG_T1042D4RDB) 871 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 872 #endif 873 874 #ifdef CONFIG_FSL_DIU_FB 875 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 876 #else 877 #define DIU_ENVIRONMENT 878 #endif 879 880 #define CONFIG_EXTRA_ENV_SETTINGS \ 881 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 882 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 883 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 884 "netdev=eth0\0" \ 885 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 886 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 887 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 888 "tftpflash=tftpboot $loadaddr $uboot && " \ 889 "protect off $ubootaddr +$filesize && " \ 890 "erase $ubootaddr +$filesize && " \ 891 "cp.b $loadaddr $ubootaddr $filesize && " \ 892 "protect on $ubootaddr +$filesize && " \ 893 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 894 "consoledev=ttyS0\0" \ 895 "ramdiskaddr=2000000\0" \ 896 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 897 "fdtaddr=1e00000\0" \ 898 "fdtfile=" __stringify(FDTFILE) "\0" \ 899 "bdev=sda3\0" 900 901 #define CONFIG_LINUX \ 902 "setenv bootargs root=/dev/ram rw " \ 903 "console=$consoledev,$baudrate $othbootargs;" \ 904 "setenv ramdiskaddr 0x02000000;" \ 905 "setenv fdtaddr 0x00c00000;" \ 906 "setenv loadaddr 0x1000000;" \ 907 "bootm $loadaddr $ramdiskaddr $fdtaddr" 908 909 #define CONFIG_HDBOOT \ 910 "setenv bootargs root=/dev/$bdev rw " \ 911 "console=$consoledev,$baudrate $othbootargs;" \ 912 "tftp $loadaddr $bootfile;" \ 913 "tftp $fdtaddr $fdtfile;" \ 914 "bootm $loadaddr - $fdtaddr" 915 916 #define CONFIG_NFSBOOTCOMMAND \ 917 "setenv bootargs root=/dev/nfs rw " \ 918 "nfsroot=$serverip:$rootpath " \ 919 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 920 "console=$consoledev,$baudrate $othbootargs;" \ 921 "tftp $loadaddr $bootfile;" \ 922 "tftp $fdtaddr $fdtfile;" \ 923 "bootm $loadaddr - $fdtaddr" 924 925 #define CONFIG_RAMBOOTCOMMAND \ 926 "setenv bootargs root=/dev/ram rw " \ 927 "console=$consoledev,$baudrate $othbootargs;" \ 928 "tftp $ramdiskaddr $ramdiskfile;" \ 929 "tftp $loadaddr $bootfile;" \ 930 "tftp $fdtaddr $fdtfile;" \ 931 "bootm $loadaddr $ramdiskaddr $fdtaddr" 932 933 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 934 935 #include <asm/fsl_secure_boot.h> 936 937 #endif /* __CONFIG_H */ 938