1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 46 #define CONFIG_SPL_SERIAL_SUPPORT 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 #define CONFIG_SYS_TEXT_BASE 0x00201000 51 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 52 #define CONFIG_SPL_PAD_TO 0x40000 53 #define CONFIG_SPL_MAX_SIZE 0x28000 54 #define RESET_VECTOR_OFFSET 0x27FFC 55 #define BOOT_PAGE_OFFSET 0x27000 56 #ifdef CONFIG_SPL_BUILD 57 #define CONFIG_SPL_SKIP_RELOCATE 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 60 #define CONFIG_SYS_NO_FLASH 61 #endif 62 63 #ifdef CONFIG_NAND 64 #define CONFIG_SPL_NAND_SUPPORT 65 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 66 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 67 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 68 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 69 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 70 #define CONFIG_SPL_NAND_BOOT 71 #endif 72 73 #ifdef CONFIG_SPIFLASH 74 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 75 #define CONFIG_SPL_SPI_SUPPORT 76 #define CONFIG_SPL_SPI_FLASH_SUPPORT 77 #define CONFIG_SPL_SPI_FLASH_MINIMAL 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #ifndef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #endif 86 #define CONFIG_SPL_SPI_BOOT 87 #endif 88 89 #ifdef CONFIG_SDCARD 90 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 91 #define CONFIG_SPL_MMC_MINIMAL 92 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 93 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 94 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 95 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 96 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 97 #ifndef CONFIG_SPL_BUILD 98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 99 #endif 100 #define CONFIG_SPL_MMC_BOOT 101 #endif 102 103 #endif /* CONFIG_RAMBOOT_PBL */ 104 105 #define CONFIG_SRIO_PCIE_BOOT_MASTER 106 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 107 /* Set 1M boot space */ 108 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 109 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 110 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 111 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 112 #define CONFIG_SYS_NO_FLASH 113 #endif 114 115 #ifndef CONFIG_SYS_TEXT_BASE 116 #define CONFIG_SYS_TEXT_BASE 0xeff40000 117 #endif 118 119 #ifndef CONFIG_RESET_VECTOR_ADDRESS 120 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 121 #endif 122 123 /* 124 * These can be toggled for performance analysis, otherwise use default. 125 */ 126 #define CONFIG_SYS_CACHE_STASHING 127 #define CONFIG_BTB /* toggle branch predition */ 128 #define CONFIG_DDR_ECC 129 #ifdef CONFIG_DDR_ECC 130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 131 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 132 #endif 133 134 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 135 #define CONFIG_SYS_MEMTEST_END 0x00400000 136 #define CONFIG_SYS_ALT_MEMTEST 137 138 #ifndef CONFIG_SYS_NO_FLASH 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 142 #endif 143 144 #if defined(CONFIG_SPIFLASH) 145 #define CONFIG_SYS_EXTRA_ENV_RELOC 146 #define CONFIG_ENV_IS_IN_SPI_FLASH 147 #define CONFIG_ENV_SPI_BUS 0 148 #define CONFIG_ENV_SPI_CS 0 149 #define CONFIG_ENV_SPI_MAX_HZ 10000000 150 #define CONFIG_ENV_SPI_MODE 0 151 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 152 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 153 #define CONFIG_ENV_SECT_SIZE 0x10000 154 #elif defined(CONFIG_SDCARD) 155 #define CONFIG_SYS_EXTRA_ENV_RELOC 156 #define CONFIG_ENV_IS_IN_MMC 157 #define CONFIG_SYS_MMC_ENV_DEV 0 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_OFFSET (512 * 0x800) 160 #elif defined(CONFIG_NAND) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_NAND 163 #define CONFIG_ENV_SIZE 0x2000 164 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 165 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 166 #define CONFIG_ENV_IS_IN_REMOTE 167 #define CONFIG_ENV_ADDR 0xffe20000 168 #define CONFIG_ENV_SIZE 0x2000 169 #elif defined(CONFIG_ENV_IS_NOWHERE) 170 #define CONFIG_ENV_SIZE 0x2000 171 #else 172 #define CONFIG_ENV_IS_IN_FLASH 173 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 174 #define CONFIG_ENV_SIZE 0x2000 175 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 176 #endif 177 178 #ifndef __ASSEMBLY__ 179 unsigned long get_board_sys_clk(void); 180 unsigned long get_board_ddr_clk(void); 181 #endif 182 183 #define CONFIG_SYS_CLK_FREQ 66660000 184 #define CONFIG_DDR_CLK_FREQ 133330000 185 186 /* 187 * Config the L3 Cache as L3 SRAM 188 */ 189 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 190 #define CONFIG_SYS_L3_SIZE (512 << 10) 191 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 192 #ifdef CONFIG_RAMBOOT_PBL 193 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 194 #endif 195 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 196 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 197 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 198 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 199 200 #define CONFIG_SYS_DCSRBAR 0xf0000000 201 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 202 203 /* EEPROM */ 204 #define CONFIG_ID_EEPROM 205 #define CONFIG_SYS_I2C_EEPROM_NXID 206 #define CONFIG_SYS_EEPROM_BUS_NUM 0 207 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 208 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 209 210 /* 211 * DDR Setup 212 */ 213 #define CONFIG_VERY_BIG_RAM 214 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 215 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 216 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 217 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 218 #define CONFIG_DDR_SPD 219 #define CONFIG_SYS_FSL_DDR3 220 #undef CONFIG_FSL_DDR_INTERACTIVE 221 #define CONFIG_SYS_SPD_BUS_NUM 0 222 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 223 #define SPD_EEPROM_ADDRESS1 0x51 224 #define SPD_EEPROM_ADDRESS2 0x52 225 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 226 #define CTRL_INTLV_PREFERED cacheline 227 228 /* 229 * IFC Definitions 230 */ 231 #define CONFIG_SYS_FLASH_BASE 0xe8000000 232 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 233 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 234 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 235 CSPR_PORT_SIZE_16 | \ 236 CSPR_MSEL_NOR | \ 237 CSPR_V) 238 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 239 240 /* NOR Flash Timing Params */ 241 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 242 243 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 244 FTIM0_NOR_TEADC(0x5) | \ 245 FTIM0_NOR_TEAHC(0x5)) 246 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 247 FTIM1_NOR_TRAD_NOR(0x1A) |\ 248 FTIM1_NOR_TSEQRAD_NOR(0x13)) 249 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 250 FTIM2_NOR_TCH(0x4) | \ 251 FTIM2_NOR_TWPH(0x0E) | \ 252 FTIM2_NOR_TWP(0x1c)) 253 #define CONFIG_SYS_NOR_FTIM3 0x0 254 255 #define CONFIG_SYS_FLASH_QUIET_TEST 256 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 257 258 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 259 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 260 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 261 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 262 #define CONFIG_SYS_FLASH_EMPTY_INFO 263 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 264 265 /* CPLD on IFC */ 266 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 267 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 268 #define CONFIG_SYS_CSPR2_EXT (0xf) 269 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 270 | CSPR_PORT_SIZE_8 \ 271 | CSPR_MSEL_GPCM \ 272 | CSPR_V) 273 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 274 #define CONFIG_SYS_CSOR2 0x0 275 276 /* CPLD Timing parameters for IFC CS2 */ 277 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 278 FTIM0_GPCM_TEADC(0x0e) | \ 279 FTIM0_GPCM_TEAHC(0x0e)) 280 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 281 FTIM1_GPCM_TRAD(0x1f)) 282 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 283 FTIM2_GPCM_TCH(0x8) | \ 284 FTIM2_GPCM_TWP(0x1f)) 285 #define CONFIG_SYS_CS2_FTIM3 0x0 286 287 /* NAND Flash on IFC */ 288 #define CONFIG_NAND_FSL_IFC 289 #define CONFIG_SYS_NAND_BASE 0xff800000 290 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 291 292 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 293 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 294 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 295 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 296 | CSPR_V) 297 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 298 299 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 300 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 301 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 302 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 303 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 304 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 305 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 306 307 #define CONFIG_SYS_NAND_ONFI_DETECTION 308 309 /* ONFI NAND Flash mode0 Timing Params */ 310 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 311 FTIM0_NAND_TWP(0x18) | \ 312 FTIM0_NAND_TWCHT(0x07) | \ 313 FTIM0_NAND_TWH(0x0a)) 314 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 315 FTIM1_NAND_TWBE(0x39) | \ 316 FTIM1_NAND_TRR(0x0e) | \ 317 FTIM1_NAND_TRP(0x18)) 318 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 319 FTIM2_NAND_TREH(0x0a) | \ 320 FTIM2_NAND_TWHRE(0x1e)) 321 #define CONFIG_SYS_NAND_FTIM3 0x0 322 323 #define CONFIG_SYS_NAND_DDR_LAW 11 324 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 325 #define CONFIG_SYS_MAX_NAND_DEVICE 1 326 #define CONFIG_CMD_NAND 327 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 328 329 #if defined(CONFIG_NAND) 330 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 331 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 332 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 333 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 334 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 335 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 336 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 337 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 338 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 339 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 340 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 341 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 342 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 343 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 344 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 345 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 346 #else 347 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 348 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 349 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 350 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 351 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 352 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 353 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 354 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 355 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 356 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 357 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 358 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 359 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 360 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 361 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 362 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 363 #endif 364 365 #if defined(CONFIG_RAMBOOT_PBL) 366 #define CONFIG_SYS_RAMBOOT 367 #endif 368 369 #ifdef CONFIG_SPL_BUILD 370 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 371 #else 372 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 373 #endif 374 375 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 376 #define CONFIG_MISC_INIT_R 377 #define CONFIG_HWCONFIG 378 379 /* define to use L1 as initial stack */ 380 #define CONFIG_L1_INIT_RAM 381 #define CONFIG_SYS_INIT_RAM_LOCK 382 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 383 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 385 /* The assembler doesn't like typecast */ 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 387 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 388 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 389 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 390 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 391 GENERATED_GBL_DATA_SIZE) 392 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 393 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 394 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 395 396 /* 397 * Serial Port 398 */ 399 #define CONFIG_CONS_INDEX 1 400 #define CONFIG_SYS_NS16550_SERIAL 401 #define CONFIG_SYS_NS16550_REG_SIZE 1 402 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 403 #define CONFIG_SYS_BAUDRATE_TABLE \ 404 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 409 410 /* 411 * I2C 412 */ 413 #define CONFIG_SYS_I2C 414 #define CONFIG_SYS_I2C_FSL 415 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 417 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 419 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 420 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 421 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 422 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 423 #define CONFIG_SYS_FSL_I2C_SPEED 100000 424 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 425 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 426 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 427 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 428 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 429 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 430 #define I2C_MUX_CH_DEFAULT 0x8 431 432 #define I2C_MUX_CH_VOL_MONITOR 0xa 433 434 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 435 #ifndef CONFIG_SPL_BUILD 436 #define CONFIG_VID 437 #endif 438 #define CONFIG_VOL_MONITOR_IR36021_SET 439 #define CONFIG_VOL_MONITOR_IR36021_READ 440 /* The lowest and highest voltage allowed for T208xRDB */ 441 #define VDD_MV_MIN 819 442 #define VDD_MV_MAX 1212 443 444 /* 445 * RapidIO 446 */ 447 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 448 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 449 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 450 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 451 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 452 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 453 /* 454 * for slave u-boot IMAGE instored in master memory space, 455 * PHYS must be aligned based on the SIZE 456 */ 457 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 458 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 459 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 460 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 461 /* 462 * for slave UCODE and ENV instored in master memory space, 463 * PHYS must be aligned based on the SIZE 464 */ 465 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 466 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 467 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 468 469 /* slave core release by master*/ 470 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 471 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 472 473 /* 474 * SRIO_PCIE_BOOT - SLAVE 475 */ 476 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 477 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 478 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 479 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 480 #endif 481 482 /* 483 * eSPI - Enhanced SPI 484 */ 485 #ifdef CONFIG_SPI_FLASH 486 #define CONFIG_SPI_FLASH_BAR 487 #define CONFIG_SF_DEFAULT_SPEED 10000000 488 #define CONFIG_SF_DEFAULT_MODE 0 489 #endif 490 491 /* 492 * General PCI 493 * Memory space is mapped 1-1, but I/O space must start from 0. 494 */ 495 #define CONFIG_PCI /* Enable PCI/PCIE */ 496 #define CONFIG_PCIE1 /* PCIE controller 1 */ 497 #define CONFIG_PCIE2 /* PCIE controller 2 */ 498 #define CONFIG_PCIE3 /* PCIE controller 3 */ 499 #define CONFIG_PCIE4 /* PCIE controller 4 */ 500 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 501 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 502 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 503 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 504 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 505 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 506 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 507 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 508 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 509 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 510 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 511 512 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 513 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 514 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 515 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 516 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 517 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 518 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 519 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 520 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 521 522 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 523 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 524 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 526 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 527 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 528 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 529 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 530 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 531 532 /* controller 4, Base address 203000 */ 533 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 534 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 535 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 536 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 537 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 538 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 539 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 540 541 #ifdef CONFIG_PCI 542 #define CONFIG_PCI_INDIRECT_BRIDGE 543 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 544 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 545 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 546 #define CONFIG_DOS_PARTITION 547 #endif 548 549 /* Qman/Bman */ 550 #ifndef CONFIG_NOBQFMAN 551 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 552 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 553 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 554 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 555 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 556 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 557 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 558 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 559 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 560 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 561 CONFIG_SYS_BMAN_CENA_SIZE) 562 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 563 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 564 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 565 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 566 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 567 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 568 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 569 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 570 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 571 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 572 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 573 CONFIG_SYS_QMAN_CENA_SIZE) 574 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 575 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 576 577 #define CONFIG_SYS_DPAA_FMAN 578 #define CONFIG_SYS_DPAA_PME 579 #define CONFIG_SYS_PMAN 580 #define CONFIG_SYS_DPAA_DCE 581 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 582 #define CONFIG_SYS_INTERLAKEN 583 584 /* Default address of microcode for the Linux Fman driver */ 585 #if defined(CONFIG_SPIFLASH) 586 /* 587 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 588 * env, so we got 0x110000. 589 */ 590 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 591 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 592 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 593 #define CONFIG_CORTINA_FW_ADDR 0x120000 594 595 #elif defined(CONFIG_SDCARD) 596 /* 597 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 598 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 599 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 600 */ 601 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 602 #define CONFIG_SYS_CORTINA_FW_IN_MMC 603 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 604 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 605 606 #elif defined(CONFIG_NAND) 607 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 608 #define CONFIG_SYS_CORTINA_FW_IN_NAND 609 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 610 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 611 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 612 /* 613 * Slave has no ucode locally, it can fetch this from remote. When implementing 614 * in two corenet boards, slave's ucode could be stored in master's memory 615 * space, the address can be mapped from slave TLB->slave LAW-> 616 * slave SRIO or PCIE outbound window->master inbound window-> 617 * master LAW->the ucode address in master's memory space. 618 */ 619 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 620 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 621 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 622 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 623 #else 624 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 625 #define CONFIG_SYS_CORTINA_FW_IN_NOR 626 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 627 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 628 #endif 629 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 630 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 631 #endif /* CONFIG_NOBQFMAN */ 632 633 #ifdef CONFIG_SYS_DPAA_FMAN 634 #define CONFIG_FMAN_ENET 635 #define CONFIG_PHYLIB_10G 636 #define CONFIG_PHY_AQUANTIA 637 #define CONFIG_PHY_CORTINA 638 #define CONFIG_PHY_REALTEK 639 #define CONFIG_CORTINA_FW_LENGTH 0x40000 640 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 641 #define RGMII_PHY2_ADDR 0x02 642 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 643 #define CORTINA_PHY_ADDR2 0x0d 644 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 645 #define FM1_10GEC4_PHY_ADDR 0x01 646 #endif 647 648 #ifdef CONFIG_FMAN_ENET 649 #define CONFIG_MII /* MII PHY management */ 650 #define CONFIG_ETHPRIME "FM1@DTSEC3" 651 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 652 #endif 653 654 /* 655 * SATA 656 */ 657 #ifdef CONFIG_FSL_SATA_V2 658 #define CONFIG_LIBATA 659 #define CONFIG_FSL_SATA 660 #define CONFIG_SYS_SATA_MAX_DEVICE 2 661 #define CONFIG_SATA1 662 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 663 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 664 #define CONFIG_SATA2 665 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 666 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 667 #define CONFIG_LBA48 668 #define CONFIG_CMD_SATA 669 #define CONFIG_DOS_PARTITION 670 #endif 671 672 /* 673 * USB 674 */ 675 #ifdef CONFIG_USB_EHCI 676 #define CONFIG_USB_EHCI_FSL 677 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 678 #define CONFIG_HAS_FSL_DR_USB 679 #endif 680 681 /* 682 * SDHC 683 */ 684 #ifdef CONFIG_MMC 685 #define CONFIG_FSL_ESDHC 686 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 687 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 688 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 689 #define CONFIG_GENERIC_MMC 690 #define CONFIG_DOS_PARTITION 691 #endif 692 693 /* 694 * Dynamic MTD Partition support with mtdparts 695 */ 696 #ifndef CONFIG_SYS_NO_FLASH 697 #define CONFIG_MTD_DEVICE 698 #define CONFIG_MTD_PARTITIONS 699 #define CONFIG_CMD_MTDPARTS 700 #define CONFIG_FLASH_CFI_MTD 701 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 702 "spi0=spife110000.1" 703 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 704 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 705 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 706 "1m(uboot),5m(kernel),128k(dtb),-(user)" 707 #endif 708 709 /* 710 * Environment 711 */ 712 713 /* 714 * Command line configuration. 715 */ 716 #define CONFIG_CMD_ERRATA 717 #define CONFIG_CMD_REGINFO 718 719 #ifdef CONFIG_PCI 720 #define CONFIG_CMD_PCI 721 #endif 722 723 /* Hash command with SHA acceleration supported in hardware */ 724 #ifdef CONFIG_FSL_CAAM 725 #define CONFIG_CMD_HASH 726 #define CONFIG_SHA_HW_ACCEL 727 #endif 728 729 /* 730 * Miscellaneous configurable options 731 */ 732 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 733 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 734 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 735 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 736 #ifdef CONFIG_CMD_KGDB 737 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 738 #else 739 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 740 #endif 741 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 742 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 743 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 744 745 /* 746 * For booting Linux, the board info and command line data 747 * have to be in the first 64 MB of memory, since this is 748 * the maximum mapped by the Linux kernel during initialization. 749 */ 750 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 751 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 752 753 #ifdef CONFIG_CMD_KGDB 754 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 755 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 756 #endif 757 758 /* 759 * Environment Configuration 760 */ 761 #define CONFIG_ROOTPATH "/opt/nfsroot" 762 #define CONFIG_BOOTFILE "uImage" 763 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 764 765 /* default location for tftp and bootm */ 766 #define CONFIG_LOADADDR 1000000 767 #define CONFIG_BAUDRATE 115200 768 #define __USB_PHY_TYPE utmi 769 770 #define CONFIG_EXTRA_ENV_SETTINGS \ 771 "hwconfig=fsl_ddr:" \ 772 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 773 "bank_intlv=auto;" \ 774 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 775 "netdev=eth0\0" \ 776 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 777 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 778 "tftpflash=tftpboot $loadaddr $uboot && " \ 779 "protect off $ubootaddr +$filesize && " \ 780 "erase $ubootaddr +$filesize && " \ 781 "cp.b $loadaddr $ubootaddr $filesize && " \ 782 "protect on $ubootaddr +$filesize && " \ 783 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 784 "consoledev=ttyS0\0" \ 785 "ramdiskaddr=2000000\0" \ 786 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 787 "fdtaddr=1e00000\0" \ 788 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 789 "bdev=sda3\0" 790 791 /* 792 * For emulation this causes u-boot to jump to the start of the 793 * proof point app code automatically 794 */ 795 #define CONFIG_PROOF_POINTS \ 796 "setenv bootargs root=/dev/$bdev rw " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "cpu 1 release 0x29000000 - - -;" \ 799 "cpu 2 release 0x29000000 - - -;" \ 800 "cpu 3 release 0x29000000 - - -;" \ 801 "cpu 4 release 0x29000000 - - -;" \ 802 "cpu 5 release 0x29000000 - - -;" \ 803 "cpu 6 release 0x29000000 - - -;" \ 804 "cpu 7 release 0x29000000 - - -;" \ 805 "go 0x29000000" 806 807 #define CONFIG_HVBOOT \ 808 "setenv bootargs config-addr=0x60000000; " \ 809 "bootm 0x01000000 - 0x00f00000" 810 811 #define CONFIG_ALU \ 812 "setenv bootargs root=/dev/$bdev rw " \ 813 "console=$consoledev,$baudrate $othbootargs;" \ 814 "cpu 1 release 0x01000000 - - -;" \ 815 "cpu 2 release 0x01000000 - - -;" \ 816 "cpu 3 release 0x01000000 - - -;" \ 817 "cpu 4 release 0x01000000 - - -;" \ 818 "cpu 5 release 0x01000000 - - -;" \ 819 "cpu 6 release 0x01000000 - - -;" \ 820 "cpu 7 release 0x01000000 - - -;" \ 821 "go 0x01000000" 822 823 #define CONFIG_LINUX \ 824 "setenv bootargs root=/dev/ram rw " \ 825 "console=$consoledev,$baudrate $othbootargs;" \ 826 "setenv ramdiskaddr 0x02000000;" \ 827 "setenv fdtaddr 0x00c00000;" \ 828 "setenv loadaddr 0x1000000;" \ 829 "bootm $loadaddr $ramdiskaddr $fdtaddr" 830 831 #define CONFIG_HDBOOT \ 832 "setenv bootargs root=/dev/$bdev rw " \ 833 "console=$consoledev,$baudrate $othbootargs;" \ 834 "tftp $loadaddr $bootfile;" \ 835 "tftp $fdtaddr $fdtfile;" \ 836 "bootm $loadaddr - $fdtaddr" 837 838 #define CONFIG_NFSBOOTCOMMAND \ 839 "setenv bootargs root=/dev/nfs rw " \ 840 "nfsroot=$serverip:$rootpath " \ 841 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 842 "console=$consoledev,$baudrate $othbootargs;" \ 843 "tftp $loadaddr $bootfile;" \ 844 "tftp $fdtaddr $fdtfile;" \ 845 "bootm $loadaddr - $fdtaddr" 846 847 #define CONFIG_RAMBOOTCOMMAND \ 848 "setenv bootargs root=/dev/ram rw " \ 849 "console=$consoledev,$baudrate $othbootargs;" \ 850 "tftp $ramdiskaddr $ramdiskfile;" \ 851 "tftp $loadaddr $bootfile;" \ 852 "tftp $fdtaddr $fdtfile;" \ 853 "bootm $loadaddr $ramdiskaddr $fdtaddr" 854 855 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 856 857 #include <asm/fsl_secure_boot.h> 858 859 #endif /* __T2080RDB_H */ 860