1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 46 #define CONFIG_SPL_SERIAL_SUPPORT 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 #define CONFIG_SYS_TEXT_BASE 0x00201000 51 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 52 #define CONFIG_SPL_PAD_TO 0x40000 53 #define CONFIG_SPL_MAX_SIZE 0x28000 54 #define RESET_VECTOR_OFFSET 0x27FFC 55 #define BOOT_PAGE_OFFSET 0x27000 56 #ifdef CONFIG_SPL_BUILD 57 #define CONFIG_SPL_SKIP_RELOCATE 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 60 #define CONFIG_SYS_NO_FLASH 61 #endif 62 63 #ifdef CONFIG_NAND 64 #define CONFIG_SPL_NAND_SUPPORT 65 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 66 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 67 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 68 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 69 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 70 #define CONFIG_SPL_NAND_BOOT 71 #endif 72 73 #ifdef CONFIG_SPIFLASH 74 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 75 #define CONFIG_SPL_SPI_SUPPORT 76 #define CONFIG_SPL_SPI_FLASH_SUPPORT 77 #define CONFIG_SPL_SPI_FLASH_MINIMAL 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #ifndef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #endif 86 #define CONFIG_SPL_SPI_BOOT 87 #endif 88 89 #ifdef CONFIG_SDCARD 90 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 91 #define CONFIG_SPL_MMC_SUPPORT 92 #define CONFIG_SPL_MMC_MINIMAL 93 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 94 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 95 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 96 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 97 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 98 #ifndef CONFIG_SPL_BUILD 99 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 100 #endif 101 #define CONFIG_SPL_MMC_BOOT 102 #endif 103 104 #endif /* CONFIG_RAMBOOT_PBL */ 105 106 #define CONFIG_SRIO_PCIE_BOOT_MASTER 107 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 108 /* Set 1M boot space */ 109 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 110 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 111 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 112 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 113 #define CONFIG_SYS_NO_FLASH 114 #endif 115 116 #ifndef CONFIG_SYS_TEXT_BASE 117 #define CONFIG_SYS_TEXT_BASE 0xeff40000 118 #endif 119 120 #ifndef CONFIG_RESET_VECTOR_ADDRESS 121 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 122 #endif 123 124 /* 125 * These can be toggled for performance analysis, otherwise use default. 126 */ 127 #define CONFIG_SYS_CACHE_STASHING 128 #define CONFIG_BTB /* toggle branch predition */ 129 #define CONFIG_DDR_ECC 130 #ifdef CONFIG_DDR_ECC 131 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 132 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 133 #endif 134 135 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 136 #define CONFIG_SYS_MEMTEST_END 0x00400000 137 #define CONFIG_SYS_ALT_MEMTEST 138 139 #ifndef CONFIG_SYS_NO_FLASH 140 #define CONFIG_FLASH_CFI_DRIVER 141 #define CONFIG_SYS_FLASH_CFI 142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 143 #endif 144 145 #if defined(CONFIG_SPIFLASH) 146 #define CONFIG_SYS_EXTRA_ENV_RELOC 147 #define CONFIG_ENV_IS_IN_SPI_FLASH 148 #define CONFIG_ENV_SPI_BUS 0 149 #define CONFIG_ENV_SPI_CS 0 150 #define CONFIG_ENV_SPI_MAX_HZ 10000000 151 #define CONFIG_ENV_SPI_MODE 0 152 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 153 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 154 #define CONFIG_ENV_SECT_SIZE 0x10000 155 #elif defined(CONFIG_SDCARD) 156 #define CONFIG_SYS_EXTRA_ENV_RELOC 157 #define CONFIG_ENV_IS_IN_MMC 158 #define CONFIG_SYS_MMC_ENV_DEV 0 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_OFFSET (512 * 0x800) 161 #elif defined(CONFIG_NAND) 162 #define CONFIG_SYS_EXTRA_ENV_RELOC 163 #define CONFIG_ENV_IS_IN_NAND 164 #define CONFIG_ENV_SIZE 0x2000 165 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 166 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 167 #define CONFIG_ENV_IS_IN_REMOTE 168 #define CONFIG_ENV_ADDR 0xffe20000 169 #define CONFIG_ENV_SIZE 0x2000 170 #elif defined(CONFIG_ENV_IS_NOWHERE) 171 #define CONFIG_ENV_SIZE 0x2000 172 #else 173 #define CONFIG_ENV_IS_IN_FLASH 174 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 175 #define CONFIG_ENV_SIZE 0x2000 176 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 177 #endif 178 179 #ifndef __ASSEMBLY__ 180 unsigned long get_board_sys_clk(void); 181 unsigned long get_board_ddr_clk(void); 182 #endif 183 184 #define CONFIG_SYS_CLK_FREQ 66660000 185 #define CONFIG_DDR_CLK_FREQ 133330000 186 187 /* 188 * Config the L3 Cache as L3 SRAM 189 */ 190 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 191 #define CONFIG_SYS_L3_SIZE (512 << 10) 192 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 193 #ifdef CONFIG_RAMBOOT_PBL 194 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 195 #endif 196 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 197 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 198 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 199 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 200 201 #define CONFIG_SYS_DCSRBAR 0xf0000000 202 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 203 204 /* EEPROM */ 205 #define CONFIG_ID_EEPROM 206 #define CONFIG_SYS_I2C_EEPROM_NXID 207 #define CONFIG_SYS_EEPROM_BUS_NUM 0 208 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 209 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 210 211 /* 212 * DDR Setup 213 */ 214 #define CONFIG_VERY_BIG_RAM 215 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 216 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 217 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 218 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 219 #define CONFIG_DDR_SPD 220 #define CONFIG_SYS_FSL_DDR3 221 #undef CONFIG_FSL_DDR_INTERACTIVE 222 #define CONFIG_SYS_SPD_BUS_NUM 0 223 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 224 #define SPD_EEPROM_ADDRESS1 0x51 225 #define SPD_EEPROM_ADDRESS2 0x52 226 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 227 #define CTRL_INTLV_PREFERED cacheline 228 229 /* 230 * IFC Definitions 231 */ 232 #define CONFIG_SYS_FLASH_BASE 0xe8000000 233 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 234 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 235 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 236 CSPR_PORT_SIZE_16 | \ 237 CSPR_MSEL_NOR | \ 238 CSPR_V) 239 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 240 241 /* NOR Flash Timing Params */ 242 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 243 244 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 245 FTIM0_NOR_TEADC(0x5) | \ 246 FTIM0_NOR_TEAHC(0x5)) 247 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 248 FTIM1_NOR_TRAD_NOR(0x1A) |\ 249 FTIM1_NOR_TSEQRAD_NOR(0x13)) 250 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 251 FTIM2_NOR_TCH(0x4) | \ 252 FTIM2_NOR_TWPH(0x0E) | \ 253 FTIM2_NOR_TWP(0x1c)) 254 #define CONFIG_SYS_NOR_FTIM3 0x0 255 256 #define CONFIG_SYS_FLASH_QUIET_TEST 257 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 261 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 262 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 263 #define CONFIG_SYS_FLASH_EMPTY_INFO 264 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 265 266 /* CPLD on IFC */ 267 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 268 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 269 #define CONFIG_SYS_CSPR2_EXT (0xf) 270 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 271 | CSPR_PORT_SIZE_8 \ 272 | CSPR_MSEL_GPCM \ 273 | CSPR_V) 274 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 275 #define CONFIG_SYS_CSOR2 0x0 276 277 /* CPLD Timing parameters for IFC CS2 */ 278 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 279 FTIM0_GPCM_TEADC(0x0e) | \ 280 FTIM0_GPCM_TEAHC(0x0e)) 281 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 282 FTIM1_GPCM_TRAD(0x1f)) 283 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 284 FTIM2_GPCM_TCH(0x8) | \ 285 FTIM2_GPCM_TWP(0x1f)) 286 #define CONFIG_SYS_CS2_FTIM3 0x0 287 288 /* NAND Flash on IFC */ 289 #define CONFIG_NAND_FSL_IFC 290 #define CONFIG_SYS_NAND_BASE 0xff800000 291 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 292 293 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 294 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 295 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 296 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 297 | CSPR_V) 298 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 299 300 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 301 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 302 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 303 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 304 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 305 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 306 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 307 308 #define CONFIG_SYS_NAND_ONFI_DETECTION 309 310 /* ONFI NAND Flash mode0 Timing Params */ 311 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 312 FTIM0_NAND_TWP(0x18) | \ 313 FTIM0_NAND_TWCHT(0x07) | \ 314 FTIM0_NAND_TWH(0x0a)) 315 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 316 FTIM1_NAND_TWBE(0x39) | \ 317 FTIM1_NAND_TRR(0x0e) | \ 318 FTIM1_NAND_TRP(0x18)) 319 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 320 FTIM2_NAND_TREH(0x0a) | \ 321 FTIM2_NAND_TWHRE(0x1e)) 322 #define CONFIG_SYS_NAND_FTIM3 0x0 323 324 #define CONFIG_SYS_NAND_DDR_LAW 11 325 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 326 #define CONFIG_SYS_MAX_NAND_DEVICE 1 327 #define CONFIG_CMD_NAND 328 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 329 330 #if defined(CONFIG_NAND) 331 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 332 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 333 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 334 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 335 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 336 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 337 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 338 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 339 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 340 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 341 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 342 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 343 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 344 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 345 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 346 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 347 #else 348 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 349 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 350 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 351 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 352 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 353 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 354 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 355 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 356 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 357 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 358 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 359 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 360 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 361 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 362 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 363 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 364 #endif 365 366 #if defined(CONFIG_RAMBOOT_PBL) 367 #define CONFIG_SYS_RAMBOOT 368 #endif 369 370 #ifdef CONFIG_SPL_BUILD 371 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 372 #else 373 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 374 #endif 375 376 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 377 #define CONFIG_MISC_INIT_R 378 #define CONFIG_HWCONFIG 379 380 /* define to use L1 as initial stack */ 381 #define CONFIG_L1_INIT_RAM 382 #define CONFIG_SYS_INIT_RAM_LOCK 383 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 384 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 386 /* The assembler doesn't like typecast */ 387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 388 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 389 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 390 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 391 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 392 GENERATED_GBL_DATA_SIZE) 393 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 394 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 395 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 396 397 /* 398 * Serial Port 399 */ 400 #define CONFIG_CONS_INDEX 1 401 #define CONFIG_SYS_NS16550_SERIAL 402 #define CONFIG_SYS_NS16550_REG_SIZE 1 403 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 404 #define CONFIG_SYS_BAUDRATE_TABLE \ 405 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 408 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 409 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 410 411 /* 412 * I2C 413 */ 414 #define CONFIG_SYS_I2C 415 #define CONFIG_SYS_I2C_FSL 416 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 417 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 418 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 419 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 420 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 421 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 422 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 423 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 424 #define CONFIG_SYS_FSL_I2C_SPEED 100000 425 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 426 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 427 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 428 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 429 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 430 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 431 #define I2C_MUX_CH_DEFAULT 0x8 432 433 #define I2C_MUX_CH_VOL_MONITOR 0xa 434 435 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 436 #ifndef CONFIG_SPL_BUILD 437 #define CONFIG_VID 438 #endif 439 #define CONFIG_VOL_MONITOR_IR36021_SET 440 #define CONFIG_VOL_MONITOR_IR36021_READ 441 /* The lowest and highest voltage allowed for T208xRDB */ 442 #define VDD_MV_MIN 819 443 #define VDD_MV_MAX 1212 444 445 /* 446 * RapidIO 447 */ 448 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 449 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 450 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 451 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 452 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 453 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 454 /* 455 * for slave u-boot IMAGE instored in master memory space, 456 * PHYS must be aligned based on the SIZE 457 */ 458 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 459 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 460 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 461 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 462 /* 463 * for slave UCODE and ENV instored in master memory space, 464 * PHYS must be aligned based on the SIZE 465 */ 466 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 467 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 468 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 469 470 /* slave core release by master*/ 471 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 472 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 473 474 /* 475 * SRIO_PCIE_BOOT - SLAVE 476 */ 477 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 478 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 479 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 480 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 481 #endif 482 483 /* 484 * eSPI - Enhanced SPI 485 */ 486 #ifdef CONFIG_SPI_FLASH 487 #define CONFIG_SPI_FLASH_BAR 488 #define CONFIG_SF_DEFAULT_SPEED 10000000 489 #define CONFIG_SF_DEFAULT_MODE 0 490 #endif 491 492 /* 493 * General PCI 494 * Memory space is mapped 1-1, but I/O space must start from 0. 495 */ 496 #define CONFIG_PCI /* Enable PCI/PCIE */ 497 #define CONFIG_PCIE1 /* PCIE controller 1 */ 498 #define CONFIG_PCIE2 /* PCIE controller 2 */ 499 #define CONFIG_PCIE3 /* PCIE controller 3 */ 500 #define CONFIG_PCIE4 /* PCIE controller 4 */ 501 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 502 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 503 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 504 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 505 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 506 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 507 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 508 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 509 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 510 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 511 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 512 513 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 514 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 515 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 516 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 517 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 518 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 519 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 520 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 521 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 522 523 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 524 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 525 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 526 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 527 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 528 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 529 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 530 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 531 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 532 533 /* controller 4, Base address 203000 */ 534 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 535 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 536 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 537 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 538 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 539 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 540 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 541 542 #ifdef CONFIG_PCI 543 #define CONFIG_PCI_INDIRECT_BRIDGE 544 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 545 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 546 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 547 #define CONFIG_DOS_PARTITION 548 #endif 549 550 /* Qman/Bman */ 551 #ifndef CONFIG_NOBQFMAN 552 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 553 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 554 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 555 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 556 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 557 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 558 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 559 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 560 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 561 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 562 CONFIG_SYS_BMAN_CENA_SIZE) 563 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 564 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 565 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 566 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 567 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 568 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 569 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 570 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 571 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 572 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 573 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 574 CONFIG_SYS_QMAN_CENA_SIZE) 575 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 576 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 577 578 #define CONFIG_SYS_DPAA_FMAN 579 #define CONFIG_SYS_DPAA_PME 580 #define CONFIG_SYS_PMAN 581 #define CONFIG_SYS_DPAA_DCE 582 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 583 #define CONFIG_SYS_INTERLAKEN 584 585 /* Default address of microcode for the Linux Fman driver */ 586 #if defined(CONFIG_SPIFLASH) 587 /* 588 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 589 * env, so we got 0x110000. 590 */ 591 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 592 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 593 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 594 #define CONFIG_CORTINA_FW_ADDR 0x120000 595 596 #elif defined(CONFIG_SDCARD) 597 /* 598 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 599 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 600 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 601 */ 602 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 603 #define CONFIG_SYS_CORTINA_FW_IN_MMC 604 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 605 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 606 607 #elif defined(CONFIG_NAND) 608 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 609 #define CONFIG_SYS_CORTINA_FW_IN_NAND 610 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 611 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 612 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 613 /* 614 * Slave has no ucode locally, it can fetch this from remote. When implementing 615 * in two corenet boards, slave's ucode could be stored in master's memory 616 * space, the address can be mapped from slave TLB->slave LAW-> 617 * slave SRIO or PCIE outbound window->master inbound window-> 618 * master LAW->the ucode address in master's memory space. 619 */ 620 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 621 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 622 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 623 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 624 #else 625 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 626 #define CONFIG_SYS_CORTINA_FW_IN_NOR 627 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 628 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 629 #endif 630 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 631 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 632 #endif /* CONFIG_NOBQFMAN */ 633 634 #ifdef CONFIG_SYS_DPAA_FMAN 635 #define CONFIG_FMAN_ENET 636 #define CONFIG_PHYLIB_10G 637 #define CONFIG_PHY_AQUANTIA 638 #define CONFIG_PHY_CORTINA 639 #define CONFIG_PHY_REALTEK 640 #define CONFIG_CORTINA_FW_LENGTH 0x40000 641 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 642 #define RGMII_PHY2_ADDR 0x02 643 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 644 #define CORTINA_PHY_ADDR2 0x0d 645 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 646 #define FM1_10GEC4_PHY_ADDR 0x01 647 #endif 648 649 #ifdef CONFIG_FMAN_ENET 650 #define CONFIG_MII /* MII PHY management */ 651 #define CONFIG_ETHPRIME "FM1@DTSEC3" 652 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 653 #endif 654 655 /* 656 * SATA 657 */ 658 #ifdef CONFIG_FSL_SATA_V2 659 #define CONFIG_LIBATA 660 #define CONFIG_FSL_SATA 661 #define CONFIG_SYS_SATA_MAX_DEVICE 2 662 #define CONFIG_SATA1 663 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 664 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 665 #define CONFIG_SATA2 666 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 667 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 668 #define CONFIG_LBA48 669 #define CONFIG_CMD_SATA 670 #define CONFIG_DOS_PARTITION 671 #endif 672 673 /* 674 * USB 675 */ 676 #ifdef CONFIG_USB_EHCI 677 #define CONFIG_USB_EHCI_FSL 678 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 679 #define CONFIG_HAS_FSL_DR_USB 680 #endif 681 682 /* 683 * SDHC 684 */ 685 #ifdef CONFIG_MMC 686 #define CONFIG_FSL_ESDHC 687 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 688 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 689 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 690 #define CONFIG_GENERIC_MMC 691 #define CONFIG_DOS_PARTITION 692 #endif 693 694 /* 695 * Dynamic MTD Partition support with mtdparts 696 */ 697 #ifndef CONFIG_SYS_NO_FLASH 698 #define CONFIG_MTD_DEVICE 699 #define CONFIG_MTD_PARTITIONS 700 #define CONFIG_CMD_MTDPARTS 701 #define CONFIG_FLASH_CFI_MTD 702 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 703 "spi0=spife110000.1" 704 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 705 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 706 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 707 "1m(uboot),5m(kernel),128k(dtb),-(user)" 708 #endif 709 710 /* 711 * Environment 712 */ 713 714 /* 715 * Command line configuration. 716 */ 717 #define CONFIG_CMD_ERRATA 718 #define CONFIG_CMD_REGINFO 719 720 #ifdef CONFIG_PCI 721 #define CONFIG_CMD_PCI 722 #endif 723 724 /* Hash command with SHA acceleration supported in hardware */ 725 #ifdef CONFIG_FSL_CAAM 726 #define CONFIG_CMD_HASH 727 #define CONFIG_SHA_HW_ACCEL 728 #endif 729 730 /* 731 * Miscellaneous configurable options 732 */ 733 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 734 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 735 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 736 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 737 #ifdef CONFIG_CMD_KGDB 738 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 739 #else 740 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 741 #endif 742 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 743 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 744 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 745 746 /* 747 * For booting Linux, the board info and command line data 748 * have to be in the first 64 MB of memory, since this is 749 * the maximum mapped by the Linux kernel during initialization. 750 */ 751 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 752 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 753 754 #ifdef CONFIG_CMD_KGDB 755 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 756 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 757 #endif 758 759 /* 760 * Environment Configuration 761 */ 762 #define CONFIG_ROOTPATH "/opt/nfsroot" 763 #define CONFIG_BOOTFILE "uImage" 764 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 765 766 /* default location for tftp and bootm */ 767 #define CONFIG_LOADADDR 1000000 768 #define CONFIG_BAUDRATE 115200 769 #define __USB_PHY_TYPE utmi 770 771 #define CONFIG_EXTRA_ENV_SETTINGS \ 772 "hwconfig=fsl_ddr:" \ 773 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 774 "bank_intlv=auto;" \ 775 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 776 "netdev=eth0\0" \ 777 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 778 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 779 "tftpflash=tftpboot $loadaddr $uboot && " \ 780 "protect off $ubootaddr +$filesize && " \ 781 "erase $ubootaddr +$filesize && " \ 782 "cp.b $loadaddr $ubootaddr $filesize && " \ 783 "protect on $ubootaddr +$filesize && " \ 784 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 785 "consoledev=ttyS0\0" \ 786 "ramdiskaddr=2000000\0" \ 787 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 788 "fdtaddr=1e00000\0" \ 789 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 790 "bdev=sda3\0" 791 792 /* 793 * For emulation this causes u-boot to jump to the start of the 794 * proof point app code automatically 795 */ 796 #define CONFIG_PROOF_POINTS \ 797 "setenv bootargs root=/dev/$bdev rw " \ 798 "console=$consoledev,$baudrate $othbootargs;" \ 799 "cpu 1 release 0x29000000 - - -;" \ 800 "cpu 2 release 0x29000000 - - -;" \ 801 "cpu 3 release 0x29000000 - - -;" \ 802 "cpu 4 release 0x29000000 - - -;" \ 803 "cpu 5 release 0x29000000 - - -;" \ 804 "cpu 6 release 0x29000000 - - -;" \ 805 "cpu 7 release 0x29000000 - - -;" \ 806 "go 0x29000000" 807 808 #define CONFIG_HVBOOT \ 809 "setenv bootargs config-addr=0x60000000; " \ 810 "bootm 0x01000000 - 0x00f00000" 811 812 #define CONFIG_ALU \ 813 "setenv bootargs root=/dev/$bdev rw " \ 814 "console=$consoledev,$baudrate $othbootargs;" \ 815 "cpu 1 release 0x01000000 - - -;" \ 816 "cpu 2 release 0x01000000 - - -;" \ 817 "cpu 3 release 0x01000000 - - -;" \ 818 "cpu 4 release 0x01000000 - - -;" \ 819 "cpu 5 release 0x01000000 - - -;" \ 820 "cpu 6 release 0x01000000 - - -;" \ 821 "cpu 7 release 0x01000000 - - -;" \ 822 "go 0x01000000" 823 824 #define CONFIG_LINUX \ 825 "setenv bootargs root=/dev/ram rw " \ 826 "console=$consoledev,$baudrate $othbootargs;" \ 827 "setenv ramdiskaddr 0x02000000;" \ 828 "setenv fdtaddr 0x00c00000;" \ 829 "setenv loadaddr 0x1000000;" \ 830 "bootm $loadaddr $ramdiskaddr $fdtaddr" 831 832 #define CONFIG_HDBOOT \ 833 "setenv bootargs root=/dev/$bdev rw " \ 834 "console=$consoledev,$baudrate $othbootargs;" \ 835 "tftp $loadaddr $bootfile;" \ 836 "tftp $fdtaddr $fdtfile;" \ 837 "bootm $loadaddr - $fdtaddr" 838 839 #define CONFIG_NFSBOOTCOMMAND \ 840 "setenv bootargs root=/dev/nfs rw " \ 841 "nfsroot=$serverip:$rootpath " \ 842 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 843 "console=$consoledev,$baudrate $othbootargs;" \ 844 "tftp $loadaddr $bootfile;" \ 845 "tftp $fdtaddr $fdtfile;" \ 846 "bootm $loadaddr - $fdtaddr" 847 848 #define CONFIG_RAMBOOTCOMMAND \ 849 "setenv bootargs root=/dev/ram rw " \ 850 "console=$consoledev,$baudrate $othbootargs;" \ 851 "tftp $ramdiskaddr $ramdiskfile;" \ 852 "tftp $loadaddr $bootfile;" \ 853 "tftp $fdtaddr $fdtfile;" \ 854 "bootm $loadaddr $ramdiskaddr $fdtaddr" 855 856 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 857 858 #include <asm/fsl_secure_boot.h> 859 860 #endif /* __T2080RDB_H */ 861