1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_OMAP_GPIO 18 #define CONFIG_OMAP_COMMON 19 /* Common ARM Erratas */ 20 #define CONFIG_ARM_ERRATA_454179 21 #define CONFIG_ARM_ERRATA_430973 22 #define CONFIG_ARM_ERRATA_621766 23 24 #define CONFIG_SYS_TEXT_BASE 0x80008000 25 26 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 27 28 #include <asm/arch/cpu.h> /* get chip and board defs */ 29 #include <asm/arch/omap.h> 30 31 /* 32 * Display CPU and Board information 33 */ 34 #define CONFIG_DISPLAY_CPUINFO 35 #define CONFIG_DISPLAY_BOARDINFO 36 37 /* Clock Defines */ 38 #define V_OSCK 26000000 /* Clock output from T2 */ 39 #define V_SCLK (V_OSCK >> 1) 40 41 #define CONFIG_MISC_INIT_R 42 43 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 44 #define CONFIG_SETUP_MEMORY_TAGS 45 #define CONFIG_INITRD_TAG 46 #define CONFIG_REVISION_TAG 47 48 /* 49 * Size of malloc() pool 50 */ 51 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 53 2 * 1024 * 1024) 54 /* 55 * DDR related 56 */ 57 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 58 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 59 60 /* 61 * Hardware drivers 62 */ 63 64 /* 65 * NS16550 Configuration 66 */ 67 #define CONFIG_SYS_NS16550_SERIAL 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 69 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 70 71 /* 72 * select serial console configuration 73 */ 74 #define CONFIG_CONS_INDEX 1 75 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 76 #define CONFIG_SERIAL1 /* UART1 */ 77 78 /* allow to overwrite serial and ethaddr */ 79 #define CONFIG_ENV_OVERWRITE 80 #define CONFIG_BAUDRATE 115200 81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 82 115200} 83 #define CONFIG_MMC 84 #define CONFIG_OMAP_HSMMC 85 #define CONFIG_GENERIC_MMC 86 #define CONFIG_DOS_PARTITION 87 88 /* EHCI */ 89 #define CONFIG_OMAP3_GPIO_5 90 #define CONFIG_USB_EHCI 91 #define CONFIG_USB_EHCI_OMAP 92 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 93 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 94 95 /* commands to include */ 96 #define CONFIG_CMD_NAND /* NAND support */ 97 #define CONFIG_CMD_EEPROM 98 99 #define CONFIG_SYS_NO_FLASH 100 #define CONFIG_SYS_I2C 101 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 102 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 103 #define CONFIG_SYS_I2C_OMAP34XX 104 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 105 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 106 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 107 108 /* 109 * Board NAND Info. 110 */ 111 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 112 /* to access */ 113 /* nand at CS0 */ 114 115 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 116 /* NAND devices */ 117 118 #define CONFIG_AUTO_COMPLETE 119 120 /* 121 * Miscellaneous configurable options 122 */ 123 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 124 #define CONFIG_CMDLINE_EDITING 125 #define CONFIG_AUTO_COMPLETE 126 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 127 128 /* Print Buffer Size */ 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 130 sizeof(CONFIG_SYS_PROMPT) + 16) 131 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 132 /* args */ 133 /* Boot Argument Buffer Size */ 134 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 135 /* memtest works on */ 136 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 137 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 138 0x01F00000) /* 31MB */ 139 140 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 141 /* address */ 142 143 /* 144 * AM3517 has 12 GP timers, they can be driven by the system clock 145 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 146 * This rate is divided by a local divisor. 147 */ 148 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 149 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 150 151 /* 152 * Physical Memory Map 153 */ 154 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 155 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 156 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 157 158 /* 159 * FLASH and environment organization 160 */ 161 162 /* **** PISMO SUPPORT *** */ 163 #define CONFIG_NAND 164 #define CONFIG_NAND_OMAP_GPMC 165 #define CONFIG_ENV_IS_IN_NAND 166 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 167 168 /* Redundant Environment */ 169 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 170 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 171 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 172 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 173 2 * CONFIG_SYS_ENV_SECT_SIZE) 174 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 175 176 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 177 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 178 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 179 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 180 CONFIG_SYS_INIT_RAM_SIZE - \ 181 GENERATED_GBL_DATA_SIZE) 182 183 /* 184 * ethernet support, EMAC 185 * 186 */ 187 #define CONFIG_DRIVER_TI_EMAC 188 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 189 #define CONFIG_MII 190 #define CONFIG_EMAC_MDIO_PHY_NUM 0 191 #define CONFIG_BOOTP_DNS 192 #define CONFIG_BOOTP_DNS2 193 #define CONFIG_BOOTP_SEND_HOSTNAME 194 #define CONFIG_NET_RETRY_COUNT 10 195 196 /* Defines for SPL */ 197 #define CONFIG_SPL_FRAMEWORK 198 #define CONFIG_SPL_BOARD_INIT 199 #define CONFIG_SPL_CONSOLE 200 #define CONFIG_SPL_NAND_SIMPLE 201 #define CONFIG_SPL_NAND_SOFTECC 202 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 203 204 #define CONFIG_SPL_MMC_SUPPORT 205 #define CONFIG_SPL_SERIAL_SUPPORT 206 #define CONFIG_SPL_POWER_SUPPORT 207 #define CONFIG_SPL_NAND_SUPPORT 208 #define CONFIG_SPL_NAND_BASE 209 #define CONFIG_SPL_NAND_DRIVERS 210 #define CONFIG_SPL_NAND_ECC 211 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 212 213 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 214 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 215 CONFIG_SPL_TEXT_BASE) 216 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 217 218 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 219 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 220 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 221 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 222 223 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 224 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 225 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 226 227 /* FAT */ 228 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 229 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 230 231 /* RAW SD card / eMMC */ 232 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 233 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 234 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 235 236 /* NAND boot config */ 237 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 238 #define CONFIG_SYS_NAND_PAGE_COUNT 64 239 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 240 #define CONFIG_SYS_NAND_OOBSIZE 64 241 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 242 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 243 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 244 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 245 48, 49, 50, 51, 52, 53, 54, 55,\ 246 56, 57, 58, 59, 60, 61, 62, 63} 247 #define CONFIG_SYS_NAND_ECCSIZE 256 248 #define CONFIG_SYS_NAND_ECCBYTES 3 249 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 250 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 251 252 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 253 254 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 255 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 256 257 #define CONFIG_CMD_UBI 258 #define CONFIG_CMD_UBIFS 259 #define CONFIG_RBTREE 260 #define CONFIG_LZO 261 #define CONFIG_MTD_PARTITIONS 262 #define CONFIG_MTD_DEVICE 263 #define CONFIG_CMD_MTDPARTS 264 265 /* Setup MTD for NAND on the SOM */ 266 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 267 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 268 "1m(u-boot),256k(env1)," \ 269 "256k(env2),6m(kernel),-(rootfs)" 270 271 #define CONFIG_TAM3517_SETTINGS \ 272 "netdev=eth0\0" \ 273 "nandargs=setenv bootargs root=${nandroot} " \ 274 "rootfstype=${nandrootfstype}\0" \ 275 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 276 "nfsroot=${serverip}:${rootpath}\0" \ 277 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 278 "addip_sta=setenv bootargs ${bootargs} " \ 279 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 280 ":${hostname}:${netdev}:off panic=1\0" \ 281 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 282 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 283 "else run addip_sta;fi\0" \ 284 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 285 "addtty=setenv bootargs ${bootargs}" \ 286 " console=ttyO0,${baudrate}\0" \ 287 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 288 "loadaddr=82000000\0" \ 289 "kernel_addr_r=82000000\0" \ 290 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 291 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 292 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 293 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 294 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 295 "bootm ${kernel_addr}\0" \ 296 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 297 "nand read ${kernel_addr_r} kernel\0" \ 298 "bootm ${kernel_addr_r}\0" \ 299 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 300 "run nfsargs addip addtty addmtd addmisc;" \ 301 "bootm ${kernel_addr_r}\0" \ 302 "net_self=if run net_self_load;then " \ 303 "run ramargs addip addtty addmtd addmisc;" \ 304 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 305 "else echo Images not loades;fi\0" \ 306 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 307 "load=tftp ${loadaddr} ${u-boot}\0" \ 308 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 309 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 310 "uboot_addr=0x80000\0" \ 311 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 312 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 313 "updatemlo=nandecc hw;nand erase 0 20000;" \ 314 "nand write ${loadaddr} 0 20000\0" \ 315 "upd=if run load;then echo Updating u-boot;if run update;" \ 316 "then echo U-Boot updated;" \ 317 "else echo Error updating u-boot !;" \ 318 "echo Board without bootloader !!;" \ 319 "fi;" \ 320 "else echo U-Boot not downloaded..exiting;fi\0" \ 321 322 /* 323 * this is common code for all TAM3517 boards. 324 * MAC address is stored from manufacturer in 325 * I2C EEPROM 326 */ 327 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 328 /* 329 * The I2C EEPROM on the TAM3517 contains 330 * mac address and production data 331 */ 332 struct tam3517_module_info { 333 char customer[48]; 334 char product[48]; 335 336 /* 337 * bit 0~47 : sequence number 338 * bit 48~55 : week of year, from 0. 339 * bit 56~63 : year 340 */ 341 unsigned long long sequence_number; 342 343 /* 344 * bit 0~7 : revision fixed 345 * bit 8~15 : revision major 346 * bit 16~31 : TNxxx 347 */ 348 unsigned int revision; 349 unsigned char eth_addr[4][8]; 350 unsigned char _rev[100]; 351 }; 352 353 #define TAM3517_READ_EEPROM(info, ret) \ 354 do { \ 355 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 356 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 357 (void *)info, sizeof(*info))) \ 358 ret = 1; \ 359 else \ 360 ret = 0; \ 361 } while (0) 362 363 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 364 do { \ 365 char buf[80], ethname[20]; \ 366 int i; \ 367 memset(buf, 0, sizeof(buf)); \ 368 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 369 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 370 (info)->eth_addr[i][5], \ 371 (info)->eth_addr[i][4], \ 372 (info)->eth_addr[i][3], \ 373 (info)->eth_addr[i][2], \ 374 (info)->eth_addr[i][1], \ 375 (info)->eth_addr[i][0]); \ 376 \ 377 if (i) \ 378 sprintf(ethname, "eth%daddr", i); \ 379 else \ 380 strcpy(ethname, "ethaddr"); \ 381 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 382 setenv(ethname, buf); \ 383 } \ 384 } while (0) 385 386 /* The following macros are taken from Technexion's documentation */ 387 #define TAM3517_sequence_number(info) \ 388 ((info)->sequence_number % 0x1000000000000LL) 389 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 390 #define TAM3517_year(info) ((info)->sequence_number >> 56) 391 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 392 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 393 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 394 395 #define TAM3517_PRINT_SOM_INFO(info) \ 396 do { \ 397 printf("Vendor:%s\n", (info)->customer); \ 398 printf("SOM: %s\n", (info)->product); \ 399 printf("SeqNr: %02llu%02llu%012llu\n", \ 400 TAM3517_year(info), \ 401 TAM3517_week_of_year(info), \ 402 TAM3517_sequence_number(info)); \ 403 printf("Rev: TN%u %u.%u\n", \ 404 TAM3517_revision_tn(info), \ 405 TAM3517_revision_major(info), \ 406 TAM3517_revision_fixed(info)); \ 407 } while (0) 408 409 #endif 410 411 #endif /* __TAM3517_H */ 412