1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_BOOKE 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #define CONFIG_E500MC /* BOOKE e500mc family */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 30 #define CONFIG_FSL_IFC /* Enable IFC Support */ 31 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 36 37 /* support deep sleep */ 38 #ifdef CONFIG_PPC_T1024 39 #define CONFIG_DEEP_SLEEP 40 #endif 41 #if defined(CONFIG_DEEP_SLEEP) 42 #define CONFIG_SILENT_CONSOLE 43 #define CONFIG_BOARD_EARLY_INIT_F 44 #endif 45 46 #ifdef CONFIG_RAMBOOT_PBL 47 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 48 #if defined(CONFIG_T1024RDB) 49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg 50 #elif defined(CONFIG_T1023RDB) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg 52 #endif 53 #define CONFIG_SPL_FLUSH_IMAGE 54 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 55 #define CONFIG_FSL_LAW /* Use common FSL init code */ 56 #define CONFIG_SYS_TEXT_BASE 0x30001000 57 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 58 #define CONFIG_SPL_PAD_TO 0x40000 59 #define CONFIG_SPL_MAX_SIZE 0x28000 60 #define RESET_VECTOR_OFFSET 0x27FFC 61 #define BOOT_PAGE_OFFSET 0x27000 62 #ifdef CONFIG_SPL_BUILD 63 #define CONFIG_SPL_SKIP_RELOCATE 64 #define CONFIG_SPL_COMMON_INIT_DDR 65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 66 #define CONFIG_SYS_NO_FLASH 67 #endif 68 69 #ifdef CONFIG_NAND 70 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 71 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 72 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 73 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 75 #define CONFIG_SPL_NAND_BOOT 76 #endif 77 78 #ifdef CONFIG_SPIFLASH 79 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 80 #define CONFIG_SPL_SPI_SUPPORT 81 #define CONFIG_SPL_SPI_FLASH_SUPPORT 82 #define CONFIG_SPL_SPI_FLASH_MINIMAL 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 87 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 88 #ifndef CONFIG_SPL_BUILD 89 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 90 #endif 91 #define CONFIG_SPL_SPI_BOOT 92 #endif 93 94 #ifdef CONFIG_SDCARD 95 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 96 #define CONFIG_SPL_MMC_MINIMAL 97 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 98 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 99 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 100 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 101 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 102 #ifndef CONFIG_SPL_BUILD 103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 104 #endif 105 #define CONFIG_SPL_MMC_BOOT 106 #endif 107 108 #endif /* CONFIG_RAMBOOT_PBL */ 109 110 #ifndef CONFIG_SYS_TEXT_BASE 111 #define CONFIG_SYS_TEXT_BASE 0xeff40000 112 #endif 113 114 #ifndef CONFIG_RESET_VECTOR_ADDRESS 115 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 116 #endif 117 118 #ifndef CONFIG_SYS_NO_FLASH 119 #define CONFIG_FLASH_CFI_DRIVER 120 #define CONFIG_SYS_FLASH_CFI 121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 122 #endif 123 124 /* PCIe Boot - Master */ 125 #define CONFIG_SRIO_PCIE_BOOT_MASTER 126 /* 127 * for slave u-boot IMAGE instored in master memory space, 128 * PHYS must be aligned based on the SIZE 129 */ 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 132 #ifdef CONFIG_PHYS_64BIT 133 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 135 #else 136 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 138 #endif 139 /* 140 * for slave UCODE and ENV instored in master memory space, 141 * PHYS must be aligned based on the SIZE 142 */ 143 #ifdef CONFIG_PHYS_64BIT 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 145 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 146 #else 147 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 149 #endif 150 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 151 /* slave core release by master*/ 152 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 153 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 154 155 /* PCIe Boot - Slave */ 156 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 157 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 158 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 159 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 160 /* Set 1M boot space for PCIe boot */ 161 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 162 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 163 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 164 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 165 #define CONFIG_SYS_NO_FLASH 166 #endif 167 168 #if defined(CONFIG_SPIFLASH) 169 #define CONFIG_SYS_EXTRA_ENV_RELOC 170 #define CONFIG_ENV_IS_IN_SPI_FLASH 171 #define CONFIG_ENV_SPI_BUS 0 172 #define CONFIG_ENV_SPI_CS 0 173 #define CONFIG_ENV_SPI_MAX_HZ 10000000 174 #define CONFIG_ENV_SPI_MODE 0 175 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 176 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 177 #if defined(CONFIG_T1024RDB) 178 #define CONFIG_ENV_SECT_SIZE 0x10000 179 #elif defined(CONFIG_T1023RDB) 180 #define CONFIG_ENV_SECT_SIZE 0x40000 181 #endif 182 #elif defined(CONFIG_SDCARD) 183 #define CONFIG_SYS_EXTRA_ENV_RELOC 184 #define CONFIG_ENV_IS_IN_MMC 185 #define CONFIG_SYS_MMC_ENV_DEV 0 186 #define CONFIG_ENV_SIZE 0x2000 187 #define CONFIG_ENV_OFFSET (512 * 0x800) 188 #elif defined(CONFIG_NAND) 189 #define CONFIG_SYS_EXTRA_ENV_RELOC 190 #define CONFIG_ENV_IS_IN_NAND 191 #define CONFIG_ENV_SIZE 0x2000 192 #if defined(CONFIG_T1024RDB) 193 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 194 #elif defined(CONFIG_T1023RDB) 195 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 196 #endif 197 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 198 #define CONFIG_ENV_IS_IN_REMOTE 199 #define CONFIG_ENV_ADDR 0xffe20000 200 #define CONFIG_ENV_SIZE 0x2000 201 #elif defined(CONFIG_ENV_IS_NOWHERE) 202 #define CONFIG_ENV_SIZE 0x2000 203 #else 204 #define CONFIG_ENV_IS_IN_FLASH 205 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 206 #define CONFIG_ENV_SIZE 0x2000 207 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 208 #endif 209 210 #ifndef __ASSEMBLY__ 211 unsigned long get_board_sys_clk(void); 212 unsigned long get_board_ddr_clk(void); 213 #endif 214 215 #define CONFIG_SYS_CLK_FREQ 100000000 216 #define CONFIG_DDR_CLK_FREQ 100000000 217 218 /* 219 * These can be toggled for performance analysis, otherwise use default. 220 */ 221 #define CONFIG_SYS_CACHE_STASHING 222 #define CONFIG_BACKSIDE_L2_CACHE 223 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 224 #define CONFIG_BTB /* toggle branch predition */ 225 #define CONFIG_DDR_ECC 226 #ifdef CONFIG_DDR_ECC 227 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 228 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 229 #endif 230 231 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 232 #define CONFIG_SYS_MEMTEST_END 0x00400000 233 #define CONFIG_SYS_ALT_MEMTEST 234 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 235 236 /* 237 * Config the L3 Cache as L3 SRAM 238 */ 239 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 240 #define CONFIG_SYS_L3_SIZE (256 << 10) 241 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 242 #ifdef CONFIG_RAMBOOT_PBL 243 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 244 #endif 245 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 246 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 247 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 248 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 249 250 #ifdef CONFIG_PHYS_64BIT 251 #define CONFIG_SYS_DCSRBAR 0xf0000000 252 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 253 #endif 254 255 /* EEPROM */ 256 #define CONFIG_ID_EEPROM 257 #define CONFIG_SYS_I2C_EEPROM_NXID 258 #define CONFIG_SYS_EEPROM_BUS_NUM 0 259 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 260 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 261 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 263 264 /* 265 * DDR Setup 266 */ 267 #define CONFIG_VERY_BIG_RAM 268 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 269 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 270 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 271 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 272 #define CONFIG_FSL_DDR_INTERACTIVE 273 #if defined(CONFIG_T1024RDB) 274 #define CONFIG_DDR_SPD 275 #define CONFIG_SYS_FSL_DDR3 276 #define CONFIG_SYS_SPD_BUS_NUM 0 277 #define SPD_EEPROM_ADDRESS 0x51 278 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 279 #elif defined(CONFIG_T1023RDB) 280 #define CONFIG_SYS_FSL_DDR4 281 #define CONFIG_SYS_DDR_RAW_TIMING 282 #define CONFIG_SYS_SDRAM_SIZE 2048 283 #endif 284 285 /* 286 * IFC Definitions 287 */ 288 #define CONFIG_SYS_FLASH_BASE 0xe8000000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 291 #else 292 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 293 #endif 294 295 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 296 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 297 CSPR_PORT_SIZE_16 | \ 298 CSPR_MSEL_NOR | \ 299 CSPR_V) 300 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 301 302 /* NOR Flash Timing Params */ 303 #if defined(CONFIG_T1024RDB) 304 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 305 #elif defined(CONFIG_T1023RDB) 306 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 307 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 308 #endif 309 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 310 FTIM0_NOR_TEADC(0x5) | \ 311 FTIM0_NOR_TEAHC(0x5)) 312 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 313 FTIM1_NOR_TRAD_NOR(0x1A) |\ 314 FTIM1_NOR_TSEQRAD_NOR(0x13)) 315 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 316 FTIM2_NOR_TCH(0x4) | \ 317 FTIM2_NOR_TWPH(0x0E) | \ 318 FTIM2_NOR_TWP(0x1c)) 319 #define CONFIG_SYS_NOR_FTIM3 0x0 320 321 #define CONFIG_SYS_FLASH_QUIET_TEST 322 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 323 324 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 325 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 326 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 327 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 328 329 #define CONFIG_SYS_FLASH_EMPTY_INFO 330 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 331 332 #ifdef CONFIG_T1024RDB 333 /* CPLD on IFC */ 334 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 335 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 336 #define CONFIG_SYS_CSPR2_EXT (0xf) 337 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 338 | CSPR_PORT_SIZE_8 \ 339 | CSPR_MSEL_GPCM \ 340 | CSPR_V) 341 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 342 #define CONFIG_SYS_CSOR2 0x0 343 344 /* CPLD Timing parameters for IFC CS2 */ 345 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 346 FTIM0_GPCM_TEADC(0x0e) | \ 347 FTIM0_GPCM_TEAHC(0x0e)) 348 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 349 FTIM1_GPCM_TRAD(0x1f)) 350 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 351 FTIM2_GPCM_TCH(0x8) | \ 352 FTIM2_GPCM_TWP(0x1f)) 353 #define CONFIG_SYS_CS2_FTIM3 0x0 354 #endif 355 356 /* NAND Flash on IFC */ 357 #define CONFIG_NAND_FSL_IFC 358 #define CONFIG_SYS_NAND_BASE 0xff800000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 361 #else 362 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 363 #endif 364 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 365 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 366 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 367 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 368 | CSPR_V) 369 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 370 371 #if defined(CONFIG_T1024RDB) 372 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 373 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 374 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 375 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 376 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 377 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 378 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 379 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 380 #elif defined(CONFIG_T1023RDB) 381 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 382 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 383 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 384 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 385 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 386 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 387 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 388 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 389 #endif 390 391 #define CONFIG_SYS_NAND_ONFI_DETECTION 392 /* ONFI NAND Flash mode0 Timing Params */ 393 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 394 FTIM0_NAND_TWP(0x18) | \ 395 FTIM0_NAND_TWCHT(0x07) | \ 396 FTIM0_NAND_TWH(0x0a)) 397 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 398 FTIM1_NAND_TWBE(0x39) | \ 399 FTIM1_NAND_TRR(0x0e) | \ 400 FTIM1_NAND_TRP(0x18)) 401 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 402 FTIM2_NAND_TREH(0x0a) | \ 403 FTIM2_NAND_TWHRE(0x1e)) 404 #define CONFIG_SYS_NAND_FTIM3 0x0 405 406 #define CONFIG_SYS_NAND_DDR_LAW 11 407 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 408 #define CONFIG_SYS_MAX_NAND_DEVICE 1 409 #define CONFIG_CMD_NAND 410 411 #if defined(CONFIG_NAND) 412 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 413 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 414 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 415 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 416 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 417 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 418 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 419 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 420 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 421 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 422 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 423 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 424 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 425 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 426 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 427 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 428 #else 429 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 430 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 431 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 432 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 433 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 434 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 435 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 436 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 437 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 438 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 439 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 440 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 441 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 442 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 443 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 444 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 445 #endif 446 447 #ifdef CONFIG_SPL_BUILD 448 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 449 #else 450 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 451 #endif 452 453 #if defined(CONFIG_RAMBOOT_PBL) 454 #define CONFIG_SYS_RAMBOOT 455 #endif 456 457 #define CONFIG_BOARD_EARLY_INIT_R 458 #define CONFIG_MISC_INIT_R 459 460 #define CONFIG_HWCONFIG 461 462 /* define to use L1 as initial stack */ 463 #define CONFIG_L1_INIT_RAM 464 #define CONFIG_SYS_INIT_RAM_LOCK 465 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 466 #ifdef CONFIG_PHYS_64BIT 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 469 /* The assembler doesn't like typecast */ 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 471 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 472 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 473 #else 474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 477 #endif 478 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 479 480 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 481 GENERATED_GBL_DATA_SIZE) 482 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 483 484 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 485 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 486 487 /* Serial Port */ 488 #define CONFIG_CONS_INDEX 1 489 #define CONFIG_SYS_NS16550_SERIAL 490 #define CONFIG_SYS_NS16550_REG_SIZE 1 491 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 492 493 #define CONFIG_SYS_BAUDRATE_TABLE \ 494 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 495 496 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 497 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 498 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 499 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 500 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 501 502 /* Video */ 503 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 504 #ifdef CONFIG_FSL_DIU_FB 505 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 506 #define CONFIG_VIDEO 507 #define CONFIG_CMD_BMP 508 #define CONFIG_CFB_CONSOLE 509 #define CONFIG_VIDEO_SW_CURSOR 510 #define CONFIG_VGA_AS_SINGLE_DEVICE 511 #define CONFIG_VIDEO_LOGO 512 #define CONFIG_VIDEO_BMP_LOGO 513 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 514 /* 515 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 516 * disable empty flash sector detection, which is I/O-intensive. 517 */ 518 #undef CONFIG_SYS_FLASH_EMPTY_INFO 519 #endif 520 521 /* I2C */ 522 #define CONFIG_SYS_I2C 523 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 524 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 525 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 526 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 527 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 528 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 529 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 530 531 #define I2C_PCA6408_BUS_NUM 1 532 #define I2C_PCA6408_ADDR 0x20 533 534 /* I2C bus multiplexer */ 535 #define I2C_MUX_CH_DEFAULT 0x8 536 537 /* 538 * RTC configuration 539 */ 540 #define RTC 541 #define CONFIG_RTC_DS1337 1 542 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 543 544 /* 545 * eSPI - Enhanced SPI 546 */ 547 #define CONFIG_SPI_FLASH_BAR 548 #define CONFIG_SF_DEFAULT_SPEED 10000000 549 #define CONFIG_SF_DEFAULT_MODE 0 550 551 /* 552 * General PCIe 553 * Memory space is mapped 1-1, but I/O space must start from 0. 554 */ 555 #define CONFIG_PCI /* Enable PCI/PCIE */ 556 #define CONFIG_PCIE1 /* PCIE controller 1 */ 557 #define CONFIG_PCIE2 /* PCIE controller 2 */ 558 #define CONFIG_PCIE3 /* PCIE controller 3 */ 559 #ifdef CONFIG_PPC_T1040 560 #define CONFIG_PCIE4 /* PCIE controller 4 */ 561 #endif 562 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 563 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 564 #define CONFIG_PCI_INDIRECT_BRIDGE 565 566 #ifdef CONFIG_PCI 567 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 568 #ifdef CONFIG_PCIE1 569 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 570 #ifdef CONFIG_PHYS_64BIT 571 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 572 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 573 #else 574 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 575 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 576 #endif 577 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 578 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 579 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 582 #else 583 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 584 #endif 585 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 586 #endif 587 588 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 589 #ifdef CONFIG_PCIE2 590 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 591 #ifdef CONFIG_PHYS_64BIT 592 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 593 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 594 #else 595 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 596 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 597 #endif 598 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 599 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 600 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 601 #ifdef CONFIG_PHYS_64BIT 602 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 603 #else 604 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 605 #endif 606 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 607 #endif 608 609 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 610 #ifdef CONFIG_PCIE3 611 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 612 #ifdef CONFIG_PHYS_64BIT 613 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 614 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 615 #else 616 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 617 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 618 #endif 619 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 620 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 621 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 622 #ifdef CONFIG_PHYS_64BIT 623 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 624 #else 625 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 626 #endif 627 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 628 #endif 629 630 /* controller 4, Base address 203000, to be removed */ 631 #ifdef CONFIG_PCIE4 632 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 633 #ifdef CONFIG_PHYS_64BIT 634 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 635 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 636 #else 637 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 638 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 639 #endif 640 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 641 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 642 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 643 #ifdef CONFIG_PHYS_64BIT 644 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 645 #else 646 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 647 #endif 648 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 649 #endif 650 651 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 652 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 653 #define CONFIG_DOS_PARTITION 654 #endif /* CONFIG_PCI */ 655 656 /* 657 * USB 658 */ 659 #define CONFIG_HAS_FSL_DR_USB 660 661 #ifdef CONFIG_HAS_FSL_DR_USB 662 #define CONFIG_USB_EHCI 663 #define CONFIG_USB_EHCI_FSL 664 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 665 #endif 666 667 /* 668 * SDHC 669 */ 670 #define CONFIG_MMC 671 #ifdef CONFIG_MMC 672 #define CONFIG_FSL_ESDHC 673 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 674 #define CONFIG_GENERIC_MMC 675 #define CONFIG_DOS_PARTITION 676 #endif 677 678 /* Qman/Bman */ 679 #ifndef CONFIG_NOBQFMAN 680 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 681 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 682 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 683 #ifdef CONFIG_PHYS_64BIT 684 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 685 #else 686 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 687 #endif 688 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 689 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 690 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 691 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 692 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 693 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 694 CONFIG_SYS_BMAN_CENA_SIZE) 695 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 696 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 697 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 698 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 699 #ifdef CONFIG_PHYS_64BIT 700 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 701 #else 702 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 703 #endif 704 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 705 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 706 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 707 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 708 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 709 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 710 CONFIG_SYS_QMAN_CENA_SIZE) 711 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 712 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 713 714 #define CONFIG_SYS_DPAA_FMAN 715 716 #ifdef CONFIG_T1024RDB 717 #define CONFIG_QE 718 #define CONFIG_U_QE 719 #endif 720 /* Default address of microcode for the Linux FMan driver */ 721 #if defined(CONFIG_SPIFLASH) 722 /* 723 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 724 * env, so we got 0x110000. 725 */ 726 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 727 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 728 #define CONFIG_SYS_QE_FW_ADDR 0x130000 729 #elif defined(CONFIG_SDCARD) 730 /* 731 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 732 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 733 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 734 */ 735 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 736 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 737 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 738 #elif defined(CONFIG_NAND) 739 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 740 #if defined(CONFIG_T1024RDB) 741 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 742 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 743 #elif defined(CONFIG_T1023RDB) 744 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 745 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 746 #endif 747 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 748 /* 749 * Slave has no ucode locally, it can fetch this from remote. When implementing 750 * in two corenet boards, slave's ucode could be stored in master's memory 751 * space, the address can be mapped from slave TLB->slave LAW-> 752 * slave SRIO or PCIE outbound window->master inbound window-> 753 * master LAW->the ucode address in master's memory space. 754 */ 755 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 756 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 757 #else 758 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 759 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 760 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 761 #endif 762 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 763 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 764 #endif /* CONFIG_NOBQFMAN */ 765 766 #ifdef CONFIG_SYS_DPAA_FMAN 767 #define CONFIG_FMAN_ENET 768 #define CONFIG_PHYLIB_10G 769 #define CONFIG_PHY_REALTEK 770 #define CONFIG_PHY_AQUANTIA 771 #if defined(CONFIG_T1024RDB) 772 #define RGMII_PHY1_ADDR 0x2 773 #define RGMII_PHY2_ADDR 0x6 774 #define SGMII_AQR_PHY_ADDR 0x2 775 #define FM1_10GEC1_PHY_ADDR 0x1 776 #elif defined(CONFIG_T1023RDB) 777 #define RGMII_PHY1_ADDR 0x1 778 #define SGMII_RTK_PHY_ADDR 0x3 779 #define SGMII_AQR_PHY_ADDR 0x2 780 #endif 781 #endif 782 783 #ifdef CONFIG_FMAN_ENET 784 #define CONFIG_MII /* MII PHY management */ 785 #define CONFIG_ETHPRIME "FM1@DTSEC4" 786 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 787 #endif 788 789 /* 790 * Dynamic MTD Partition support with mtdparts 791 */ 792 #ifndef CONFIG_SYS_NO_FLASH 793 #define CONFIG_MTD_DEVICE 794 #define CONFIG_MTD_PARTITIONS 795 #define CONFIG_CMD_MTDPARTS 796 #define CONFIG_FLASH_CFI_MTD 797 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 798 "spi0=spife110000.1" 799 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 800 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 801 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 802 "1m(uboot),5m(kernel),128k(dtb),-(user)" 803 #endif 804 805 /* 806 * Environment 807 */ 808 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 809 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 810 811 /* 812 * Command line configuration. 813 */ 814 #define CONFIG_CMD_DATE 815 #define CONFIG_CMD_EEPROM 816 #define CONFIG_CMD_ERRATA 817 #define CONFIG_CMD_IRQ 818 #define CONFIG_CMD_REGINFO 819 820 #ifdef CONFIG_PCI 821 #define CONFIG_CMD_PCI 822 #endif 823 824 /* 825 * Miscellaneous configurable options 826 */ 827 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 828 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 829 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 830 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 831 #ifdef CONFIG_CMD_KGDB 832 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 833 #else 834 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 835 #endif 836 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 837 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 838 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 839 840 /* 841 * For booting Linux, the board info and command line data 842 * have to be in the first 64 MB of memory, since this is 843 * the maximum mapped by the Linux kernel during initialization. 844 */ 845 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 846 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 847 848 #ifdef CONFIG_CMD_KGDB 849 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 850 #endif 851 852 /* 853 * Environment Configuration 854 */ 855 #define CONFIG_ROOTPATH "/opt/nfsroot" 856 #define CONFIG_BOOTFILE "uImage" 857 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 858 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 859 #define CONFIG_BAUDRATE 115200 860 #define __USB_PHY_TYPE utmi 861 862 #ifdef CONFIG_PPC_T1024 863 #define CONFIG_BOARDNAME t1024rdb 864 #define BANK_INTLV cs0_cs1 865 #else 866 #define CONFIG_BOARDNAME t1023rdb 867 #define BANK_INTLV null 868 #endif 869 870 #define CONFIG_EXTRA_ENV_SETTINGS \ 871 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 872 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 873 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 874 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 875 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 876 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 877 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 878 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 879 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 880 "netdev=eth0\0" \ 881 "tftpflash=tftpboot $loadaddr $uboot && " \ 882 "protect off $ubootaddr +$filesize && " \ 883 "erase $ubootaddr +$filesize && " \ 884 "cp.b $loadaddr $ubootaddr $filesize && " \ 885 "protect on $ubootaddr +$filesize && " \ 886 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 887 "consoledev=ttyS0\0" \ 888 "ramdiskaddr=2000000\0" \ 889 "fdtaddr=1e00000\0" \ 890 "bdev=sda3\0" 891 892 #define CONFIG_LINUX \ 893 "setenv bootargs root=/dev/ram rw " \ 894 "console=$consoledev,$baudrate $othbootargs;" \ 895 "setenv ramdiskaddr 0x02000000;" \ 896 "setenv fdtaddr 0x00c00000;" \ 897 "setenv loadaddr 0x1000000;" \ 898 "bootm $loadaddr $ramdiskaddr $fdtaddr" 899 900 #define CONFIG_NFSBOOTCOMMAND \ 901 "setenv bootargs root=/dev/nfs rw " \ 902 "nfsroot=$serverip:$rootpath " \ 903 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 904 "console=$consoledev,$baudrate $othbootargs;" \ 905 "tftp $loadaddr $bootfile;" \ 906 "tftp $fdtaddr $fdtfile;" \ 907 "bootm $loadaddr - $fdtaddr" 908 909 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 910 911 /* Hash command with SHA acceleration supported in hardware */ 912 #ifdef CONFIG_FSL_CAAM 913 #define CONFIG_CMD_HASH 914 #define CONFIG_SHA_HW_ACCEL 915 #endif 916 917 #include <asm/fsl_secure_boot.h> 918 919 #endif /* __T1024RDB_H */ 920