1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 24 #define CONFIG_DEEP_SLEEP 25 #if defined(CONFIG_DEEP_SLEEP) 26 #define CONFIG_SILENT_CONSOLE 27 #endif 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 33 34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 36 37 /* 38 * Generic Timer Definitions 39 */ 40 #define GENERIC_TIMER_CLK 12500000 41 42 #ifndef __ASSEMBLY__ 43 unsigned long get_board_sys_clk(void); 44 unsigned long get_board_ddr_clk(void); 45 #endif 46 47 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 48 #define CONFIG_SYS_CLK_FREQ 100000000 49 #define CONFIG_DDR_CLK_FREQ 100000000 50 #define CONFIG_QIXIS_I2C_ACCESS 51 #else 52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 53 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 54 #endif 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 #define CONFIG_SPL_FRAMEWORK 69 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 70 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 71 #define CONFIG_SPL_WATCHDOG_SUPPORT 72 #define CONFIG_SPL_SERIAL_SUPPORT 73 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 74 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 75 76 #define CONFIG_SPL_TEXT_BASE 0x10000000 77 #define CONFIG_SPL_MAX_SIZE 0x1a000 78 #define CONFIG_SPL_STACK 0x1001d000 79 #define CONFIG_SPL_PAD_TO 0x1c000 80 #define CONFIG_SYS_TEXT_BASE 0x82000000 81 82 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 83 CONFIG_SYS_MONITOR_LEN) 84 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 85 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 86 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 87 #define CONFIG_SYS_MONITOR_LEN 0xc0000 88 #endif 89 90 #ifdef CONFIG_QSPI_BOOT 91 #define CONFIG_SYS_TEXT_BASE 0x40010000 92 #endif 93 94 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 95 #define CONFIG_SYS_NO_FLASH 96 #endif 97 98 #ifdef CONFIG_NAND_BOOT 99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 100 #define CONFIG_SPL_FRAMEWORK 101 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 102 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 103 #define CONFIG_SPL_WATCHDOG_SUPPORT 104 #define CONFIG_SPL_SERIAL_SUPPORT 105 #define CONFIG_SPL_NAND_SUPPORT 106 107 #define CONFIG_SPL_TEXT_BASE 0x10000000 108 #define CONFIG_SPL_MAX_SIZE 0x1a000 109 #define CONFIG_SPL_STACK 0x1001d000 110 #define CONFIG_SPL_PAD_TO 0x1c000 111 #define CONFIG_SYS_TEXT_BASE 0x82000000 112 113 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 114 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 115 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 116 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 117 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 118 119 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 120 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 121 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 122 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 123 #define CONFIG_SYS_MONITOR_LEN 0x80000 124 #endif 125 126 #ifndef CONFIG_SYS_TEXT_BASE 127 #define CONFIG_SYS_TEXT_BASE 0x60100000 128 #endif 129 130 #define CONFIG_NR_DRAM_BANKS 1 131 132 #define CONFIG_DDR_SPD 133 #define SPD_EEPROM_ADDRESS 0x51 134 #define CONFIG_SYS_SPD_BUS_NUM 0 135 136 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 137 #ifndef CONFIG_SYS_FSL_DDR4 138 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 139 #define CONFIG_SYS_DDR_RAW_TIMING 140 #endif 141 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 142 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 143 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 #define CONFIG_DDR_ECC 148 #ifdef CONFIG_DDR_ECC 149 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 150 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 151 #endif 152 153 #define CONFIG_SYS_HAS_SERDES 154 155 #define CONFIG_FSL_CAAM /* Enable CAAM */ 156 157 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 158 !defined(CONFIG_QSPI_BOOT) 159 #define CONFIG_U_QE 160 #endif 161 162 /* 163 * IFC Definitions 164 */ 165 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 166 #define CONFIG_FSL_IFC 167 #define CONFIG_SYS_FLASH_BASE 0x60000000 168 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 169 170 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 171 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 172 CSPR_PORT_SIZE_16 | \ 173 CSPR_MSEL_NOR | \ 174 CSPR_V) 175 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 176 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 177 + 0x8000000) | \ 178 CSPR_PORT_SIZE_16 | \ 179 CSPR_MSEL_NOR | \ 180 CSPR_V) 181 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 182 183 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 184 CSOR_NOR_TRHZ_80) 185 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 186 FTIM0_NOR_TEADC(0x5) | \ 187 FTIM0_NOR_TEAHC(0x5)) 188 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 189 FTIM1_NOR_TRAD_NOR(0x1a) | \ 190 FTIM1_NOR_TSEQRAD_NOR(0x13)) 191 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 192 FTIM2_NOR_TCH(0x4) | \ 193 FTIM2_NOR_TWPH(0xe) | \ 194 FTIM2_NOR_TWP(0x1c)) 195 #define CONFIG_SYS_NOR_FTIM3 0 196 197 #define CONFIG_FLASH_CFI_DRIVER 198 #define CONFIG_SYS_FLASH_CFI 199 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 200 #define CONFIG_SYS_FLASH_QUIET_TEST 201 #define CONFIG_FLASH_SHOW_PROGRESS 45 202 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 203 #define CONFIG_SYS_WRITE_SWAPPED_DATA 204 205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 209 210 #define CONFIG_SYS_FLASH_EMPTY_INFO 211 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 212 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 213 214 /* 215 * NAND Flash Definitions 216 */ 217 #define CONFIG_NAND_FSL_IFC 218 219 #define CONFIG_SYS_NAND_BASE 0x7e800000 220 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 221 222 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 223 224 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 225 | CSPR_PORT_SIZE_8 \ 226 | CSPR_MSEL_NAND \ 227 | CSPR_V) 228 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 229 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 230 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 231 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 232 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 233 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 234 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 235 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 236 237 #define CONFIG_SYS_NAND_ONFI_DETECTION 238 239 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 240 FTIM0_NAND_TWP(0x18) | \ 241 FTIM0_NAND_TWCHT(0x7) | \ 242 FTIM0_NAND_TWH(0xa)) 243 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 244 FTIM1_NAND_TWBE(0x39) | \ 245 FTIM1_NAND_TRR(0xe) | \ 246 FTIM1_NAND_TRP(0x18)) 247 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 248 FTIM2_NAND_TREH(0xa) | \ 249 FTIM2_NAND_TWHRE(0x1e)) 250 #define CONFIG_SYS_NAND_FTIM3 0x0 251 252 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 253 #define CONFIG_SYS_MAX_NAND_DEVICE 1 254 #define CONFIG_CMD_NAND 255 256 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 257 #endif 258 259 /* 260 * QIXIS Definitions 261 */ 262 #define CONFIG_FSL_QIXIS 263 264 #ifdef CONFIG_FSL_QIXIS 265 #define QIXIS_BASE 0x7fb00000 266 #define QIXIS_BASE_PHYS QIXIS_BASE 267 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 268 #define QIXIS_LBMAP_SWITCH 6 269 #define QIXIS_LBMAP_MASK 0x0f 270 #define QIXIS_LBMAP_SHIFT 0 271 #define QIXIS_LBMAP_DFLTBANK 0x00 272 #define QIXIS_LBMAP_ALTBANK 0x04 273 #define QIXIS_PWR_CTL 0x21 274 #define QIXIS_PWR_CTL_POWEROFF 0x80 275 #define QIXIS_RST_CTL_RESET 0x44 276 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 277 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 278 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 279 280 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 281 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 282 CSPR_PORT_SIZE_8 | \ 283 CSPR_MSEL_GPCM | \ 284 CSPR_V) 285 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 286 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 287 CSOR_NOR_NOR_MODE_AVD_NOR | \ 288 CSOR_NOR_TRHZ_80) 289 290 /* 291 * QIXIS Timing parameters for IFC GPCM 292 */ 293 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 294 FTIM0_GPCM_TEADC(0xe) | \ 295 FTIM0_GPCM_TEAHC(0xe)) 296 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 297 FTIM1_GPCM_TRAD(0x1f)) 298 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 299 FTIM2_GPCM_TCH(0xe) | \ 300 FTIM2_GPCM_TWP(0xf0)) 301 #define CONFIG_SYS_FPGA_FTIM3 0x0 302 #endif 303 304 #if defined(CONFIG_NAND_BOOT) 305 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 306 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 307 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 308 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 309 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 310 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 311 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 312 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 313 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 314 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 315 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 316 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 317 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 318 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 319 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 320 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 321 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 322 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 323 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 324 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 325 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 326 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 327 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 328 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 329 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 330 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 331 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 332 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 333 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 334 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 335 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 336 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 337 #else 338 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 339 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 340 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 341 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 342 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 343 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 344 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 345 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 346 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 347 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 348 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 349 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 350 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 351 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 352 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 353 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 354 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 355 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 356 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 357 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 358 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 359 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 360 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 361 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 362 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 363 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 364 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 365 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 366 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 367 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 368 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 369 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 370 #endif 371 372 /* 373 * Serial Port 374 */ 375 #ifdef CONFIG_LPUART 376 #define CONFIG_LPUART_32B_REG 377 #else 378 #define CONFIG_CONS_INDEX 1 379 #define CONFIG_SYS_NS16550_SERIAL 380 #ifndef CONFIG_DM_SERIAL 381 #define CONFIG_SYS_NS16550_REG_SIZE 1 382 #endif 383 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 384 #endif 385 386 #define CONFIG_BAUDRATE 115200 387 388 /* 389 * I2C 390 */ 391 #define CONFIG_SYS_I2C 392 #define CONFIG_SYS_I2C_MXC 393 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 394 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 395 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 396 397 /* 398 * I2C bus multiplexer 399 */ 400 #define I2C_MUX_PCA_ADDR_PRI 0x77 401 #define I2C_MUX_CH_DEFAULT 0x8 402 #define I2C_MUX_CH_CH7301 0xC 403 404 /* 405 * MMC 406 */ 407 #define CONFIG_MMC 408 #define CONFIG_FSL_ESDHC 409 #define CONFIG_GENERIC_MMC 410 411 #define CONFIG_DOS_PARTITION 412 413 /* SPI */ 414 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 415 /* QSPI */ 416 #define QSPI0_AMBA_BASE 0x40000000 417 #define FSL_QSPI_FLASH_SIZE (1 << 24) 418 #define FSL_QSPI_FLASH_NUM 2 419 420 /* DSPI */ 421 422 /* DM SPI */ 423 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 424 #define CONFIG_DM_SPI_FLASH 425 #define CONFIG_SPI_FLASH_DATAFLASH 426 #endif 427 #endif 428 429 /* 430 * USB 431 */ 432 /* EHCI Support - disbaled by default */ 433 /*#define CONFIG_HAS_FSL_DR_USB*/ 434 435 #ifdef CONFIG_HAS_FSL_DR_USB 436 #define CONFIG_USB_EHCI 437 #define CONFIG_USB_EHCI_FSL 438 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 439 #endif 440 441 /*XHCI Support - enabled by default*/ 442 #define CONFIG_HAS_FSL_XHCI_USB 443 444 #ifdef CONFIG_HAS_FSL_XHCI_USB 445 #define CONFIG_USB_XHCI_FSL 446 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 447 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 448 #endif 449 450 /* 451 * Video 452 */ 453 #define CONFIG_FSL_DCU_FB 454 455 #ifdef CONFIG_FSL_DCU_FB 456 #define CONFIG_VIDEO 457 #define CONFIG_CMD_BMP 458 #define CONFIG_CFB_CONSOLE 459 #define CONFIG_VGA_AS_SINGLE_DEVICE 460 #define CONFIG_VIDEO_LOGO 461 #define CONFIG_VIDEO_BMP_LOGO 462 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 463 464 #define CONFIG_FSL_DIU_CH7301 465 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 466 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 467 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 468 #endif 469 470 /* 471 * eTSEC 472 */ 473 #define CONFIG_TSEC_ENET 474 475 #ifdef CONFIG_TSEC_ENET 476 #define CONFIG_MII 477 #define CONFIG_MII_DEFAULT_TSEC 3 478 #define CONFIG_TSEC1 1 479 #define CONFIG_TSEC1_NAME "eTSEC1" 480 #define CONFIG_TSEC2 1 481 #define CONFIG_TSEC2_NAME "eTSEC2" 482 #define CONFIG_TSEC3 1 483 #define CONFIG_TSEC3_NAME "eTSEC3" 484 485 #define TSEC1_PHY_ADDR 1 486 #define TSEC2_PHY_ADDR 2 487 #define TSEC3_PHY_ADDR 3 488 489 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 490 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 491 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 492 493 #define TSEC1_PHYIDX 0 494 #define TSEC2_PHYIDX 0 495 #define TSEC3_PHYIDX 0 496 497 #define CONFIG_ETHPRIME "eTSEC1" 498 499 #define CONFIG_PHY_GIGE 500 #define CONFIG_PHYLIB 501 #define CONFIG_PHY_REALTEK 502 503 #define CONFIG_HAS_ETH0 504 #define CONFIG_HAS_ETH1 505 #define CONFIG_HAS_ETH2 506 507 #define CONFIG_FSL_SGMII_RISER 1 508 #define SGMII_RISER_PHY_OFFSET 0x1b 509 510 #ifdef CONFIG_FSL_SGMII_RISER 511 #define CONFIG_SYS_TBIPA_VALUE 8 512 #endif 513 514 #endif 515 516 /* PCIe */ 517 #define CONFIG_PCI /* Enable PCI/PCIE */ 518 #define CONFIG_PCIE1 /* PCIE controller 1 */ 519 #define CONFIG_PCIE2 /* PCIE controller 2 */ 520 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 521 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 522 523 #define CONFIG_SYS_PCI_64BIT 524 525 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 526 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 527 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 528 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 529 530 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 531 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 532 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 533 534 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 535 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 536 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 537 538 #ifdef CONFIG_PCI 539 #define CONFIG_PCI_PNP 540 #define CONFIG_PCI_SCAN_SHOW 541 #define CONFIG_CMD_PCI 542 #endif 543 544 #define CONFIG_CMDLINE_TAG 545 #define CONFIG_CMDLINE_EDITING 546 547 #define CONFIG_ARMV7_NONSEC 548 #define CONFIG_ARMV7_VIRT 549 #define CONFIG_PEN_ADDR_BIG_ENDIAN 550 #define CONFIG_LAYERSCAPE_NS_ACCESS 551 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 552 #define CONFIG_TIMER_CLK_FREQ 12500000 553 554 #define CONFIG_HWCONFIG 555 #define HWCONFIG_BUFFER_SIZE 256 556 557 #define CONFIG_FSL_DEVICE_DISABLE 558 559 560 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 561 562 #ifdef CONFIG_LPUART 563 #define CONFIG_EXTRA_ENV_SETTINGS \ 564 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 565 "fdt_high=0xffffffff\0" \ 566 "initrd_high=0xffffffff\0" \ 567 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 568 #else 569 #define CONFIG_EXTRA_ENV_SETTINGS \ 570 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 571 "fdt_high=0xffffffff\0" \ 572 "initrd_high=0xffffffff\0" \ 573 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 574 #endif 575 576 /* 577 * Miscellaneous configurable options 578 */ 579 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 580 #define CONFIG_AUTO_COMPLETE 581 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 582 #define CONFIG_SYS_PBSIZE \ 583 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 584 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 585 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 586 587 #define CONFIG_SYS_MEMTEST_START 0x80000000 588 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 589 590 #define CONFIG_SYS_LOAD_ADDR 0x82000000 591 592 #define CONFIG_LS102XA_STREAM_ID 593 594 /* 595 * Stack sizes 596 * The stack sizes are set up in start.S using the settings below 597 */ 598 #define CONFIG_STACKSIZE (30 * 1024) 599 600 #define CONFIG_SYS_INIT_SP_OFFSET \ 601 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 602 #define CONFIG_SYS_INIT_SP_ADDR \ 603 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 604 605 #ifdef CONFIG_SPL_BUILD 606 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 607 #else 608 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 609 #endif 610 611 /* 612 * Environment 613 */ 614 #define CONFIG_ENV_OVERWRITE 615 616 #if defined(CONFIG_SD_BOOT) 617 #define CONFIG_ENV_OFFSET 0x100000 618 #define CONFIG_ENV_IS_IN_MMC 619 #define CONFIG_SYS_MMC_ENV_DEV 0 620 #define CONFIG_ENV_SIZE 0x2000 621 #elif defined(CONFIG_QSPI_BOOT) 622 #define CONFIG_ENV_IS_IN_SPI_FLASH 623 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 624 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 625 #define CONFIG_ENV_SECT_SIZE 0x10000 626 #elif defined(CONFIG_NAND_BOOT) 627 #define CONFIG_ENV_IS_IN_NAND 628 #define CONFIG_ENV_SIZE 0x2000 629 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 630 #else 631 #define CONFIG_ENV_IS_IN_FLASH 632 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 633 #define CONFIG_ENV_SIZE 0x2000 634 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 635 #endif 636 637 #define CONFIG_MISC_INIT_R 638 639 /* Hash command with SHA acceleration supported in hardware */ 640 #ifdef CONFIG_FSL_CAAM 641 #define CONFIG_CMD_HASH 642 #define CONFIG_SHA_HW_ACCEL 643 #endif 644 645 #include <asm/fsl_secure_boot.h> 646 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 647 648 #endif 649