1 /* 2 * Copyright (C) 2013 Samsung Electronics 3 * 4 * Configuration settings for the SAMSUNG EXYNOS5 board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_EXYNOS5_COMMON_H 10 #define __CONFIG_EXYNOS5_COMMON_H 11 12 #define CONFIG_EXYNOS5 /* Exynos5 Family */ 13 14 #include "exynos-common.h" 15 16 #define CONFIG_EXYNOS_SPL 17 18 #ifdef FTRACE 19 #define CONFIG_TRACE 20 #define CONFIG_CMD_TRACE 21 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) 22 #define CONFIG_TRACE_EARLY_SIZE (8 << 20) 23 #define CONFIG_TRACE_EARLY 24 #define CONFIG_TRACE_EARLY_ADDR 0x50000000 25 #endif 26 27 /* Enable ACE acceleration for SHA1 and SHA256 */ 28 #define CONFIG_EXYNOS_ACE_SHA 29 #define CONFIG_SHA_HW_ACCEL 30 31 /* Power Down Modes */ 32 #define S5P_CHECK_SLEEP 0x00000BAD 33 #define S5P_CHECK_DIDLE 0xBAD00000 34 #define S5P_CHECK_LPA 0xABAD0000 35 36 /* Offset for inform registers */ 37 #define INFORM0_OFFSET 0x800 38 #define INFORM1_OFFSET 0x804 39 #define INFORM2_OFFSET 0x808 40 #define INFORM3_OFFSET 0x80c 41 42 /* select serial console configuration */ 43 #define CONFIG_BAUDRATE 115200 44 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 45 #define CONFIG_SILENT_CONSOLE 46 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 47 #define CONFIG_CONSOLE_MUX 48 49 #define CONFIG_CMD_HASH 50 51 /* Thermal Management Unit */ 52 #define CONFIG_EXYNOS_TMU 53 #define CONFIG_CMD_DTT 54 #define CONFIG_TMU_CMD_DTT 55 56 /* MMC SPL */ 57 #define COPY_BL2_FNPTR_ADDR 0x02020030 58 #define CONFIG_SUPPORT_EMMC_BOOT 59 60 #define CONFIG_SPL_LIBGENERIC_SUPPORT 61 62 /* specific .lds file */ 63 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" 64 65 /* Boot Argument Buffer Size */ 66 /* memtest works on */ 67 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 68 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) 69 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 70 71 #define CONFIG_RD_LVL 72 73 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 74 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 75 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 76 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 77 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 78 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 79 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 80 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 81 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 82 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 83 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 84 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 85 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 86 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 87 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 88 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 89 90 #define CONFIG_SYS_MONITOR_BASE 0x00000000 91 92 #define CONFIG_SYS_MMC_ENV_DEV 0 93 94 #define CONFIG_SECURE_BL1_ONLY 95 96 /* Secure FW size configuration */ 97 #ifdef CONFIG_SECURE_BL1_ONLY 98 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ 99 #else 100 #define CONFIG_SEC_FW_SIZE 0 101 #endif 102 103 /* Configuration of BL1, BL2, ENV Blocks on mmc */ 104 #define CONFIG_RES_BLOCK_SIZE (512) 105 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 106 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ 107 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 108 109 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) 110 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) 111 112 /* U-Boot copy size from boot Media to DRAM.*/ 113 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) 114 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) 115 116 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 117 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) 118 119 /* I2C */ 120 #define CONFIG_SYS_I2C_S3C24X0 121 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ 122 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 123 124 /* SPI */ 125 #ifdef CONFIG_SPI_FLASH 126 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 127 #define CONFIG_SF_DEFAULT_SPEED 50000000 128 #endif 129 130 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 131 #define CONFIG_ENV_SPI_MODE SPI_MODE_0 132 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 133 #define CONFIG_ENV_SPI_BUS 1 134 #define CONFIG_ENV_SPI_MAX_HZ 50000000 135 #endif 136 137 /* Ethernet Controllor Driver */ 138 #ifdef CONFIG_CMD_NET 139 #define CONFIG_SMC911X 140 #define CONFIG_SMC911X_BASE 0x5000000 141 #define CONFIG_SMC911X_16_BIT 142 #define CONFIG_ENV_SROM_BANK 1 143 #endif /*CONFIG_CMD_NET*/ 144 145 /* SHA hashing */ 146 #define CONFIG_CMD_HASH 147 #define CONFIG_HASH_VERIFY 148 #define CONFIG_SHA1 149 #define CONFIG_SHA256 150 151 /* Enable Time Command */ 152 153 /* USB */ 154 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 155 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 156 157 #define CONFIG_USB_HOST_ETHER 158 #define CONFIG_USB_ETHER_ASIX 159 #define CONFIG_USB_ETHER_SMSC95XX 160 #define CONFIG_USB_ETHER_RTL8152 161 162 /* USB boot mode */ 163 #define CONFIG_USB_BOOTING 164 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 165 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 166 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 167 168 #define BOOT_TARGET_DEVICES(func) \ 169 func(MMC, mmc, 1) \ 170 func(MMC, mmc, 0) \ 171 func(PXE, pxe, na) \ 172 func(DHCP, dhcp, na) 173 174 #include <config_distro_bootcmd.h> 175 176 #ifndef MEM_LAYOUT_ENV_SETTINGS 177 /* 2GB RAM, bootm size of 256M, load scripts after that */ 178 #define MEM_LAYOUT_ENV_SETTINGS \ 179 "bootm_size=0x10000000\0" \ 180 "kernel_addr_r=0x42000000\0" \ 181 "fdt_addr_r=0x43000000\0" \ 182 "ramdisk_addr_r=0x43300000\0" \ 183 "scriptaddr=0x50000000\0" \ 184 "pxefile_addr_r=0x51000000\0" 185 #endif 186 187 #ifndef EXYNOS_DEVICE_SETTINGS 188 #define EXYNOS_DEVICE_SETTINGS \ 189 "stdin=serial\0" \ 190 "stdout=serial\0" \ 191 "stderr=serial\0" 192 #endif 193 194 #ifndef EXYNOS_FDTFILE_SETTING 195 #define EXYNOS_FDTFILE_SETTING 196 #endif 197 198 #define CONFIG_EXTRA_ENV_SETTINGS \ 199 EXYNOS_DEVICE_SETTINGS \ 200 EXYNOS_FDTFILE_SETTING \ 201 MEM_LAYOUT_ENV_SETTINGS \ 202 BOOTENV 203 204 #endif /* __CONFIG_EXYNOS5_COMMON_H */ 205