1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg 24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_FSL_LAW /* Use common FSL init code */ 33 #define CONFIG_SYS_TEXT_BASE 0x00201000 34 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 35 #define CONFIG_SPL_PAD_TO 0x40000 36 #define CONFIG_SPL_MAX_SIZE 0x28000 37 #define RESET_VECTOR_OFFSET 0x27FFC 38 #define BOOT_PAGE_OFFSET 0x27000 39 40 #ifdef CONFIG_NAND 41 #define CONFIG_SPL_NAND_SUPPORT 42 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 43 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 44 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 45 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 47 #define CONFIG_SPL_NAND_BOOT 48 #endif 49 50 #ifdef CONFIG_SDCARD 51 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 52 #define CONFIG_SPL_MMC_SUPPORT 53 #define CONFIG_SPL_MMC_MINIMAL 54 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 55 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 56 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 57 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 58 #ifndef CONFIG_SPL_BUILD 59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 60 #endif 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 62 #define CONFIG_SPL_MMC_BOOT 63 #endif 64 65 #ifdef CONFIG_SPL_BUILD 66 #define CONFIG_SPL_SKIP_RELOCATE 67 #define CONFIG_SPL_COMMON_INIT_DDR 68 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 69 #define CONFIG_SYS_NO_FLASH 70 #endif 71 72 #endif 73 #endif /* CONFIG_RAMBOOT_PBL */ 74 75 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 76 /* Set 1M boot space */ 77 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 79 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 80 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 81 #define CONFIG_SYS_NO_FLASH 82 #endif 83 84 #define CONFIG_SRIO_PCIE_BOOT_MASTER 85 #define CONFIG_DDR_ECC 86 87 #include "t4qds.h" 88 89 #ifdef CONFIG_SYS_NO_FLASH 90 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 91 #define CONFIG_ENV_IS_NOWHERE 92 #endif 93 #else 94 #define CONFIG_FLASH_CFI_DRIVER 95 #define CONFIG_SYS_FLASH_CFI 96 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 97 #endif 98 99 #if defined(CONFIG_SPIFLASH) 100 #define CONFIG_SYS_EXTRA_ENV_RELOC 101 #define CONFIG_ENV_IS_IN_SPI_FLASH 102 #define CONFIG_ENV_SPI_BUS 0 103 #define CONFIG_ENV_SPI_CS 0 104 #define CONFIG_ENV_SPI_MAX_HZ 10000000 105 #define CONFIG_ENV_SPI_MODE 0 106 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 107 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 108 #define CONFIG_ENV_SECT_SIZE 0x10000 109 #elif defined(CONFIG_SDCARD) 110 #define CONFIG_SYS_EXTRA_ENV_RELOC 111 #define CONFIG_ENV_IS_IN_MMC 112 #define CONFIG_SYS_MMC_ENV_DEV 0 113 #define CONFIG_ENV_SIZE 0x2000 114 #define CONFIG_ENV_OFFSET (512 * 0x800) 115 #elif defined(CONFIG_NAND) 116 #define CONFIG_SYS_EXTRA_ENV_RELOC 117 #define CONFIG_ENV_IS_IN_NAND 118 #define CONFIG_ENV_SIZE 0x2000 119 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 120 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 121 #define CONFIG_ENV_IS_IN_REMOTE 122 #define CONFIG_ENV_ADDR 0xffe20000 123 #define CONFIG_ENV_SIZE 0x2000 124 #elif defined(CONFIG_ENV_IS_NOWHERE) 125 #define CONFIG_ENV_SIZE 0x2000 126 #else 127 #define CONFIG_ENV_IS_IN_FLASH 128 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 129 #define CONFIG_ENV_SIZE 0x2000 130 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 131 #endif 132 133 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 134 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 135 136 #ifndef __ASSEMBLY__ 137 unsigned long get_board_sys_clk(void); 138 unsigned long get_board_ddr_clk(void); 139 #endif 140 141 /* EEPROM */ 142 #define CONFIG_ID_EEPROM 143 #define CONFIG_SYS_I2C_EEPROM_NXID 144 #define CONFIG_SYS_EEPROM_BUS_NUM 0 145 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 146 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 147 148 /* 149 * DDR Setup 150 */ 151 #define CONFIG_SYS_SPD_BUS_NUM 0 152 #define SPD_EEPROM_ADDRESS1 0x51 153 #define SPD_EEPROM_ADDRESS2 0x52 154 #define SPD_EEPROM_ADDRESS3 0x53 155 #define SPD_EEPROM_ADDRESS4 0x54 156 #define SPD_EEPROM_ADDRESS5 0x55 157 #define SPD_EEPROM_ADDRESS6 0x56 158 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 159 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 160 161 /* 162 * IFC Definitions 163 */ 164 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 165 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 166 + 0x8000000) | \ 167 CSPR_PORT_SIZE_16 | \ 168 CSPR_MSEL_NOR | \ 169 CSPR_V) 170 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 171 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 172 CSPR_PORT_SIZE_16 | \ 173 CSPR_MSEL_NOR | \ 174 CSPR_V) 175 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 176 /* NOR Flash Timing Params */ 177 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 178 179 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 180 FTIM0_NOR_TEADC(0x5) | \ 181 FTIM0_NOR_TEAHC(0x5)) 182 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 183 FTIM1_NOR_TRAD_NOR(0x1A) |\ 184 FTIM1_NOR_TSEQRAD_NOR(0x13)) 185 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 186 FTIM2_NOR_TCH(0x4) | \ 187 FTIM2_NOR_TWPH(0x0E) | \ 188 FTIM2_NOR_TWP(0x1c)) 189 #define CONFIG_SYS_NOR_FTIM3 0x0 190 191 #define CONFIG_SYS_FLASH_QUIET_TEST 192 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 193 194 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 195 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 196 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 197 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 198 199 #define CONFIG_SYS_FLASH_EMPTY_INFO 200 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 201 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 202 203 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 204 #define QIXIS_BASE 0xffdf0000 205 #define QIXIS_LBMAP_SWITCH 6 206 #define QIXIS_LBMAP_MASK 0x0f 207 #define QIXIS_LBMAP_SHIFT 0 208 #define QIXIS_LBMAP_DFLTBANK 0x00 209 #define QIXIS_LBMAP_ALTBANK 0x04 210 #define QIXIS_RST_CTL_RESET 0x83 211 #define QIXIS_RST_FORCE_MEM 0x1 212 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 213 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 214 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 215 #define QIXIS_BRDCFG5 0x55 216 #define QIXIS_MUX_SDHC 2 217 #define QIXIS_MUX_SDHC_WIDTH8 1 218 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 219 220 #define CONFIG_SYS_CSPR3_EXT (0xf) 221 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 222 | CSPR_PORT_SIZE_8 \ 223 | CSPR_MSEL_GPCM \ 224 | CSPR_V) 225 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 226 #define CONFIG_SYS_CSOR3 0x0 227 /* QIXIS Timing parameters for IFC CS3 */ 228 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 229 FTIM0_GPCM_TEADC(0x0e) | \ 230 FTIM0_GPCM_TEAHC(0x0e)) 231 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 232 FTIM1_GPCM_TRAD(0x3f)) 233 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 234 FTIM2_GPCM_TCH(0x8) | \ 235 FTIM2_GPCM_TWP(0x1f)) 236 #define CONFIG_SYS_CS3_FTIM3 0x0 237 238 /* NAND Flash on IFC */ 239 #define CONFIG_NAND_FSL_IFC 240 #define CONFIG_SYS_NAND_BASE 0xff800000 241 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 242 243 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 244 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 245 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 246 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 247 | CSPR_V) 248 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 249 250 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 251 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 252 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 253 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 254 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 255 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 256 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 257 258 #define CONFIG_SYS_NAND_ONFI_DETECTION 259 260 /* ONFI NAND Flash mode0 Timing Params */ 261 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 262 FTIM0_NAND_TWP(0x18) | \ 263 FTIM0_NAND_TWCHT(0x07) | \ 264 FTIM0_NAND_TWH(0x0a)) 265 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 266 FTIM1_NAND_TWBE(0x39) | \ 267 FTIM1_NAND_TRR(0x0e) | \ 268 FTIM1_NAND_TRP(0x18)) 269 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 270 FTIM2_NAND_TREH(0x0a) | \ 271 FTIM2_NAND_TWHRE(0x1e)) 272 #define CONFIG_SYS_NAND_FTIM3 0x0 273 274 #define CONFIG_SYS_NAND_DDR_LAW 11 275 276 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 277 #define CONFIG_SYS_MAX_NAND_DEVICE 1 278 #define CONFIG_CMD_NAND 279 280 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 281 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 282 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 283 284 #if defined(CONFIG_NAND) 285 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 286 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 287 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 288 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 289 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 290 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 291 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 292 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 293 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 294 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 295 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 296 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 297 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 298 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 299 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 300 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 301 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 302 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 303 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 304 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 305 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 306 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 307 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 308 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 309 #else 310 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 318 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 319 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 320 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 327 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 328 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 329 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 330 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 331 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 332 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 333 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 334 #endif 335 336 #if defined(CONFIG_RAMBOOT_PBL) 337 #define CONFIG_SYS_RAMBOOT 338 #endif 339 340 /* I2C */ 341 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 342 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 343 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 344 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 345 346 #define I2C_MUX_CH_DEFAULT 0x8 347 #define I2C_MUX_CH_VOL_MONITOR 0xa 348 #define I2C_MUX_CH_VSC3316_FS 0xc 349 #define I2C_MUX_CH_VSC3316_BS 0xd 350 351 /* Voltage monitor on channel 2*/ 352 #define I2C_VOL_MONITOR_ADDR 0x40 353 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 354 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 355 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 356 357 /* VSC Crossbar switches */ 358 #define CONFIG_VSC_CROSSBAR 359 #define VSC3316_FSM_TX_ADDR 0x70 360 #define VSC3316_FSM_RX_ADDR 0x71 361 362 /* 363 * RapidIO 364 */ 365 366 /* 367 * for slave u-boot IMAGE instored in master memory space, 368 * PHYS must be aligned based on the SIZE 369 */ 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 374 /* 375 * for slave UCODE and ENV instored in master memory space, 376 * PHYS must be aligned based on the SIZE 377 */ 378 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 379 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 381 382 /* slave core release by master*/ 383 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 384 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 385 386 /* 387 * SRIO_PCIE_BOOT - SLAVE 388 */ 389 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 390 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 391 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 392 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 393 #endif 394 /* 395 * eSPI - Enhanced SPI 396 */ 397 #define CONFIG_SF_DEFAULT_SPEED 10000000 398 #define CONFIG_SF_DEFAULT_MODE 0 399 400 /* Qman/Bman */ 401 #ifndef CONFIG_NOBQFMAN 402 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 403 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 404 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 405 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 406 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 407 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 408 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 409 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 410 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 411 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 412 CONFIG_SYS_BMAN_CENA_SIZE) 413 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 414 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 415 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 416 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 417 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 418 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 419 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 420 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 421 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 422 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 423 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 424 CONFIG_SYS_QMAN_CENA_SIZE) 425 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 426 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 427 428 #define CONFIG_SYS_DPAA_FMAN 429 #define CONFIG_SYS_DPAA_PME 430 #define CONFIG_SYS_PMAN 431 #define CONFIG_SYS_DPAA_DCE 432 #define CONFIG_SYS_DPAA_RMAN 433 #define CONFIG_SYS_INTERLAKEN 434 435 /* Default address of microcode for the Linux Fman driver */ 436 #if defined(CONFIG_SPIFLASH) 437 /* 438 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 439 * env, so we got 0x110000. 440 */ 441 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 442 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 443 #elif defined(CONFIG_SDCARD) 444 /* 445 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 446 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 447 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 448 */ 449 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 450 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 451 #elif defined(CONFIG_NAND) 452 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 453 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 454 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 455 /* 456 * Slave has no ucode locally, it can fetch this from remote. When implementing 457 * in two corenet boards, slave's ucode could be stored in master's memory 458 * space, the address can be mapped from slave TLB->slave LAW-> 459 * slave SRIO or PCIE outbound window->master inbound window-> 460 * master LAW->the ucode address in master's memory space. 461 */ 462 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 463 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 464 #else 465 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 466 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 467 #endif 468 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 469 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 470 #endif /* CONFIG_NOBQFMAN */ 471 472 #ifdef CONFIG_SYS_DPAA_FMAN 473 #define CONFIG_FMAN_ENET 474 #define CONFIG_PHYLIB_10G 475 #define CONFIG_PHY_VITESSE 476 #define CONFIG_PHY_TERANETICS 477 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 478 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 479 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 480 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 481 #define FM1_10GEC1_PHY_ADDR 0x0 482 #define FM1_10GEC2_PHY_ADDR 0x1 483 #define FM2_10GEC1_PHY_ADDR 0x2 484 #define FM2_10GEC2_PHY_ADDR 0x3 485 #endif 486 487 /* SATA */ 488 #ifdef CONFIG_FSL_SATA_V2 489 #define CONFIG_LIBATA 490 #define CONFIG_FSL_SATA 491 492 #define CONFIG_SYS_SATA_MAX_DEVICE 2 493 #define CONFIG_SATA1 494 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 495 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 496 #define CONFIG_SATA2 497 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 498 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 499 500 #define CONFIG_LBA48 501 #define CONFIG_CMD_SATA 502 #define CONFIG_DOS_PARTITION 503 #endif 504 505 #ifdef CONFIG_FMAN_ENET 506 #define CONFIG_MII /* MII PHY management */ 507 #define CONFIG_ETHPRIME "FM1@DTSEC1" 508 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 509 #endif 510 511 /* Hash command with SHA acceleration supported in hardware */ 512 #ifdef CONFIG_FSL_CAAM 513 #define CONFIG_CMD_HASH 514 #define CONFIG_SHA_HW_ACCEL 515 #endif 516 517 /* 518 * USB 519 */ 520 #define CONFIG_USB_EHCI 521 #define CONFIG_USB_EHCI_FSL 522 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 523 #define CONFIG_HAS_FSL_DR_USB 524 525 #define CONFIG_MMC 526 527 #ifdef CONFIG_MMC 528 #define CONFIG_FSL_ESDHC 529 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 530 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 531 #define CONFIG_GENERIC_MMC 532 #define CONFIG_DOS_PARTITION 533 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 534 #define CONFIG_ESDHC_DETECT_QUIRK \ 535 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 536 IS_SVR_REV(get_svr(), 1, 0)) 537 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 538 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 539 #endif 540 541 542 #define __USB_PHY_TYPE utmi 543 544 /* 545 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 546 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 547 * interleaving. It can be cacheline, page, bank, superbank. 548 * See doc/README.fsl-ddr for details. 549 */ 550 #ifdef CONFIG_PPC_T4240 551 #define CTRL_INTLV_PREFERED 3way_4KB 552 #else 553 #define CTRL_INTLV_PREFERED cacheline 554 #endif 555 556 #define CONFIG_EXTRA_ENV_SETTINGS \ 557 "hwconfig=fsl_ddr:" \ 558 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 559 "bank_intlv=auto;" \ 560 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 561 "netdev=eth0\0" \ 562 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 563 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 564 "tftpflash=tftpboot $loadaddr $uboot && " \ 565 "protect off $ubootaddr +$filesize && " \ 566 "erase $ubootaddr +$filesize && " \ 567 "cp.b $loadaddr $ubootaddr $filesize && " \ 568 "protect on $ubootaddr +$filesize && " \ 569 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 570 "consoledev=ttyS0\0" \ 571 "ramdiskaddr=2000000\0" \ 572 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 573 "fdtaddr=1e00000\0" \ 574 "fdtfile=t4240qds/t4240qds.dtb\0" \ 575 "bdev=sda3\0" 576 577 #define CONFIG_HVBOOT \ 578 "setenv bootargs config-addr=0x60000000; " \ 579 "bootm 0x01000000 - 0x00f00000" 580 581 #define CONFIG_ALU \ 582 "setenv bootargs root=/dev/$bdev rw " \ 583 "console=$consoledev,$baudrate $othbootargs;" \ 584 "cpu 1 release 0x01000000 - - -;" \ 585 "cpu 2 release 0x01000000 - - -;" \ 586 "cpu 3 release 0x01000000 - - -;" \ 587 "cpu 4 release 0x01000000 - - -;" \ 588 "cpu 5 release 0x01000000 - - -;" \ 589 "cpu 6 release 0x01000000 - - -;" \ 590 "cpu 7 release 0x01000000 - - -;" \ 591 "go 0x01000000" 592 593 #define CONFIG_LINUX \ 594 "setenv bootargs root=/dev/ram rw " \ 595 "console=$consoledev,$baudrate $othbootargs;" \ 596 "setenv ramdiskaddr 0x02000000;" \ 597 "setenv fdtaddr 0x00c00000;" \ 598 "setenv loadaddr 0x1000000;" \ 599 "bootm $loadaddr $ramdiskaddr $fdtaddr" 600 601 #define CONFIG_HDBOOT \ 602 "setenv bootargs root=/dev/$bdev rw " \ 603 "console=$consoledev,$baudrate $othbootargs;" \ 604 "tftp $loadaddr $bootfile;" \ 605 "tftp $fdtaddr $fdtfile;" \ 606 "bootm $loadaddr - $fdtaddr" 607 608 #define CONFIG_NFSBOOTCOMMAND \ 609 "setenv bootargs root=/dev/nfs rw " \ 610 "nfsroot=$serverip:$rootpath " \ 611 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 612 "console=$consoledev,$baudrate $othbootargs;" \ 613 "tftp $loadaddr $bootfile;" \ 614 "tftp $fdtaddr $fdtfile;" \ 615 "bootm $loadaddr - $fdtaddr" 616 617 #define CONFIG_RAMBOOTCOMMAND \ 618 "setenv bootargs root=/dev/ram rw " \ 619 "console=$consoledev,$baudrate $othbootargs;" \ 620 "tftp $ramdiskaddr $ramdiskfile;" \ 621 "tftp $loadaddr $bootfile;" \ 622 "tftp $fdtaddr $fdtfile;" \ 623 "bootm $loadaddr $ramdiskaddr $fdtaddr" 624 625 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 626 627 #include <asm/fsl_secure_boot.h> 628 629 #endif /* __CONFIG_H */ 630