1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg 24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 29 #define CONFIG_SPL_SERIAL_SUPPORT 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LIBGENERIC_SUPPORT 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_SYS_TEXT_BASE 0x00201000 35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 36 #define CONFIG_SPL_PAD_TO 0x40000 37 #define CONFIG_SPL_MAX_SIZE 0x28000 38 #define RESET_VECTOR_OFFSET 0x27FFC 39 #define BOOT_PAGE_OFFSET 0x27000 40 41 #ifdef CONFIG_NAND 42 #define CONFIG_SPL_NAND_SUPPORT 43 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 44 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 45 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 46 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 47 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 48 #define CONFIG_SPL_NAND_BOOT 49 #endif 50 51 #ifdef CONFIG_SDCARD 52 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 53 #define CONFIG_SPL_MMC_SUPPORT 54 #define CONFIG_SPL_MMC_MINIMAL 55 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 56 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 57 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 58 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 59 #ifndef CONFIG_SPL_BUILD 60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 61 #endif 62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 63 #define CONFIG_SPL_MMC_BOOT 64 #endif 65 66 #ifdef CONFIG_SPL_BUILD 67 #define CONFIG_SPL_SKIP_RELOCATE 68 #define CONFIG_SPL_COMMON_INIT_DDR 69 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 70 #define CONFIG_SYS_NO_FLASH 71 #endif 72 73 #endif 74 #endif /* CONFIG_RAMBOOT_PBL */ 75 76 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 77 /* Set 1M boot space */ 78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 80 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 81 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 82 #define CONFIG_SYS_NO_FLASH 83 #endif 84 85 #define CONFIG_SRIO_PCIE_BOOT_MASTER 86 #define CONFIG_DDR_ECC 87 88 #include "t4qds.h" 89 90 #ifdef CONFIG_SYS_NO_FLASH 91 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 92 #define CONFIG_ENV_IS_NOWHERE 93 #endif 94 #else 95 #define CONFIG_FLASH_CFI_DRIVER 96 #define CONFIG_SYS_FLASH_CFI 97 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 98 #endif 99 100 #if defined(CONFIG_SPIFLASH) 101 #define CONFIG_SYS_EXTRA_ENV_RELOC 102 #define CONFIG_ENV_IS_IN_SPI_FLASH 103 #define CONFIG_ENV_SPI_BUS 0 104 #define CONFIG_ENV_SPI_CS 0 105 #define CONFIG_ENV_SPI_MAX_HZ 10000000 106 #define CONFIG_ENV_SPI_MODE 0 107 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 108 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 109 #define CONFIG_ENV_SECT_SIZE 0x10000 110 #elif defined(CONFIG_SDCARD) 111 #define CONFIG_SYS_EXTRA_ENV_RELOC 112 #define CONFIG_ENV_IS_IN_MMC 113 #define CONFIG_SYS_MMC_ENV_DEV 0 114 #define CONFIG_ENV_SIZE 0x2000 115 #define CONFIG_ENV_OFFSET (512 * 0x800) 116 #elif defined(CONFIG_NAND) 117 #define CONFIG_SYS_EXTRA_ENV_RELOC 118 #define CONFIG_ENV_IS_IN_NAND 119 #define CONFIG_ENV_SIZE 0x2000 120 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 121 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 122 #define CONFIG_ENV_IS_IN_REMOTE 123 #define CONFIG_ENV_ADDR 0xffe20000 124 #define CONFIG_ENV_SIZE 0x2000 125 #elif defined(CONFIG_ENV_IS_NOWHERE) 126 #define CONFIG_ENV_SIZE 0x2000 127 #else 128 #define CONFIG_ENV_IS_IN_FLASH 129 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 130 #define CONFIG_ENV_SIZE 0x2000 131 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 132 #endif 133 134 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 135 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 136 137 #ifndef __ASSEMBLY__ 138 unsigned long get_board_sys_clk(void); 139 unsigned long get_board_ddr_clk(void); 140 #endif 141 142 /* EEPROM */ 143 #define CONFIG_ID_EEPROM 144 #define CONFIG_SYS_I2C_EEPROM_NXID 145 #define CONFIG_SYS_EEPROM_BUS_NUM 0 146 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 148 149 /* 150 * DDR Setup 151 */ 152 #define CONFIG_SYS_SPD_BUS_NUM 0 153 #define SPD_EEPROM_ADDRESS1 0x51 154 #define SPD_EEPROM_ADDRESS2 0x52 155 #define SPD_EEPROM_ADDRESS3 0x53 156 #define SPD_EEPROM_ADDRESS4 0x54 157 #define SPD_EEPROM_ADDRESS5 0x55 158 #define SPD_EEPROM_ADDRESS6 0x56 159 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 160 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 161 162 /* 163 * IFC Definitions 164 */ 165 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 166 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 167 + 0x8000000) | \ 168 CSPR_PORT_SIZE_16 | \ 169 CSPR_MSEL_NOR | \ 170 CSPR_V) 171 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 172 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 173 CSPR_PORT_SIZE_16 | \ 174 CSPR_MSEL_NOR | \ 175 CSPR_V) 176 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 177 /* NOR Flash Timing Params */ 178 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 179 180 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 181 FTIM0_NOR_TEADC(0x5) | \ 182 FTIM0_NOR_TEAHC(0x5)) 183 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 184 FTIM1_NOR_TRAD_NOR(0x1A) |\ 185 FTIM1_NOR_TSEQRAD_NOR(0x13)) 186 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 187 FTIM2_NOR_TCH(0x4) | \ 188 FTIM2_NOR_TWPH(0x0E) | \ 189 FTIM2_NOR_TWP(0x1c)) 190 #define CONFIG_SYS_NOR_FTIM3 0x0 191 192 #define CONFIG_SYS_FLASH_QUIET_TEST 193 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 194 195 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 196 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 199 200 #define CONFIG_SYS_FLASH_EMPTY_INFO 201 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 202 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 203 204 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 205 #define QIXIS_BASE 0xffdf0000 206 #define QIXIS_LBMAP_SWITCH 6 207 #define QIXIS_LBMAP_MASK 0x0f 208 #define QIXIS_LBMAP_SHIFT 0 209 #define QIXIS_LBMAP_DFLTBANK 0x00 210 #define QIXIS_LBMAP_ALTBANK 0x04 211 #define QIXIS_RST_CTL_RESET 0x83 212 #define QIXIS_RST_FORCE_MEM 0x1 213 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 214 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 215 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 216 #define QIXIS_BRDCFG5 0x55 217 #define QIXIS_MUX_SDHC 2 218 #define QIXIS_MUX_SDHC_WIDTH8 1 219 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 220 221 #define CONFIG_SYS_CSPR3_EXT (0xf) 222 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 223 | CSPR_PORT_SIZE_8 \ 224 | CSPR_MSEL_GPCM \ 225 | CSPR_V) 226 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 227 #define CONFIG_SYS_CSOR3 0x0 228 /* QIXIS Timing parameters for IFC CS3 */ 229 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 230 FTIM0_GPCM_TEADC(0x0e) | \ 231 FTIM0_GPCM_TEAHC(0x0e)) 232 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 233 FTIM1_GPCM_TRAD(0x3f)) 234 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 235 FTIM2_GPCM_TCH(0x8) | \ 236 FTIM2_GPCM_TWP(0x1f)) 237 #define CONFIG_SYS_CS3_FTIM3 0x0 238 239 /* NAND Flash on IFC */ 240 #define CONFIG_NAND_FSL_IFC 241 #define CONFIG_SYS_NAND_BASE 0xff800000 242 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 243 244 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 245 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 246 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 247 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 248 | CSPR_V) 249 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 250 251 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 252 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 253 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 254 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 255 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 256 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 257 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 258 259 #define CONFIG_SYS_NAND_ONFI_DETECTION 260 261 /* ONFI NAND Flash mode0 Timing Params */ 262 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 263 FTIM0_NAND_TWP(0x18) | \ 264 FTIM0_NAND_TWCHT(0x07) | \ 265 FTIM0_NAND_TWH(0x0a)) 266 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 267 FTIM1_NAND_TWBE(0x39) | \ 268 FTIM1_NAND_TRR(0x0e) | \ 269 FTIM1_NAND_TRP(0x18)) 270 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 271 FTIM2_NAND_TREH(0x0a) | \ 272 FTIM2_NAND_TWHRE(0x1e)) 273 #define CONFIG_SYS_NAND_FTIM3 0x0 274 275 #define CONFIG_SYS_NAND_DDR_LAW 11 276 277 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 278 #define CONFIG_SYS_MAX_NAND_DEVICE 1 279 #define CONFIG_CMD_NAND 280 281 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 282 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 283 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 284 285 #if defined(CONFIG_NAND) 286 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 287 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 288 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 289 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 290 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 291 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 292 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 293 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 294 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 295 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 296 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 297 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 298 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 299 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 300 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 301 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 302 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 303 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 304 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 305 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 306 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 307 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 308 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 309 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 310 #else 311 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 312 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 313 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 314 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 315 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 316 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 317 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 318 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 319 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 320 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 321 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 322 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 323 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 324 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 325 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 326 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 327 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 328 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 329 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 330 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 331 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 332 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 333 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 334 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 335 #endif 336 337 #if defined(CONFIG_RAMBOOT_PBL) 338 #define CONFIG_SYS_RAMBOOT 339 #endif 340 341 /* I2C */ 342 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 343 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 344 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 345 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 346 347 #define I2C_MUX_CH_DEFAULT 0x8 348 #define I2C_MUX_CH_VOL_MONITOR 0xa 349 #define I2C_MUX_CH_VSC3316_FS 0xc 350 #define I2C_MUX_CH_VSC3316_BS 0xd 351 352 /* Voltage monitor on channel 2*/ 353 #define I2C_VOL_MONITOR_ADDR 0x40 354 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 355 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 356 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 357 358 /* VSC Crossbar switches */ 359 #define CONFIG_VSC_CROSSBAR 360 #define VSC3316_FSM_TX_ADDR 0x70 361 #define VSC3316_FSM_RX_ADDR 0x71 362 363 /* 364 * RapidIO 365 */ 366 367 /* 368 * for slave u-boot IMAGE instored in master memory space, 369 * PHYS must be aligned based on the SIZE 370 */ 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 373 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 374 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 375 /* 376 * for slave UCODE and ENV instored in master memory space, 377 * PHYS must be aligned based on the SIZE 378 */ 379 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 380 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 381 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 382 383 /* slave core release by master*/ 384 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 385 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 386 387 /* 388 * SRIO_PCIE_BOOT - SLAVE 389 */ 390 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 391 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 392 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 393 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 394 #endif 395 /* 396 * eSPI - Enhanced SPI 397 */ 398 #define CONFIG_SF_DEFAULT_SPEED 10000000 399 #define CONFIG_SF_DEFAULT_MODE 0 400 401 /* Qman/Bman */ 402 #ifndef CONFIG_NOBQFMAN 403 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 404 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 405 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 406 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 407 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 408 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 409 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 410 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 411 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 412 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 413 CONFIG_SYS_BMAN_CENA_SIZE) 414 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 415 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 416 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 417 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 418 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 419 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 420 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 421 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 422 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 423 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 424 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 425 CONFIG_SYS_QMAN_CENA_SIZE) 426 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 427 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 428 429 #define CONFIG_SYS_DPAA_FMAN 430 #define CONFIG_SYS_DPAA_PME 431 #define CONFIG_SYS_PMAN 432 #define CONFIG_SYS_DPAA_DCE 433 #define CONFIG_SYS_DPAA_RMAN 434 #define CONFIG_SYS_INTERLAKEN 435 436 /* Default address of microcode for the Linux Fman driver */ 437 #if defined(CONFIG_SPIFLASH) 438 /* 439 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 440 * env, so we got 0x110000. 441 */ 442 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 443 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 444 #elif defined(CONFIG_SDCARD) 445 /* 446 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 447 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 448 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 449 */ 450 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 451 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 452 #elif defined(CONFIG_NAND) 453 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 454 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 455 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 456 /* 457 * Slave has no ucode locally, it can fetch this from remote. When implementing 458 * in two corenet boards, slave's ucode could be stored in master's memory 459 * space, the address can be mapped from slave TLB->slave LAW-> 460 * slave SRIO or PCIE outbound window->master inbound window-> 461 * master LAW->the ucode address in master's memory space. 462 */ 463 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 464 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 465 #else 466 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 467 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 468 #endif 469 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 470 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 471 #endif /* CONFIG_NOBQFMAN */ 472 473 #ifdef CONFIG_SYS_DPAA_FMAN 474 #define CONFIG_FMAN_ENET 475 #define CONFIG_PHYLIB_10G 476 #define CONFIG_PHY_VITESSE 477 #define CONFIG_PHY_TERANETICS 478 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 479 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 480 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 481 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 482 #define FM1_10GEC1_PHY_ADDR 0x0 483 #define FM1_10GEC2_PHY_ADDR 0x1 484 #define FM2_10GEC1_PHY_ADDR 0x2 485 #define FM2_10GEC2_PHY_ADDR 0x3 486 #endif 487 488 /* SATA */ 489 #ifdef CONFIG_FSL_SATA_V2 490 #define CONFIG_LIBATA 491 #define CONFIG_FSL_SATA 492 493 #define CONFIG_SYS_SATA_MAX_DEVICE 2 494 #define CONFIG_SATA1 495 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 496 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 497 #define CONFIG_SATA2 498 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 499 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 500 501 #define CONFIG_LBA48 502 #define CONFIG_CMD_SATA 503 #define CONFIG_DOS_PARTITION 504 #endif 505 506 #ifdef CONFIG_FMAN_ENET 507 #define CONFIG_MII /* MII PHY management */ 508 #define CONFIG_ETHPRIME "FM1@DTSEC1" 509 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 510 #endif 511 512 /* Hash command with SHA acceleration supported in hardware */ 513 #ifdef CONFIG_FSL_CAAM 514 #define CONFIG_CMD_HASH 515 #define CONFIG_SHA_HW_ACCEL 516 #endif 517 518 /* 519 * USB 520 */ 521 #define CONFIG_USB_EHCI 522 #define CONFIG_USB_EHCI_FSL 523 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 524 #define CONFIG_HAS_FSL_DR_USB 525 526 #define CONFIG_MMC 527 528 #ifdef CONFIG_MMC 529 #define CONFIG_FSL_ESDHC 530 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 531 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 532 #define CONFIG_GENERIC_MMC 533 #define CONFIG_DOS_PARTITION 534 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 535 #define CONFIG_ESDHC_DETECT_QUIRK \ 536 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 537 IS_SVR_REV(get_svr(), 1, 0)) 538 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 539 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 540 #endif 541 542 543 #define __USB_PHY_TYPE utmi 544 545 /* 546 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 547 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 548 * interleaving. It can be cacheline, page, bank, superbank. 549 * See doc/README.fsl-ddr for details. 550 */ 551 #ifdef CONFIG_PPC_T4240 552 #define CTRL_INTLV_PREFERED 3way_4KB 553 #else 554 #define CTRL_INTLV_PREFERED cacheline 555 #endif 556 557 #define CONFIG_EXTRA_ENV_SETTINGS \ 558 "hwconfig=fsl_ddr:" \ 559 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 560 "bank_intlv=auto;" \ 561 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 562 "netdev=eth0\0" \ 563 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 564 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 565 "tftpflash=tftpboot $loadaddr $uboot && " \ 566 "protect off $ubootaddr +$filesize && " \ 567 "erase $ubootaddr +$filesize && " \ 568 "cp.b $loadaddr $ubootaddr $filesize && " \ 569 "protect on $ubootaddr +$filesize && " \ 570 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 571 "consoledev=ttyS0\0" \ 572 "ramdiskaddr=2000000\0" \ 573 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 574 "fdtaddr=1e00000\0" \ 575 "fdtfile=t4240qds/t4240qds.dtb\0" \ 576 "bdev=sda3\0" 577 578 #define CONFIG_HVBOOT \ 579 "setenv bootargs config-addr=0x60000000; " \ 580 "bootm 0x01000000 - 0x00f00000" 581 582 #define CONFIG_ALU \ 583 "setenv bootargs root=/dev/$bdev rw " \ 584 "console=$consoledev,$baudrate $othbootargs;" \ 585 "cpu 1 release 0x01000000 - - -;" \ 586 "cpu 2 release 0x01000000 - - -;" \ 587 "cpu 3 release 0x01000000 - - -;" \ 588 "cpu 4 release 0x01000000 - - -;" \ 589 "cpu 5 release 0x01000000 - - -;" \ 590 "cpu 6 release 0x01000000 - - -;" \ 591 "cpu 7 release 0x01000000 - - -;" \ 592 "go 0x01000000" 593 594 #define CONFIG_LINUX \ 595 "setenv bootargs root=/dev/ram rw " \ 596 "console=$consoledev,$baudrate $othbootargs;" \ 597 "setenv ramdiskaddr 0x02000000;" \ 598 "setenv fdtaddr 0x00c00000;" \ 599 "setenv loadaddr 0x1000000;" \ 600 "bootm $loadaddr $ramdiskaddr $fdtaddr" 601 602 #define CONFIG_HDBOOT \ 603 "setenv bootargs root=/dev/$bdev rw " \ 604 "console=$consoledev,$baudrate $othbootargs;" \ 605 "tftp $loadaddr $bootfile;" \ 606 "tftp $fdtaddr $fdtfile;" \ 607 "bootm $loadaddr - $fdtaddr" 608 609 #define CONFIG_NFSBOOTCOMMAND \ 610 "setenv bootargs root=/dev/nfs rw " \ 611 "nfsroot=$serverip:$rootpath " \ 612 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 613 "console=$consoledev,$baudrate $othbootargs;" \ 614 "tftp $loadaddr $bootfile;" \ 615 "tftp $fdtaddr $fdtfile;" \ 616 "bootm $loadaddr - $fdtaddr" 617 618 #define CONFIG_RAMBOOTCOMMAND \ 619 "setenv bootargs root=/dev/ram rw " \ 620 "console=$consoledev,$baudrate $othbootargs;" \ 621 "tftp $ramdiskaddr $ramdiskfile;" \ 622 "tftp $loadaddr $bootfile;" \ 623 "tftp $fdtaddr $fdtfile;" \ 624 "bootm $loadaddr $ramdiskaddr $fdtaddr" 625 626 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 627 628 #include <asm/fsl_secure_boot.h> 629 630 #endif /* __CONFIG_H */ 631