rockchip/rk3399: Remove unneeded register sets

This removes the mmio_... function calls to set the multicast bit for
the PHY registers when overriding the write leveling values. These are
not needed

rockchip/rk3399: Remove unneeded register sets

This removes the mmio_... function calls to set the multicast bit for
the PHY registers when overriding the write leveling values. These are
not needed since multicast is set by default when calling the
function, and it's also better not to leave the side effect of
disabling multicast when exiting the function.

Change-Id: I83e089a2a2d55268b3832f36724c3b2c4be81082
Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip/rk3399: remove unneeded DDR restore function

This removes the phy_dll_bypass_set function as it is unneeded. The
values that function sets are saved during suspend, so the proper
values wil

rockchip/rk3399: remove unneeded DDR restore function

This removes the phy_dll_bypass_set function as it is unneeded. The
values that function sets are saved during suspend, so the proper
values will be restored on resume.

Change-Id: I17542206c56e639ce8cb6375233145167441d4e2
Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip/rk3399: Save space for DRAM suspend data

This removes the space allocation for the unused PHY register space.
For instance in PHY registers 0-127, only 0-90 are used, so don't save
the 91-1

rockchip/rk3399: Save space for DRAM suspend data

This removes the space allocation for the unused PHY register space.
For instance in PHY registers 0-127, only 0-90 are used, so don't save
the 91-127 registers. This saves about 1.6KB of space.

Change-Id: I0c9f6d9bed8f0c1f3b8b805dfb10cf0c06208919
Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip: add pmusram section

the function pmu_cpuon_entrypoint() need to run in the pmusram,
we just copy bin file to pmusram before, now we add pmusram section
and link pmu_cpuon_entrypoint() to p

rockchip: add pmusram section

the function pmu_cpuon_entrypoint() need to run in the pmusram,
we just copy bin file to pmusram before, now we add pmusram section
and link pmu_cpuon_entrypoint() to pmusram directly

Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip/rk3399: fix DRAM gate training issue

The differential signal of DQS need keep low level
before gate training. It need enable RPULL and disable
PHY side ODT to ensure it when do gate trainin

rockchip/rk3399: fix DRAM gate training issue

The differential signal of DQS need keep low level
before gate training. It need enable RPULL and disable
PHY side ODT to ensure it when do gate training.
But it can not access the PHY registers to do it when
perform DFS.So the workaroud as below: It is ensure that
the PHY's read gate is landing somewhere in the incoming
DQS's pulses before it starts searching for pre-amble window.
It need get the rddqs_delay_ps to calculate the start point
of gate training for DFS.

Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe
Signed-off-by: Lin Huang <hl@rock-chips.com>

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rockchip: rk3328: Add assert check in pmu.c

Add assert() check for cpuson_flags[] and cpuson_entry_point[].

Change-Id: I971fe54c2baa3b4514a3979042341220f5e20901
Signed-off-by: tony.xie <tony.xie@ro

rockchip: rk3328: Add assert check in pmu.c

Add assert() check for cpuson_flags[] and cpuson_entry_point[].

Change-Id: I971fe54c2baa3b4514a3979042341220f5e20901
Signed-off-by: tony.xie <tony.xie@rock-chips.com>

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Use SPDX license identifiers for remaining files

Change-Id: I7f54f45db65f32481cc05e1bd2c9c683b756e19a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

Merge pull request #918 from rockchip-linux/rk3328

rockchip: rk3328: support rk3328

Revert "rockchip: Remove unused rockchip_pd_pwr_down_wfi function"

This reverts commit b6dcbf588af442fa87721dc707ff9e54d04ff504.

This function wasn't used when it was removed, but it is needed to
c

Revert "rockchip: Remove unused rockchip_pd_pwr_down_wfi function"

This reverts commit b6dcbf588af442fa87721dc707ff9e54d04ff504.

This function wasn't used when it was removed, but it is needed to
compile the new changes proposed for Rockchip platforms.

Change-Id: Ia5bfe1f8398e08431f96923e2f059a83e5cb78d4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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rockchip: rk3328: Add a missing paragraph for copyright notice.

Change-Id: I78c7e304d3070f66e2ca3bf838c76ee6a2ae3430
Signed-off-by: tony.xie <tony.xie@rock-chips.com>

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/

Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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rockchip: rk3328: support rk3328
rk3328 is a Quad-core soc and Cortex-a53 inside!
This patch supports the following functions:
1、power up/off cpus
2、suspend/resume cpus
3、suspend/resume system
4、rese

rockchip: rk3328: support rk3328
rk3328 is a Quad-core soc and Cortex-a53 inside!
This patch supports the following functions:
1、power up/off cpus
2、suspend/resume cpus
3、suspend/resume system
4、reset system
5、power off system

Change-Id: I60687058d13912c6929293b06fed9c6bc72bdc84
Signed-off-by: tony.xie <tony.xie@rock-chips.com>

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Merge pull request #892 from rockchip-linux/fixes-a-typo

rockchip/rk3399: the printf changed to tf_printf for console output

rockchip/rk3399: changed printf/tf_printf for console output

The printf() isn't used by the firmware itself, just by the tools under
the ./tools/ folder. Then tf_printf will unconditionally print.
R

rockchip/rk3399: changed printf/tf_printf for console output

The printf() isn't used by the firmware itself, just by the tools under
the ./tools/ folder. Then tf_printf will unconditionally print.
Remove the unused print_dram_status_info() function.

Change-Id: Ie699ccb54a5be9a2cbbd7b8d4193b57075a2f57a
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: Remove unused rockchip_pd_pwr_down_wfi function

The rockchip_pd_pwr_down_wfi function is currently unused, which may
trigger compiler warnings or errors. Remove it.

Change-Id: I7e1b0ae092

rockchip: Remove unused rockchip_pd_pwr_down_wfi function

The rockchip_pd_pwr_down_wfi function is currently unused, which may
trigger compiler warnings or errors. Remove it.

Change-Id: I7e1b0ae092e8855528ac2065ecefc8bd45305f31
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>

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Move plat/common source file definitions to generic Makefiles

These source file definitions should be defined in generic
Makefiles so that all platforms can benefit. Ensure that the
symbols are prop

Move plat/common source file definitions to generic Makefiles

These source file definitions should be defined in generic
Makefiles so that all platforms can benefit. Ensure that the
symbols are properly marked as weak so they can be overridden
by platforms.

NOTE: This change is a potential compatibility break for
non-upstream platforms.

Change-Id: I7b892efa9f2d6d216931360dc6c436e1d10cffed
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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Merge pull request #854 from rockchip-linux/pm_plat

rockchip: plat_pm.c: Change callbacks implement for our SOCs.

rockchip: Change the callback implement of power domain for rk3368

Change-Id: I6d39b4cac9b34b1f841e9bbddaf9c49785ba0c5e
Signed-off-by: tony.xie <tony.xie@rock-chips.com>

rockchip: plat_pm.c: Change callbacks implement for our SOCs.

Remove struct rockchip_pm_ops_cb and instead of using weak functions
implement; in this way we want the codes look clear and simple;

Ch

rockchip: plat_pm.c: Change callbacks implement for our SOCs.

Remove struct rockchip_pm_ops_cb and instead of using weak functions
implement; in this way we want the codes look clear and simple;

Change-Id: Ib9e8a5e932fdfc2b3e6a1ec502c40dfe720ac400
Signed-off-by: tony.xie <tony.xie@rock-chips.com>

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Merge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210

RK3399 ARM TF clean up 20170210

rockchip: rk3399: enable secure accessing for SRAM

Sorry to miss the security configuration for SRAM, if we don't support
it, somebody may modify the comment of SRAM in the non-secure space.
Let's f

rockchip: rk3399: enable secure accessing for SRAM

Sorry to miss the security configuration for SRAM, if we don't support
it, somebody may modify the comment of SRAM in the non-secure space.
Let's fix this issue.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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rockchip: rk3399: Use tFC value instead of tRFC value

This fixes code that set a tFC value in a register using the tRFC
value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

rockchip: rk3399: Fix CAS latency setting

The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.

Signed-off-by: Derek Basehore <dbasehore

rockchip: rk3399: Fix CAS latency setting

The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip: rk3399: disable training modules after DDR DFS

On resume, we use the DFS hardware to switch frequency index,
followed by a full training sequence on that index. Leaving
the DFS training mo

rockchip: rk3399: disable training modules after DDR DFS

On resume, we use the DFS hardware to switch frequency index,
followed by a full training sequence on that index. Leaving
the DFS training modules enabled causes issues with the full
training done at resume. We also only needs these enabled
during a call to ddr_set_rate during runtime, so there's no
issue disabling them at the end of ddr_set_rate.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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rockchip: rk3399: Move DQS drive strength setting to M0

This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength

rockchip: rk3399: Move DQS drive strength setting to M0

This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength
changed for data training, which is triggered by the M0, but it also
needs to be changed back when data training is finished.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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