1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLAT_DEF_H__ 32 #define __PLAT_DEF_H__ 33 34 #define MAJOR_VERSION (1) 35 #define MINOR_VERSION (2) 36 37 #define SIZE_K(n) ((n) * 1024) 38 39 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 40 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 41 42 #define UART2_BASE 0xff130000 43 #define UART2_SIZE SIZE_K(64) 44 45 #define PMU_BASE 0xff140000 46 #define PMU_SIZE SIZE_K(64) 47 48 #define SGRF_BASE 0xff0d0000 49 #define SGRF_SIZE SIZE_K(64) 50 51 #define CRU_BASE 0xff440000 52 #define CRU_SIZE SIZE_K(64) 53 54 #define GRF_BASE 0xff100000 55 #define GRF_SIZE SIZE_K(64) 56 57 #define GPIO0_BASE 0xff210000 58 #define GPIO0_SIZE SIZE_K(32) 59 60 #define GPIO1_BASE 0xff220000 61 #define GPIO1_SIZE SIZE_K(32) 62 63 #define GPIO2_BASE 0xff230000 64 #define GPIO2_SIZE SIZE_K(64) 65 66 #define GPIO3_BASE 0xff240000 67 #define GPIO3_SIZE SIZE_K(64) 68 69 #define STIME_BASE 0xff1d0000 70 #define STIME_SIZE SIZE_K(64) 71 72 #define INTMEM_BASE 0xff090000 73 #define INTMEM_SIZE SIZE_K(32) 74 75 #define SRAM_LDS_BASE (INTMEM_BASE + SIZE_K(4)) 76 #define SRAM_LDS_SIZE (INTMEM_SIZE - SIZE_K(4)) 77 78 #define PMUSRAM_BASE INTMEM_BASE 79 #define PMUSRAM_SIZE SIZE_K(4) 80 #define PMUSRAM_RSIZE SIZE_K(4) 81 82 #define VOP_BASE 0xff370000 83 #define VOP_SIZE SIZE_K(16) 84 85 #define DDR_PHY_BASE 0xff400000 86 #define DDR_PHY_SIZE SIZE_K(4) 87 88 #define SERVER_MSCH_BASE 0xff720000 89 #define SERVER_MSCH_SIZE SIZE_K(4) 90 91 #define DDR_UPCTL_BASE 0xff780000 92 #define DDR_UPCTL_SIZE SIZE_K(12) 93 94 #define DDR_MONITOR_BASE 0xff790000 95 #define DDR_MONITOR_SIZE SIZE_K(4) 96 97 #define FIREWALL_DDR_BASE 0xff7c0000 98 #define FIREWALL_DDR_SIZE SIZE_K(64) 99 100 #define FIREWALL_CFG_BASE 0xff7d0000 101 #define FIREWALL_CFG_SIZE SIZE_K(64) 102 103 #define GIC400_BASE 0xff810000 104 #define GIC400_SIZE SIZE_K(64) 105 106 #define DDR_GRF_BASE 0xff798000 107 #define DDR_GRF_SIZE SIZE_K(16) 108 109 #define PWM_BASE 0xff1b0000 110 #define PWM_SIZE SIZE_K(64) 111 112 #define DDR_PARAM_BASE 0x02000000 113 #define DDR_PARAM_SIZE SIZE_K(4) 114 115 #define EFUSE8_BASE 0xff260000 116 #define EFUSE8_SIZE SIZE_K(4) 117 118 #define EFUSE32_BASE 0xff0b0000 119 #define EFUSE32_SIZE SIZE_K(4) 120 121 /************************************************************************** 122 * UART related constants 123 **************************************************************************/ 124 #define RK3328_UART2_BASE UART2_BASE 125 #define RK3328_BAUDRATE 1500000 126 #define RK3328_UART_CLOCK 24000000 127 128 /****************************************************************************** 129 * System counter frequency related constants 130 ******************************************************************************/ 131 #define SYS_COUNTER_FREQ_IN_TICKS 24000000U 132 #define SYS_COUNTER_FREQ_IN_MHZ 24 133 134 /****************************************************************************** 135 * GIC-400 & interrupt handling related constants 136 ******************************************************************************/ 137 138 /* Base rk_platform compatible GIC memory map */ 139 #define RK3328_GICD_BASE (GIC400_BASE + 0x1000) 140 #define RK3328_GICC_BASE (GIC400_BASE + 0x2000) 141 #define RK3328_GICR_BASE 0 /* no GICR in GIC-400 */ 142 143 /****************************************************************************** 144 * sgi, ppi 145 ******************************************************************************/ 146 #define RK_IRQ_SEC_PHY_TIMER 29 147 148 #define RK_IRQ_SEC_SGI_0 8 149 #define RK_IRQ_SEC_SGI_1 9 150 #define RK_IRQ_SEC_SGI_2 10 151 #define RK_IRQ_SEC_SGI_3 11 152 #define RK_IRQ_SEC_SGI_4 12 153 #define RK_IRQ_SEC_SGI_5 13 154 #define RK_IRQ_SEC_SGI_6 14 155 #define RK_IRQ_SEC_SGI_7 15 156 157 /* 158 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 159 * terminology. On a GICv2 system or mode, the lists will be merged and treated 160 * as Group 0 interrupts. 161 */ 162 #define RK_G1S_IRQS RK_IRQ_SEC_PHY_TIMER, RK_IRQ_SEC_SGI_6 163 164 #define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/ 165 #define SHARE_MEM_PAGE_NUM 15 166 #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 167 168 #endif /* __PLAT_DEF_H__ */ 169