1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <string.h> 32 #include <stdint.h> 33 #include <dram.h> 34 #include "dram_spec_timing.h" 35 36 static const uint8_t ddr3_cl_cwl[][7] = { 37 /* 38 * speed 0~330 331 ~ 400 401 ~ 533 534~666 667~800 801~933 934~1066 39 * tCK>3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07 40 * cl<<4, cwl cl<<4, cwl cl<<4, cwl 41 */ 42 /* DDR3_800D (5-5-5) */ 43 {((5 << 4) | 5), ((5 << 4) | 5), 0, 0, 0, 0, 0}, 44 /* DDR3_800E (6-6-6) */ 45 {((5 << 4) | 5), ((6 << 4) | 5), 0, 0, 0, 0, 0}, 46 /* DDR3_1066E (6-6-6) */ 47 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), 0, 0, 0, 0}, 48 /* DDR3_1066F (7-7-7) */ 49 {((5 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), 0, 0, 0, 0}, 50 /* DDR3_1066G (8-8-8) */ 51 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), 0, 0, 0, 0}, 52 /* DDR3_1333F (7-7-7) */ 53 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 54 0, 0, 0}, 55 /* DDR3_1333G (8-8-8) */ 56 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 57 0, 0, 0}, 58 /* DDR3_1333H (9-9-9) */ 59 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((9 << 4) | 7), 60 0, 0, 0}, 61 /* DDR3_1333J (10-10-10) */ 62 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 63 0, 0, 0}, 64 /* DDR3_1600G (8-8-8) */ 65 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 66 ((8 << 4) | 8), 0, 0}, 67 /* DDR3_1600H (9-9-9) */ 68 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 69 ((9 << 4) | 8), 0, 0}, 70 /* DDR3_1600J (10-10-10) */ 71 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 72 ((10 << 4) | 8), 0, 0}, 73 /* DDR3_1600K (11-11-11) */ 74 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 75 ((11 << 4) | 8), 0, 0}, 76 /* DDR3_1866J (10-10-10) */ 77 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 78 ((9 << 4) | 8), ((11 << 4) | 9), 0}, 79 /* DDR3_1866K (11-11-11) */ 80 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 81 ((10 << 4) | 8), ((11 << 4) | 9), 0}, 82 /* DDR3_1866L (12-12-12) */ 83 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 84 ((11 << 4) | 8), ((12 << 4) | 9), 0}, 85 /* DDR3_1866M (13-13-13) */ 86 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 87 ((11 << 4) | 8), ((13 << 4) | 9), 0}, 88 /* DDR3_2133K (11-11-11) */ 89 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 90 ((9 << 4) | 8), ((10 << 4) | 9), ((11 << 4) | 10)}, 91 /* DDR3_2133L (12-12-12) */ 92 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 93 ((9 << 4) | 8), ((11 << 4) | 9), ((12 << 4) | 10)}, 94 /* DDR3_2133M (13-13-13) */ 95 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 96 ((10 << 4) | 8), ((12 << 4) | 9), ((13 << 4) | 10)}, 97 /* DDR3_2133N (14-14-14) */ 98 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 99 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)}, 100 /* DDR3_DEFAULT */ 101 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 102 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)} 103 }; 104 105 static const uint16_t ddr3_trc_tfaw[] = { 106 /* tRC tFAW */ 107 ((50 << 8) | 50), /* DDR3_800D (5-5-5) */ 108 ((53 << 8) | 50), /* DDR3_800E (6-6-6) */ 109 110 ((49 << 8) | 50), /* DDR3_1066E (6-6-6) */ 111 ((51 << 8) | 50), /* DDR3_1066F (7-7-7) */ 112 ((53 << 8) | 50), /* DDR3_1066G (8-8-8) */ 113 114 ((47 << 8) | 45), /* DDR3_1333F (7-7-7) */ 115 ((48 << 8) | 45), /* DDR3_1333G (8-8-8) */ 116 ((50 << 8) | 45), /* DDR3_1333H (9-9-9) */ 117 ((51 << 8) | 45), /* DDR3_1333J (10-10-10) */ 118 119 ((45 << 8) | 40), /* DDR3_1600G (8-8-8) */ 120 ((47 << 8) | 40), /* DDR3_1600H (9-9-9)*/ 121 ((48 << 8) | 40), /* DDR3_1600J (10-10-10) */ 122 ((49 << 8) | 40), /* DDR3_1600K (11-11-11) */ 123 124 ((45 << 8) | 35), /* DDR3_1866J (10-10-10) */ 125 ((46 << 8) | 35), /* DDR3_1866K (11-11-11) */ 126 ((47 << 8) | 35), /* DDR3_1866L (12-12-12) */ 127 ((48 << 8) | 35), /* DDR3_1866M (13-13-13) */ 128 129 ((44 << 8) | 35), /* DDR3_2133K (11-11-11) */ 130 ((45 << 8) | 35), /* DDR3_2133L (12-12-12) */ 131 ((46 << 8) | 35), /* DDR3_2133M (13-13-13) */ 132 ((47 << 8) | 35), /* DDR3_2133N (14-14-14) */ 133 134 ((53 << 8) | 50) /* DDR3_DEFAULT */ 135 }; 136 137 static uint32_t get_max_speed_rate(struct timing_related_config *timing_config) 138 { 139 if (timing_config->ch_cnt > 1) 140 return max(timing_config->dram_info[0].speed_rate, 141 timing_config->dram_info[1].speed_rate); 142 else 143 return timing_config->dram_info[0].speed_rate; 144 } 145 146 static uint32_t 147 get_max_die_capability(struct timing_related_config *timing_config) 148 { 149 uint32_t die_cap = 0; 150 uint32_t cs, ch; 151 152 for (ch = 0; ch < timing_config->ch_cnt; ch++) { 153 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { 154 die_cap = max(die_cap, 155 timing_config-> 156 dram_info[ch].per_die_capability[cs]); 157 } 158 } 159 return die_cap; 160 } 161 162 /* tRSTL, 100ns */ 163 #define DDR3_TRSTL (100) 164 /* trsth, 500us */ 165 #define DDR3_TRSTH (500000) 166 /* trefi, 7.8us */ 167 #define DDR3_TREFI_7_8_US (7800) 168 /* tWR, 15ns */ 169 #define DDR3_TWR (15) 170 /* tRTP, max(4 tCK,7.5ns) */ 171 #define DDR3_TRTP (7) 172 /* tRRD = max(4nCK, 10ns) */ 173 #define DDR3_TRRD (10) 174 /* tCK */ 175 #define DDR3_TCCD (4) 176 /*tWTR, max(4 tCK,7.5ns)*/ 177 #define DDR3_TWTR (7) 178 /* tCK */ 179 #define DDR3_TRTW (0) 180 /* tRAS, 37.5ns(400MHz) 37.5ns(533MHz) */ 181 #define DDR3_TRAS (37) 182 /* ns */ 183 #define DDR3_TRFC_512MBIT (90) 184 /* ns */ 185 #define DDR3_TRFC_1GBIT (110) 186 /* ns */ 187 #define DDR3_TRFC_2GBIT (160) 188 /* ns */ 189 #define DDR3_TRFC_4GBIT (300) 190 /* ns */ 191 #define DDR3_TRFC_8GBIT (350) 192 193 /*pd and sr*/ 194 #define DDR3_TXP (7) /* tXP, max(3 tCK, 7.5ns)( < 933MHz) */ 195 #define DDR3_TXPDLL (24) /* tXPDLL, max(10 tCK, 24ns) */ 196 #define DDR3_TDLLK (512) /* tXSR, tDLLK=512 tCK */ 197 #define DDR3_TCKE_400MHZ (7) /* tCKE, max(3 tCK,7.5ns)(400MHz) */ 198 #define DDR3_TCKE_533MHZ (6) /* tCKE, max(3 tCK,5.625ns)(533MHz) */ 199 #define DDR3_TCKSRE (10) /* tCKSRX, max(5 tCK, 10ns) */ 200 201 /*mode register timing*/ 202 #define DDR3_TMOD (15) /* tMOD, max(12 tCK,15ns) */ 203 #define DDR3_TMRD (4) /* tMRD, 4 tCK */ 204 205 /* ZQ */ 206 #define DDR3_TZQINIT (640) /* tZQinit, max(512 tCK, 640ns) */ 207 #define DDR3_TZQCS (80) /* tZQCS, max(64 tCK, 80ns) */ 208 #define DDR3_TZQOPER (320) /* tZQoper, max(256 tCK, 320ns) */ 209 210 /* Write leveling */ 211 #define DDR3_TWLMRD (40) /* tCK */ 212 #define DDR3_TWLO (9) /* max 7.5ns */ 213 #define DDR3_TWLDQSEN (25) /* tCK */ 214 215 /* 216 * Description: depend on input parameter "timing_config", 217 * and calculate all ddr3 218 * spec timing to "pdram_timing" 219 * parameters: 220 * input: timing_config 221 * output: pdram_timing 222 */ 223 static void ddr3_get_parameter(struct timing_related_config *timing_config, 224 struct dram_timing_t *pdram_timing) 225 { 226 uint32_t nmhz = timing_config->freq; 227 uint32_t ddr_speed_bin = get_max_speed_rate(timing_config); 228 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 229 uint32_t tmp; 230 231 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 232 pdram_timing->mhz = nmhz; 233 pdram_timing->al = 0; 234 pdram_timing->bl = timing_config->bl; 235 if (nmhz <= 330) 236 tmp = 0; 237 else if (nmhz <= 400) 238 tmp = 1; 239 else if (nmhz <= 533) 240 tmp = 2; 241 else if (nmhz <= 666) 242 tmp = 3; 243 else if (nmhz <= 800) 244 tmp = 4; 245 else if (nmhz <= 933) 246 tmp = 5; 247 else 248 tmp = 6; 249 250 /* when dll bypss cl = cwl = 6 */ 251 if (nmhz < 300) { 252 pdram_timing->cl = 6; 253 pdram_timing->cwl = 6; 254 } else { 255 pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf; 256 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; 257 } 258 259 switch (timing_config->dramds) { 260 case 40: 261 tmp = DDR3_DS_40; 262 break; 263 case 34: 264 default: 265 tmp = DDR3_DS_34; 266 break; 267 } 268 269 if (timing_config->odt) 270 switch (timing_config->dramodt) { 271 case 60: 272 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; 273 break; 274 case 40: 275 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; 276 break; 277 case 120: 278 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; 279 break; 280 case 0: 281 default: 282 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 283 break; 284 } 285 else 286 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 287 288 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); 289 pdram_timing->mr[3] = 0; 290 291 pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000); 292 pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000); 293 /* tREFI, average periodic refresh interval, 7.8us */ 294 pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000); 295 /* base timing */ 296 pdram_timing->trcd = pdram_timing->cl; 297 pdram_timing->trp = pdram_timing->cl; 298 pdram_timing->trppb = pdram_timing->cl; 299 tmp = ((DDR3_TWR * nmhz + 999) / 1000); 300 pdram_timing->twr = tmp; 301 pdram_timing->tdal = tmp + pdram_timing->trp; 302 if (tmp < 9) { 303 tmp = tmp - 4; 304 } else { 305 tmp += (tmp & 0x1) ? 1 : 0; 306 tmp = tmp >> 1; 307 } 308 if (pdram_timing->bl == 4) 309 pdram_timing->mr[0] = DDR3_BC4 310 | DDR3_CL(pdram_timing->cl) 311 | DDR3_WR(tmp); 312 else 313 pdram_timing->mr[0] = DDR3_BL8 314 | DDR3_CL(pdram_timing->cl) 315 | DDR3_WR(tmp); 316 tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 317 pdram_timing->trtp = max(4, tmp); 318 pdram_timing->trc = 319 (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000); 320 tmp = ((DDR3_TRRD * nmhz + 999) / 1000); 321 pdram_timing->trrd = max(4, tmp); 322 pdram_timing->tccd = DDR3_TCCD; 323 tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 324 pdram_timing->twtr = max(4, tmp); 325 pdram_timing->trtw = DDR3_TRTW; 326 pdram_timing->tras_max = 9 * pdram_timing->trefi; 327 pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999) 328 / 1000); 329 pdram_timing->tfaw = 330 (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999) 331 / 1000); 332 /* tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb) */ 333 if (ddr_capability_per_die <= 0x4000000) 334 tmp = DDR3_TRFC_512MBIT; 335 else if (ddr_capability_per_die <= 0x8000000) 336 tmp = DDR3_TRFC_1GBIT; 337 else if (ddr_capability_per_die <= 0x10000000) 338 tmp = DDR3_TRFC_2GBIT; 339 else if (ddr_capability_per_die <= 0x20000000) 340 tmp = DDR3_TRFC_4GBIT; 341 else 342 tmp = DDR3_TRFC_8GBIT; 343 pdram_timing->trfc = (tmp * nmhz + 999) / 1000; 344 pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000)); 345 pdram_timing->tdqsck_max = 0; 346 /*pd and sr*/ 347 pdram_timing->txsr = DDR3_TDLLK; 348 tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 349 pdram_timing->txp = max(3, tmp); 350 tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000); 351 pdram_timing->txpdll = max(10, tmp); 352 pdram_timing->tdllk = DDR3_TDLLK; 353 if (nmhz >= 533) 354 tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000); 355 else 356 tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000); 357 pdram_timing->tcke = max(3, tmp); 358 pdram_timing->tckesr = (pdram_timing->tcke + 1); 359 tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000); 360 pdram_timing->tcksre = max(5, tmp); 361 pdram_timing->tcksrx = max(5, tmp); 362 /*mode register timing*/ 363 tmp = ((DDR3_TMOD * nmhz + 999) / 1000); 364 pdram_timing->tmod = max(12, tmp); 365 pdram_timing->tmrd = DDR3_TMRD; 366 pdram_timing->tmrr = 0; 367 /*ODT*/ 368 pdram_timing->todton = pdram_timing->cwl - 2; 369 /*ZQ*/ 370 tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000); 371 pdram_timing->tzqinit = max(512, tmp); 372 tmp = ((DDR3_TZQCS * nmhz + 999) / 1000); 373 pdram_timing->tzqcs = max(64, tmp); 374 tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000); 375 pdram_timing->tzqoper = max(256, tmp); 376 /* write leveling */ 377 pdram_timing->twlmrd = DDR3_TWLMRD; 378 pdram_timing->twldqsen = DDR3_TWLDQSEN; 379 pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000); 380 } 381 382 #define LPDDR2_TINIT1 (100) /* ns */ 383 #define LPDDR2_TINIT2 (5) /* tCK */ 384 #define LPDDR2_TINIT3 (200000) /* 200us */ 385 #define LPDDR2_TINIT4 (1000) /* 1us */ 386 #define LPDDR2_TINIT5 (10000) /* 10us */ 387 #define LPDDR2_TRSTL (0) /* tCK */ 388 #define LPDDR2_TRSTH (500000) /* 500us */ 389 #define LPDDR2_TREFI_3_9_US (3900) /* 3.9us */ 390 #define LPDDR2_TREFI_7_8_US (7800) /* 7.8us */ 391 392 /* base timing */ 393 #define LPDDR2_TRCD (24) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 394 #define LPDDR2_TRP_PB (18) /* tRPpb,15ns(Fast)18ns(Typ)24ns(Slow) */ 395 #define LPDDR2_TRP_AB_8_BANK (21) /* tRPab,18ns(Fast)21ns(Typ)27ns(Slow) */ 396 #define LPDDR2_TWR (15) /* tWR, max(3tCK,15ns) */ 397 #define LPDDR2_TRTP (7) /* tRTP, max(2tCK, 7.5ns) */ 398 #define LPDDR2_TRRD (10) /* tRRD, max(2tCK,10ns) */ 399 #define LPDDR2_TCCD (2) /* tCK */ 400 #define LPDDR2_TWTR_GREAT_200MHZ (7) /* ns */ 401 #define LPDDR2_TWTR_LITTLE_200MHZ (10) /* ns */ 402 #define LPDDR2_TRTW (0) /* tCK */ 403 #define LPDDR2_TRAS_MAX (70000) /* 70us */ 404 #define LPDDR2_TRAS (42) /* tRAS, max(3tCK,42ns) */ 405 #define LPDDR2_TFAW_GREAT_200MHZ (50) /* max(8tCK,50ns) */ 406 #define LPDDR2_TFAW_LITTLE_200MHZ (60) /* max(8tCK,60ns) */ 407 #define LPDDR2_TRFC_8GBIT (210) /* ns */ 408 #define LPDDR2_TRFC_4GBIT (130) /* ns */ 409 #define LPDDR2_TDQSCK_MIN (2) /* tDQSCKmin, 2.5ns */ 410 #define LPDDR2_TDQSCK_MAX (5) /* tDQSCKmax, 5.5ns */ 411 412 /*pd and sr*/ 413 #define LPDDR2_TXP (7) /* tXP, max(2tCK,7.5ns) */ 414 #define LPDDR2_TXPDLL (0) 415 #define LPDDR2_TDLLK (0) /* tCK */ 416 #define LPDDR2_TCKE (3) /* tCK */ 417 #define LPDDR2_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 418 #define LPDDR2_TCKSRE (1) /* tCK */ 419 #define LPDDR2_TCKSRX (2) /* tCK */ 420 421 /*mode register timing*/ 422 #define LPDDR2_TMOD (0) 423 #define LPDDR2_TMRD (5) /* tMRD, (=tMRW), 5 tCK */ 424 #define LPDDR2_TMRR (2) /* tCK */ 425 426 /*ZQ*/ 427 #define LPDDR2_TZQINIT (1000) /* ns */ 428 #define LPDDR2_TZQCS (90) /* tZQCS, max(6tCK,90ns) */ 429 #define LPDDR2_TZQCL (360) /* tZQCL, max(6tCK,360ns) */ 430 #define LPDDR2_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 431 432 /* 433 * Description: depend on input parameter "timing_config", 434 * and calculate all lpddr2 435 * spec timing to "pdram_timing" 436 * parameters: 437 * input: timing_config 438 * output: pdram_timing 439 */ 440 static void lpddr2_get_parameter(struct timing_related_config *timing_config, 441 struct dram_timing_t *pdram_timing) 442 { 443 uint32_t nmhz = timing_config->freq; 444 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 445 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 446 447 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 448 pdram_timing->mhz = nmhz; 449 pdram_timing->al = 0; 450 pdram_timing->bl = timing_config->bl; 451 452 /* 1066 933 800 667 533 400 333 453 * RL, 8 7 6 5 4 3 3 454 * WL, 4 4 3 2 2 1 1 455 */ 456 if (nmhz <= 266) { 457 pdram_timing->cl = 4; 458 pdram_timing->cwl = 2; 459 pdram_timing->mr[2] = LPDDR2_RL4_WL2; 460 } else if (nmhz <= 333) { 461 pdram_timing->cl = 5; 462 pdram_timing->cwl = 2; 463 pdram_timing->mr[2] = LPDDR2_RL5_WL2; 464 } else if (nmhz <= 400) { 465 pdram_timing->cl = 6; 466 pdram_timing->cwl = 3; 467 pdram_timing->mr[2] = LPDDR2_RL6_WL3; 468 } else if (nmhz <= 466) { 469 pdram_timing->cl = 7; 470 pdram_timing->cwl = 4; 471 pdram_timing->mr[2] = LPDDR2_RL7_WL4; 472 } else { 473 pdram_timing->cl = 8; 474 pdram_timing->cwl = 4; 475 pdram_timing->mr[2] = LPDDR2_RL8_WL4; 476 } 477 switch (timing_config->dramds) { 478 case 120: 479 pdram_timing->mr[3] = LPDDR2_DS_120; 480 break; 481 case 80: 482 pdram_timing->mr[3] = LPDDR2_DS_80; 483 break; 484 case 60: 485 pdram_timing->mr[3] = LPDDR2_DS_60; 486 break; 487 case 48: 488 pdram_timing->mr[3] = LPDDR2_DS_48; 489 break; 490 case 40: 491 pdram_timing->mr[3] = LPDDR2_DS_40; 492 break; 493 case 34: 494 default: 495 pdram_timing->mr[3] = LPDDR2_DS_34; 496 break; 497 } 498 pdram_timing->mr[0] = 0; 499 500 pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000; 501 pdram_timing->tinit2 = LPDDR2_TINIT2; 502 pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000; 503 pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000; 504 pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000; 505 pdram_timing->trstl = LPDDR2_TRSTL; 506 pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000; 507 /* 508 * tREFI, average periodic refresh interval, 509 * 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb) 510 */ 511 if (ddr_capability_per_die >= 0x10000000) 512 pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999) 513 / 1000; 514 else 515 pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999) 516 / 1000; 517 /* base timing */ 518 tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000); 519 pdram_timing->trcd = max(3, tmp); 520 /* 521 * tRPpb, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow), 522 */ 523 trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000); 524 trppb_tmp = max(3, trppb_tmp); 525 pdram_timing->trppb = trppb_tmp; 526 /* 527 * tRPab, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 528 * 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)) 529 */ 530 trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000); 531 trp_tmp = max(3, trp_tmp); 532 pdram_timing->trp = trp_tmp; 533 twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000); 534 twr_tmp = max(3, twr_tmp); 535 pdram_timing->twr = twr_tmp; 536 bl_tmp = (pdram_timing->bl == 16) ? LPDDR2_BL16 : 537 ((pdram_timing->bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4); 538 pdram_timing->mr[1] = bl_tmp | LPDDR2_N_WR(twr_tmp); 539 tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 540 pdram_timing->trtp = max(2, tmp); 541 tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000); 542 tras_tmp = max(3, tras_tmp); 543 pdram_timing->tras_min = tras_tmp; 544 pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000); 545 pdram_timing->trc = (tras_tmp + trp_tmp); 546 tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000); 547 pdram_timing->trrd = max(2, tmp); 548 pdram_timing->tccd = LPDDR2_TCCD; 549 /* tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz)) */ 550 if (nmhz > 200) 551 tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) + 552 999) / 1000); 553 else 554 tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000); 555 pdram_timing->twtr = max(2, tmp); 556 pdram_timing->trtw = LPDDR2_TRTW; 557 if (nmhz <= 200) 558 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999) 559 / 1000; 560 else 561 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999) 562 / 1000; 563 /* tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb) */ 564 if (ddr_capability_per_die >= 0x40000000) { 565 pdram_timing->trfc = 566 (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000; 567 tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 568 } else { 569 pdram_timing->trfc = 570 (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000; 571 tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 572 } 573 if (tmp < 2) 574 tmp = 2; 575 pdram_timing->txsr = tmp; 576 pdram_timing->txsnr = tmp; 577 /* tdqsck use rounded down */ 578 pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1)) 579 / 1000); 580 pdram_timing->tdqsck_max = 581 ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 582 / 1000); 583 /* pd and sr */ 584 tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 585 pdram_timing->txp = max(2, tmp); 586 pdram_timing->txpdll = LPDDR2_TXPDLL; 587 pdram_timing->tdllk = LPDDR2_TDLLK; 588 pdram_timing->tcke = LPDDR2_TCKE; 589 tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000); 590 pdram_timing->tckesr = max(3, tmp); 591 pdram_timing->tcksre = LPDDR2_TCKSRE; 592 pdram_timing->tcksrx = LPDDR2_TCKSRX; 593 /* mode register timing */ 594 pdram_timing->tmod = LPDDR2_TMOD; 595 pdram_timing->tmrd = LPDDR2_TMRD; 596 pdram_timing->tmrr = LPDDR2_TMRR; 597 /* ZQ */ 598 pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000; 599 tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000); 600 pdram_timing->tzqcs = max(6, tmp); 601 tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000); 602 pdram_timing->tzqoper = max(6, tmp); 603 tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000); 604 pdram_timing->tzqreset = max(3, tmp); 605 } 606 607 #define LPDDR3_TINIT1 (100) /* ns */ 608 #define LPDDR3_TINIT2 (5) /* tCK */ 609 #define LPDDR3_TINIT3 (200000) /* 200us */ 610 #define LPDDR3_TINIT4 (1000) /* 1us */ 611 #define LPDDR3_TINIT5 (10000) /* 10us */ 612 #define LPDDR3_TRSTL (0) 613 #define LPDDR3_TRSTH (0) /* 500us */ 614 #define LPDDR3_TREFI_3_9_US (3900) /* 3.9us */ 615 616 /* base timging */ 617 #define LPDDR3_TRCD (18) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 618 #define LPDDR3_TRP_PB (18) /* tRPpb, 15ns(Fast) 18ns(Typ) 24ns(Slow) */ 619 #define LPDDR3_TRP_AB (21) /* tRPab, 18ns(Fast) 21ns(Typ) 27ns(Slow) */ 620 #define LPDDR3_TWR (15) /* tWR, max(4tCK,15ns) */ 621 #define LPDDR3_TRTP (7) /* tRTP, max(4tCK, 7.5ns) */ 622 #define LPDDR3_TRRD (10) /* tRRD, max(2tCK,10ns) */ 623 #define LPDDR3_TCCD (4) /* tCK */ 624 #define LPDDR3_TWTR (7) /* tWTR, max(4tCK, 7.5ns) */ 625 #define LPDDR3_TRTW (0) /* tCK register min valid value */ 626 #define LPDDR3_TRAS_MAX (70000) /* 70us */ 627 #define LPDDR3_TRAS (42) /* tRAS, max(3tCK,42ns) */ 628 #define LPDDR3_TFAW (50) /* tFAW,max(8tCK, 50ns) */ 629 #define LPDDR3_TRFC_8GBIT (210) /* tRFC, 130ns(4Gb) 210ns(>4Gb) */ 630 #define LPDDR3_TRFC_4GBIT (130) /* ns */ 631 #define LPDDR3_TDQSCK_MIN (2) /* tDQSCKmin,2.5ns */ 632 #define LPDDR3_TDQSCK_MAX (5) /* tDQSCKmax,5.5ns */ 633 634 /* pd and sr */ 635 #define LPDDR3_TXP (7) /* tXP, max(3tCK,7.5ns) */ 636 #define LPDDR3_TXPDLL (0) 637 #define LPDDR3_TCKE (7) /* tCKE, (max 7.5ns,3 tCK) */ 638 #define LPDDR3_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 639 #define LPDDR3_TCKSRE (2) /* tCKSRE=tCPDED, 2 tCK */ 640 #define LPDDR3_TCKSRX (2) /* tCKSRX, 2 tCK */ 641 642 /* mode register timing */ 643 #define LPDDR3_TMOD (0) 644 #define LPDDR3_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 645 #define LPDDR3_TMRR (4) /* tMRR, 4 tCK */ 646 #define LPDDR3_TMRRI LPDDR3_TRCD 647 648 /* ODT */ 649 #define LPDDR3_TODTON (3) /* 3.5ns */ 650 651 /* ZQ */ 652 #define LPDDR3_TZQINIT (1000) /* 1us */ 653 #define LPDDR3_TZQCS (90) /* tZQCS, 90ns */ 654 #define LPDDR3_TZQCL (360) /* 360ns */ 655 #define LPDDR3_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 656 /* write leveling */ 657 #define LPDDR3_TWLMRD (40) /* ns */ 658 #define LPDDR3_TWLO (20) /* ns */ 659 #define LPDDR3_TWLDQSEN (25) /* ns */ 660 /* CA training */ 661 #define LPDDR3_TCACKEL (10) /* tCK */ 662 #define LPDDR3_TCAENT (10) /* tCK */ 663 #define LPDDR3_TCAMRD (20) /* tCK */ 664 #define LPDDR3_TCACKEH (10) /* tCK */ 665 #define LPDDR3_TCAEXT (10) /* tCK */ 666 #define LPDDR3_TADR (20) /* ns */ 667 #define LPDDR3_TMRZ (3) /* ns */ 668 669 /* FSP */ 670 #define LPDDR3_TFC_LONG (250) /* ns */ 671 672 /* 673 * Description: depend on input parameter "timing_config", 674 * and calculate all lpddr3 675 * spec timing to "pdram_timing" 676 * parameters: 677 * input: timing_config 678 * output: pdram_timing 679 */ 680 static void lpddr3_get_parameter(struct timing_related_config *timing_config, 681 struct dram_timing_t *pdram_timing) 682 { 683 uint32_t nmhz = timing_config->freq; 684 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 685 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 686 687 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 688 pdram_timing->mhz = nmhz; 689 pdram_timing->al = 0; 690 pdram_timing->bl = timing_config->bl; 691 692 /* 693 * Only support Write Latency Set A here 694 * 1066 933 800 733 667 600 533 400 166 695 * RL, 16 14 12 11 10 9 8 6 3 696 * WL, 8 8 6 6 6 5 4 3 1 697 */ 698 if (nmhz <= 400) { 699 pdram_timing->cl = 6; 700 pdram_timing->cwl = 3; 701 pdram_timing->mr[2] = LPDDR3_RL6_WL3; 702 } else if (nmhz <= 533) { 703 pdram_timing->cl = 8; 704 pdram_timing->cwl = 4; 705 pdram_timing->mr[2] = LPDDR3_RL8_WL4; 706 } else if (nmhz <= 600) { 707 pdram_timing->cl = 9; 708 pdram_timing->cwl = 5; 709 pdram_timing->mr[2] = LPDDR3_RL9_WL5; 710 } else if (nmhz <= 667) { 711 pdram_timing->cl = 10; 712 pdram_timing->cwl = 6; 713 pdram_timing->mr[2] = LPDDR3_RL10_WL6; 714 } else if (nmhz <= 733) { 715 pdram_timing->cl = 11; 716 pdram_timing->cwl = 6; 717 pdram_timing->mr[2] = LPDDR3_RL11_WL6; 718 } else if (nmhz <= 800) { 719 pdram_timing->cl = 12; 720 pdram_timing->cwl = 6; 721 pdram_timing->mr[2] = LPDDR3_RL12_WL6; 722 } else if (nmhz <= 933) { 723 pdram_timing->cl = 14; 724 pdram_timing->cwl = 8; 725 pdram_timing->mr[2] = LPDDR3_RL14_WL8; 726 } else { 727 pdram_timing->cl = 16; 728 pdram_timing->cwl = 8; 729 pdram_timing->mr[2] = LPDDR3_RL16_WL8; 730 } 731 switch (timing_config->dramds) { 732 case 80: 733 pdram_timing->mr[3] = LPDDR3_DS_80; 734 break; 735 case 60: 736 pdram_timing->mr[3] = LPDDR3_DS_60; 737 break; 738 case 48: 739 pdram_timing->mr[3] = LPDDR3_DS_48; 740 break; 741 case 40: 742 pdram_timing->mr[3] = LPDDR3_DS_40; 743 break; 744 case 3440: 745 pdram_timing->mr[3] = LPDDR3_DS_34D_40U; 746 break; 747 case 4048: 748 pdram_timing->mr[3] = LPDDR3_DS_40D_48U; 749 break; 750 case 3448: 751 pdram_timing->mr[3] = LPDDR3_DS_34D_48U; 752 break; 753 case 34: 754 default: 755 pdram_timing->mr[3] = LPDDR3_DS_34; 756 break; 757 } 758 pdram_timing->mr[0] = 0; 759 if (timing_config->odt) 760 switch (timing_config->dramodt) { 761 case 60: 762 pdram_timing->mr11 = LPDDR3_ODT_60; 763 break; 764 case 120: 765 pdram_timing->mr11 = LPDDR3_ODT_120; 766 break; 767 case 240: 768 default: 769 pdram_timing->mr11 = LPDDR3_ODT_240; 770 break; 771 } 772 else 773 pdram_timing->mr11 = LPDDR3_ODT_DIS; 774 775 pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; 776 pdram_timing->tinit2 = LPDDR3_TINIT2; 777 pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000; 778 pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000; 779 pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000; 780 pdram_timing->trstl = LPDDR3_TRSTL; 781 pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000; 782 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 783 pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000; 784 /* base timing */ 785 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 786 pdram_timing->trcd = max(3, tmp); 787 trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000); 788 trppb_tmp = max(3, trppb_tmp); 789 pdram_timing->trppb = trppb_tmp; 790 trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000); 791 trp_tmp = max(3, trp_tmp); 792 pdram_timing->trp = trp_tmp; 793 twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000); 794 twr_tmp = max(4, twr_tmp); 795 pdram_timing->twr = twr_tmp; 796 if (twr_tmp <= 6) 797 twr_tmp = 6; 798 else if (twr_tmp <= 8) 799 twr_tmp = 8; 800 else if (twr_tmp <= 12) 801 twr_tmp = twr_tmp; 802 else if (twr_tmp <= 14) 803 twr_tmp = 14; 804 else 805 twr_tmp = 16; 806 if (twr_tmp > 9) 807 pdram_timing->mr[2] |= (1 << 4); /*enable nWR > 9*/ 808 twr_tmp = (twr_tmp > 9) ? (twr_tmp - 10) : (twr_tmp - 2); 809 bl_tmp = LPDDR3_BL8; 810 pdram_timing->mr[1] = bl_tmp | LPDDR3_N_WR(twr_tmp); 811 tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 812 pdram_timing->trtp = max(4, tmp); 813 tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000); 814 tras_tmp = max(3, tras_tmp); 815 pdram_timing->tras_min = tras_tmp; 816 pdram_timing->trc = (tras_tmp + trp_tmp); 817 tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000); 818 pdram_timing->trrd = max(2, tmp); 819 pdram_timing->tccd = LPDDR3_TCCD; 820 tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 821 pdram_timing->twtr = max(4, tmp); 822 pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000); 823 pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000); 824 tmp = (LPDDR3_TFAW * nmhz + 999) / 1000; 825 pdram_timing->tfaw = max(8, tmp); 826 if (ddr_capability_per_die > 0x20000000) { 827 pdram_timing->trfc = 828 (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000; 829 tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 830 } else { 831 pdram_timing->trfc = 832 (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000; 833 tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 834 } 835 pdram_timing->txsr = max(2, tmp); 836 pdram_timing->txsnr = max(2, tmp); 837 /* tdqsck use rounded down */ 838 pdram_timing->tdqsck = 839 ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1)) 840 / 1000); 841 pdram_timing->tdqsck_max = 842 ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 843 / 1000); 844 /*pd and sr*/ 845 tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 846 pdram_timing->txp = max(3, tmp); 847 pdram_timing->txpdll = LPDDR3_TXPDLL; 848 tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 849 pdram_timing->tcke = max(3, tmp); 850 tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000); 851 pdram_timing->tckesr = max(3, tmp); 852 pdram_timing->tcksre = LPDDR3_TCKSRE; 853 pdram_timing->tcksrx = LPDDR3_TCKSRX; 854 /*mode register timing*/ 855 pdram_timing->tmod = LPDDR3_TMOD; 856 tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000); 857 pdram_timing->tmrd = max(10, tmp); 858 pdram_timing->tmrr = LPDDR3_TMRR; 859 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 860 pdram_timing->tmrri = max(3, tmp); 861 /* ODT */ 862 pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999) 863 / 1000; 864 /* ZQ */ 865 pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000; 866 pdram_timing->tzqcs = 867 ((LPDDR3_TZQCS * nmhz + 999) / 1000); 868 pdram_timing->tzqoper = 869 ((LPDDR3_TZQCL * nmhz + 999) / 1000); 870 tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000); 871 pdram_timing->tzqreset = max(3, tmp); 872 /* write leveling */ 873 pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000; 874 pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000; 875 pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000; 876 /* CA training */ 877 pdram_timing->tcackel = LPDDR3_TCACKEL; 878 pdram_timing->tcaent = LPDDR3_TCAENT; 879 pdram_timing->tcamrd = LPDDR3_TCAMRD; 880 pdram_timing->tcackeh = LPDDR3_TCACKEH; 881 pdram_timing->tcaext = LPDDR3_TCAEXT; 882 pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; 883 pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; 884 pdram_timing->tcacd = pdram_timing->tadr + 2; 885 886 /* FSP */ 887 pdram_timing->tfc_long = (LPDDR3_TFC_LONG * nmhz + 999) / 1000; 888 } 889 890 #define LPDDR4_TINIT1 (200000) /* 200us */ 891 #define LPDDR4_TINIT2 (10) /* 10ns */ 892 #define LPDDR4_TINIT3 (2000000) /* 2ms */ 893 #define LPDDR4_TINIT4 (5) /* tCK */ 894 #define LPDDR4_TINIT5 (2000) /* 2us */ 895 #define LPDDR4_TRSTL LPDDR4_TINIT1 896 #define LPDDR4_TRSTH LPDDR4_TINIT3 897 #define LPDDR4_TREFI_3_9_US (3900) /* 3.9us */ 898 899 /* base timging */ 900 #define LPDDR4_TRCD (18) /* tRCD, max(18ns,4tCK) */ 901 #define LPDDR4_TRP_PB (18) /* tRPpb, max(18ns, 4tCK) */ 902 #define LPDDR4_TRP_AB (21) /* tRPab, max(21ns, 4tCK) */ 903 #define LPDDR4_TRRD (10) /* tRRD, max(4tCK,10ns) */ 904 #define LPDDR4_TCCD_BL16 (8) /* tCK */ 905 #define LPDDR4_TCCD_BL32 (16) /* tCK */ 906 #define LPDDR4_TWTR (10) /* tWTR, max(8tCK, 10ns) */ 907 #define LPDDR4_TRTW (0) /* tCK register min valid value */ 908 #define LPDDR4_TRAS_MAX (70000) /* 70us */ 909 #define LPDDR4_TRAS (42) /* tRAS, max(3tCK,42ns) */ 910 #define LPDDR4_TFAW (40) /* tFAW,min 40ns) */ 911 #define LPDDR4_TRFC_12GBIT (280) /* tRFC, 280ns(>=12Gb) */ 912 #define LPDDR4_TRFC_6GBIT (180) /* 6Gb/8Gb 180ns */ 913 #define LPDDR4_TRFC_4GBIT (130) /* 4Gb 130ns */ 914 #define LPDDR4_TDQSCK_MIN (1) /* tDQSCKmin,1.5ns */ 915 #define LPDDR4_TDQSCK_MAX (3) /* tDQSCKmax,3.5ns */ 916 #define LPDDR4_TPPD (4) /* tCK */ 917 918 /* pd and sr */ 919 #define LPDDR4_TXP (7) /* tXP, max(5tCK,7.5ns) */ 920 #define LPDDR4_TCKE (7) /* tCKE, max(7.5ns,4 tCK) */ 921 #define LPDDR4_TESCKE (1) /* tESCKE, max(1.75ns, 3tCK) */ 922 #define LPDDR4_TSR (15) /* tSR, max(15ns, 3tCK) */ 923 #define LPDDR4_TCMDCKE (1) /* max(1.75ns, 3tCK) */ 924 #define LPDDR4_TCSCKE (1) /* 1.75ns */ 925 #define LPDDR4_TCKELCS (5) /* max(5ns, 5tCK) */ 926 #define LPDDR4_TCSCKEH (1) /* 1.75ns */ 927 #define LPDDR4_TCKEHCS (7) /* max(7.5ns, 5tCK) */ 928 #define LPDDR4_TMRWCKEL (14) /* max(14ns, 10tCK) */ 929 #define LPDDR4_TCKELCMD (7) /* max(7.5ns, 3tCK) */ 930 #define LPDDR4_TCKEHCMD (7) /* max(7.5ns, 3tCK) */ 931 #define LPDDR4_TCKELPD (7) /* max(7.5ns, 3tCK) */ 932 #define LPDDR4_TCKCKEL (7) /* max(7.5ns, 3tCK) */ 933 934 /* mode register timing */ 935 #define LPDDR4_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 936 #define LPDDR4_TMRR (8) /* tMRR, 8 tCK */ 937 938 /* ODT */ 939 #define LPDDR4_TODTON (3) /* 3.5ns */ 940 941 /* ZQ */ 942 #define LPDDR4_TZQCAL (1000) /* 1us */ 943 #define LPDDR4_TZQLAT (30) /* tZQLAT, max(30ns,8tCK) */ 944 #define LPDDR4_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 945 #define LPDDR4_TZQCKE (1) /* tZQCKE, max(1.75ns, 3tCK) */ 946 947 /* write leveling */ 948 #define LPDDR4_TWLMRD (40) /* tCK */ 949 #define LPDDR4_TWLO (20) /* ns */ 950 #define LPDDR4_TWLDQSEN (20) /* tCK */ 951 952 /* CA training */ 953 #define LPDDR4_TCAENT (250) /* ns */ 954 #define LPDDR4_TADR (20) /* ns */ 955 #define LPDDR4_TMRZ (1) /* 1.5ns */ 956 #define LPDDR4_TVREF_LONG (250) /* ns */ 957 #define LPDDR4_TVREF_SHORT (100) /* ns */ 958 959 /* VRCG */ 960 #define LPDDR4_TVRCG_ENABLE (200) /* ns */ 961 #define LPDDR4_TVRCG_DISABLE (100) /* ns */ 962 963 /* FSP */ 964 #define LPDDR4_TFC_LONG (250) /* ns */ 965 #define LPDDR4_TCKFSPE (7) /* max(7.5ns, 4tCK) */ 966 #define LPDDR4_TCKFSPX (7) /* max(7.5ns, 4tCK) */ 967 968 /* 969 * Description: depend on input parameter "timing_config", 970 * and calculate all lpddr4 971 * spec timing to "pdram_timing" 972 * parameters: 973 * input: timing_config 974 * output: pdram_timing 975 */ 976 static void lpddr4_get_parameter(struct timing_related_config *timing_config, 977 struct dram_timing_t *pdram_timing) 978 { 979 uint32_t nmhz = timing_config->freq; 980 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 981 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp; 982 983 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 984 pdram_timing->mhz = nmhz; 985 pdram_timing->al = 0; 986 pdram_timing->bl = timing_config->bl; 987 988 /* 989 * Only support Write Latency Set A here 990 * 2133 1866 1600 1333 1066 800 533 266 991 * RL, 36 32 28 24 20 14 10 6 992 * WL, 18 16 14 12 10 8 6 4 993 * nWR, 40 34 30 24 20 16 10 6 994 * nRTP,16 14 12 10 8 8 8 8 995 */ 996 tmp = (timing_config->bl == 32) ? 1 : 0; 997 998 /* 999 * we always use WR preamble = 2tCK 1000 * RD preamble = Static 1001 */ 1002 tmp |= (1 << 2); 1003 if (nmhz <= 266) { 1004 pdram_timing->cl = 6; 1005 pdram_timing->cwl = 4; 1006 pdram_timing->twr = 6; 1007 pdram_timing->trtp = 8; 1008 pdram_timing->mr[2] = LPDDR4_RL6_NRTP8 | LPDDR4_A_WL4; 1009 } else if (nmhz <= 533) { 1010 if (timing_config->rdbi) { 1011 pdram_timing->cl = 12; 1012 pdram_timing->mr[2] = LPDDR4_RL12_NRTP8 | LPDDR4_A_WL6; 1013 } else { 1014 pdram_timing->cl = 10; 1015 pdram_timing->mr[2] = LPDDR4_RL10_NRTP8 | LPDDR4_A_WL6; 1016 } 1017 pdram_timing->cwl = 6; 1018 pdram_timing->twr = 10; 1019 pdram_timing->trtp = 8; 1020 tmp |= (1 << 4); 1021 } else if (nmhz <= 800) { 1022 if (timing_config->rdbi) { 1023 pdram_timing->cl = 16; 1024 pdram_timing->mr[2] = LPDDR4_RL16_NRTP8 | LPDDR4_A_WL8; 1025 } else { 1026 pdram_timing->cl = 14; 1027 pdram_timing->mr[2] = LPDDR4_RL14_NRTP8 | LPDDR4_A_WL8; 1028 } 1029 pdram_timing->cwl = 8; 1030 pdram_timing->twr = 16; 1031 pdram_timing->trtp = 8; 1032 tmp |= (2 << 4); 1033 } else if (nmhz <= 1066) { 1034 if (timing_config->rdbi) { 1035 pdram_timing->cl = 22; 1036 pdram_timing->mr[2] = LPDDR4_RL22_NRTP8 | LPDDR4_A_WL10; 1037 } else { 1038 pdram_timing->cl = 20; 1039 pdram_timing->mr[2] = LPDDR4_RL20_NRTP8 | LPDDR4_A_WL10; 1040 } 1041 pdram_timing->cwl = 10; 1042 pdram_timing->twr = 20; 1043 pdram_timing->trtp = 8; 1044 tmp |= (3 << 4); 1045 } else if (nmhz <= 1333) { 1046 if (timing_config->rdbi) { 1047 pdram_timing->cl = 28; 1048 pdram_timing->mr[2] = LPDDR4_RL28_NRTP10 | 1049 LPDDR4_A_WL12; 1050 } else { 1051 pdram_timing->cl = 24; 1052 pdram_timing->mr[2] = LPDDR4_RL24_NRTP10 | 1053 LPDDR4_A_WL12; 1054 } 1055 pdram_timing->cwl = 12; 1056 pdram_timing->twr = 24; 1057 pdram_timing->trtp = 10; 1058 tmp |= (4 << 4); 1059 } else if (nmhz <= 1600) { 1060 if (timing_config->rdbi) { 1061 pdram_timing->cl = 32; 1062 pdram_timing->mr[2] = LPDDR4_RL32_NRTP12 | 1063 LPDDR4_A_WL14; 1064 } else { 1065 pdram_timing->cl = 28; 1066 pdram_timing->mr[2] = LPDDR4_RL28_NRTP12 | 1067 LPDDR4_A_WL14; 1068 } 1069 pdram_timing->cwl = 14; 1070 pdram_timing->twr = 30; 1071 pdram_timing->trtp = 12; 1072 tmp |= (5 << 4); 1073 } else if (nmhz <= 1866) { 1074 if (timing_config->rdbi) { 1075 pdram_timing->cl = 36; 1076 pdram_timing->mr[2] = LPDDR4_RL36_NRTP14 | 1077 LPDDR4_A_WL16; 1078 } else { 1079 pdram_timing->cl = 32; 1080 pdram_timing->mr[2] = LPDDR4_RL32_NRTP14 | 1081 LPDDR4_A_WL16; 1082 } 1083 pdram_timing->cwl = 16; 1084 pdram_timing->twr = 34; 1085 pdram_timing->trtp = 14; 1086 tmp |= (6 << 4); 1087 } else { 1088 if (timing_config->rdbi) { 1089 pdram_timing->cl = 40; 1090 pdram_timing->mr[2] = LPDDR4_RL40_NRTP16 | 1091 LPDDR4_A_WL18; 1092 } else { 1093 pdram_timing->cl = 36; 1094 pdram_timing->mr[2] = LPDDR4_RL36_NRTP16 | 1095 LPDDR4_A_WL18; 1096 } 1097 pdram_timing->cwl = 18; 1098 pdram_timing->twr = 40; 1099 pdram_timing->trtp = 16; 1100 tmp |= (7 << 4); 1101 } 1102 pdram_timing->mr[1] = tmp; 1103 tmp = (timing_config->rdbi ? LPDDR4_DBI_RD_EN : 0) | 1104 (timing_config->wdbi ? LPDDR4_DBI_WR_EN : 0); 1105 switch (timing_config->dramds) { 1106 case 240: 1107 pdram_timing->mr[3] = LPDDR4_PDDS_240 | tmp; 1108 break; 1109 case 120: 1110 pdram_timing->mr[3] = LPDDR4_PDDS_120 | tmp; 1111 break; 1112 case 80: 1113 pdram_timing->mr[3] = LPDDR4_PDDS_80 | tmp; 1114 break; 1115 case 60: 1116 pdram_timing->mr[3] = LPDDR4_PDDS_60 | tmp; 1117 break; 1118 case 48: 1119 pdram_timing->mr[3] = LPDDR4_PDDS_48 | tmp; 1120 break; 1121 case 40: 1122 default: 1123 pdram_timing->mr[3] = LPDDR4_PDDS_40 | tmp; 1124 break; 1125 } 1126 pdram_timing->mr[0] = 0; 1127 if (timing_config->odt) { 1128 switch (timing_config->dramodt) { 1129 case 240: 1130 tmp = LPDDR4_DQODT_240; 1131 break; 1132 case 120: 1133 tmp = LPDDR4_DQODT_120; 1134 break; 1135 case 80: 1136 tmp = LPDDR4_DQODT_80; 1137 break; 1138 case 60: 1139 tmp = LPDDR4_DQODT_60; 1140 break; 1141 case 48: 1142 tmp = LPDDR4_DQODT_48; 1143 break; 1144 case 40: 1145 default: 1146 tmp = LPDDR4_DQODT_40; 1147 break; 1148 } 1149 1150 switch (timing_config->caodt) { 1151 case 240: 1152 pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; 1153 break; 1154 case 120: 1155 pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; 1156 break; 1157 case 80: 1158 pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; 1159 break; 1160 case 60: 1161 pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; 1162 break; 1163 case 48: 1164 pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; 1165 break; 1166 case 40: 1167 default: 1168 pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; 1169 break; 1170 } 1171 } else { 1172 pdram_timing->mr11 = LPDDR4_CAODT_DIS | tmp; 1173 } 1174 1175 pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; 1176 pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000; 1177 pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000; 1178 pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000; 1179 pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000; 1180 pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000; 1181 pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000; 1182 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 1183 pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000; 1184 /* base timing */ 1185 tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000); 1186 pdram_timing->trcd = max(4, tmp); 1187 trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000); 1188 trppb_tmp = max(4, trppb_tmp); 1189 pdram_timing->trppb = trppb_tmp; 1190 trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000); 1191 trp_tmp = max(4, trp_tmp); 1192 pdram_timing->trp = trp_tmp; 1193 tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000); 1194 tras_tmp = max(3, tras_tmp); 1195 pdram_timing->tras_min = tras_tmp; 1196 pdram_timing->trc = (tras_tmp + trp_tmp); 1197 tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000); 1198 pdram_timing->trrd = max(4, tmp); 1199 if (timing_config->bl == 32) 1200 pdram_timing->tccd = LPDDR4_TCCD_BL16; 1201 else 1202 pdram_timing->tccd = LPDDR4_TCCD_BL32; 1203 pdram_timing->tccdmw = 4 * pdram_timing->tccd; 1204 tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000); 1205 pdram_timing->twtr = max(8, tmp); 1206 pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000); 1207 pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000); 1208 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000; 1209 if (ddr_capability_per_die > 0x60000000) { 1210 /* >= 12Gb */ 1211 pdram_timing->trfc = 1212 (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000; 1213 tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) + 1214 999) / 1000); 1215 } else if (ddr_capability_per_die > 0x30000000) { 1216 pdram_timing->trfc = 1217 (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000; 1218 tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) + 1219 999) / 1000); 1220 } else { 1221 pdram_timing->trfc = 1222 (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000; 1223 tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) + 1224 999) / 1000); 1225 } 1226 pdram_timing->txsr = max(2, tmp); 1227 pdram_timing->txsnr = max(2, tmp); 1228 /* tdqsck use rounded down */ 1229 pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz + 1230 (nmhz >> 1)) / 1000); 1231 pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz + 1232 (nmhz >> 1) + 999) / 1000); 1233 pdram_timing->tppd = LPDDR4_TPPD; 1234 /* pd and sr */ 1235 tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 1236 pdram_timing->txp = max(5, tmp); 1237 tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 1238 pdram_timing->tcke = max(4, tmp); 1239 tmp = ((LPDDR4_TESCKE * nmhz + 1240 ((nmhz * 3) / 4) + 1241 999) / 1000); 1242 pdram_timing->tescke = max(3, tmp); 1243 tmp = ((LPDDR4_TSR * nmhz + 999) / 1000); 1244 pdram_timing->tsr = max(3, tmp); 1245 tmp = ((LPDDR4_TCMDCKE * nmhz + 1246 ((nmhz * 3) / 4) + 1247 999) / 1000); 1248 pdram_timing->tcmdcke = max(3, tmp); 1249 pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz + 1250 ((nmhz * 3) / 4) + 1251 999) / 1000); 1252 tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000); 1253 pdram_timing->tckelcs = max(5, tmp); 1254 pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz + 1255 ((nmhz * 3) / 4) + 1256 999) / 1000); 1257 tmp = ((LPDDR4_TCKEHCS * nmhz + 1258 (nmhz >> 1) + 999) / 1000); 1259 pdram_timing->tckehcs = max(5, tmp); 1260 tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000); 1261 pdram_timing->tmrwckel = max(10, tmp); 1262 tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) + 1263 999) / 1000); 1264 pdram_timing->tckelcmd = max(3, tmp); 1265 tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) + 1266 999) / 1000); 1267 pdram_timing->tckehcmd = max(3, tmp); 1268 tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) + 1269 999) / 1000); 1270 pdram_timing->tckelpd = max(3, tmp); 1271 tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) + 1272 999) / 1000); 1273 pdram_timing->tckckel = max(3, tmp); 1274 /* mode register timing */ 1275 tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000); 1276 pdram_timing->tmrd = max(10, tmp); 1277 pdram_timing->tmrr = LPDDR4_TMRR; 1278 pdram_timing->tmrri = pdram_timing->trcd + 3; 1279 /* ODT */ 1280 pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999) 1281 / 1000; 1282 /* ZQ */ 1283 pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000; 1284 tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000); 1285 pdram_timing->tzqlat = max(8, tmp); 1286 tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000); 1287 pdram_timing->tzqreset = max(3, tmp); 1288 tmp = ((LPDDR4_TZQCKE * nmhz + 1289 ((nmhz * 3) / 4) + 1290 999) / 1000); 1291 pdram_timing->tzqcke = max(3, tmp); 1292 /* write leveling */ 1293 pdram_timing->twlmrd = LPDDR4_TWLMRD; 1294 pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000; 1295 pdram_timing->twldqsen = LPDDR4_TWLDQSEN; 1296 /* CA training */ 1297 pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000; 1298 pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000; 1299 pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000; 1300 pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000; 1301 pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000; 1302 /* VRCG */ 1303 pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz + 1304 999) / 1000; 1305 pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz + 1306 999) / 1000; 1307 /* FSP */ 1308 pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000; 1309 tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000; 1310 pdram_timing->tckfspe = max(4, tmp); 1311 tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000; 1312 pdram_timing->tckfspx = max(4, tmp); 1313 } 1314 1315 /* 1316 * Description: depend on input parameter "timing_config", 1317 * and calculate correspond "dram_type" 1318 * spec timing to "pdram_timing" 1319 * parameters: 1320 * input: timing_config 1321 * output: pdram_timing 1322 * NOTE: MR ODT is set, need to disable by controller 1323 */ 1324 void dram_get_parameter(struct timing_related_config *timing_config, 1325 struct dram_timing_t *pdram_timing) 1326 { 1327 switch (timing_config->dram_type) { 1328 case DDR3: 1329 ddr3_get_parameter(timing_config, pdram_timing); 1330 break; 1331 case LPDDR2: 1332 lpddr2_get_parameter(timing_config, pdram_timing); 1333 break; 1334 case LPDDR3: 1335 lpddr3_get_parameter(timing_config, pdram_timing); 1336 break; 1337 case LPDDR4: 1338 lpddr4_get_parameter(timing_config, pdram_timing); 1339 break; 1340 } 1341 } 1342