xref: /rk3399_ARM-atf/plat/rockchip/common/bl31_plat_setup.c (revision 0d5ec955b8f7900ca33abf88638d499742531159)
1 /*
2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * Redistributions of source code must retain the above copyright notice, this
8  * list of conditions and the following disclaimer.
9  *
10  * Redistributions in binary form must reproduce the above copyright notice,
11  * this list of conditions and the following disclaimer in the documentation
12  * and/or other materials provided with the distribution.
13  *
14  * Neither the name of ARM nor the names of its contributors may be used
15  * to endorse or promote products derived from this software without specific
16  * prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <arm_gic.h>
32 #include <assert.h>
33 #include <bl_common.h>
34 #include <console.h>
35 #include <debug.h>
36 #include <generic_delay_timer.h>
37 #include <mmio.h>
38 #include <platform.h>
39 #include <plat_private.h>
40 #include <platform_def.h>
41 
42 /*******************************************************************************
43  * Declarations of linker defined symbols which will help us find the layout
44  * of trusted SRAM
45  ******************************************************************************/
46 unsigned long __RO_START__;
47 unsigned long __RO_END__;
48 
49 /*
50  * The next 2 constants identify the extents of the code & RO data region.
51  * These addresses are used by the MMU setup code and therefore they must be
52  * page-aligned.  It is the responsibility of the linker script to ensure that
53  * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
54  */
55 #define BL31_RO_BASE (unsigned long)(&__RO_START__)
56 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
57 
58 static entry_point_info_t bl32_ep_info;
59 static entry_point_info_t bl33_ep_info;
60 
61 /*******************************************************************************
62  * Return a pointer to the 'entry_point_info' structure of the next image for
63  * the security state specified. BL33 corresponds to the non-secure image type
64  * while BL32 corresponds to the secure image type. A NULL pointer is returned
65  * if the image does not exist.
66  ******************************************************************************/
67 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
68 {
69 	entry_point_info_t *next_image_info;
70 
71 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
72 
73 	/* None of the images on this platform can have 0x0 as the entrypoint */
74 	if (next_image_info->pc)
75 		return next_image_info;
76 	else
77 		return NULL;
78 }
79 
80 #pragma weak params_early_setup
81 void params_early_setup(void *plat_param_from_bl2)
82 {
83 }
84 
85 /*******************************************************************************
86  * Perform any BL3-1 early platform setup. Here is an opportunity to copy
87  * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
88  * are lost (potentially). This needs to be done before the MMU is initialized
89  * so that the memory layout can be used while creating page tables.
90  * BL2 has flushed this information to memory, so we are guaranteed to pick up
91  * good data.
92  ******************************************************************************/
93 void bl31_early_platform_setup(bl31_params_t *from_bl2,
94 			       void *plat_params_from_bl2)
95 {
96 	console_init(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK,
97 		     PLAT_RK_UART_BAUDRATE);
98 
99 	VERBOSE("bl31_setup\n");
100 
101 	/* Passing a NULL context is a critical programming error */
102 	assert(from_bl2);
103 
104 	assert(from_bl2->h.type == PARAM_BL31);
105 	assert(from_bl2->h.version >= VERSION_1);
106 
107 	bl32_ep_info = *from_bl2->bl32_ep_info;
108 	bl33_ep_info = *from_bl2->bl33_ep_info;
109 
110 	plat_rockchip_pmusram_prepare();
111 
112 	/* there may have some board sepcific message need to initialize */
113 	params_early_setup(plat_params_from_bl2);
114 }
115 
116 /*******************************************************************************
117  * Perform any BL3-1 platform setup code
118  ******************************************************************************/
119 void bl31_platform_setup(void)
120 {
121 	generic_delay_timer_init();
122 	plat_rockchip_soc_init();
123 
124 	/* Initialize the gic cpu and distributor interfaces */
125 	plat_rockchip_gic_driver_init();
126 	plat_rockchip_gic_init();
127 	plat_rockchip_pmu_init();
128 }
129 
130 /*******************************************************************************
131  * Perform the very early platform specific architectural setup here. At the
132  * moment this is only intializes the mmu in a quick and dirty way.
133  ******************************************************************************/
134 void bl31_plat_arch_setup(void)
135 {
136 	plat_cci_init();
137 	plat_cci_enable();
138 	plat_configure_mmu_el3(BL31_RO_BASE,
139 			       BL_COHERENT_RAM_END - BL31_RO_BASE,
140 			       BL31_RO_BASE,
141 			       BL31_RO_LIMIT,
142 			       BL_COHERENT_RAM_BASE,
143 			       BL_COHERENT_RAM_END);
144 }
145