1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __MEMCTRLV2_H__ 32 #define __MEMCTRLV2_H__ 33 34 #include <tegra_def.h> 35 36 /******************************************************************************* 37 * StreamID to indicate no SMMU translations (requests to be steered on the 38 * SMMU bypass path) 39 ******************************************************************************/ 40 #define MC_STREAM_ID_MAX 0x7F 41 42 /******************************************************************************* 43 * Stream ID Override Config registers 44 ******************************************************************************/ 45 #define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0 46 #define MC_STREAMID_OVERRIDE_CFG_AFIR 0x70 47 #define MC_STREAMID_OVERRIDE_CFG_HDAR 0xA8 48 #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xB0 49 #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xE0 50 #define MC_STREAMID_OVERRIDE_CFG_SATAR 0xF8 51 #define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138 52 #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158 53 #define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188 54 #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 55 #define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8 56 #define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8 57 #define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8 58 #define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220 59 #define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230 60 #define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238 61 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250 62 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258 63 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260 64 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268 65 #define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0 66 #define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8 67 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0 68 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8 69 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300 70 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308 71 #define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310 72 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318 73 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320 74 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328 75 #define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330 76 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338 77 #define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360 78 #define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368 79 #define MC_STREAMID_OVERRIDE_CFG_VIW 0x390 80 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0 81 #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8 82 #define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0 83 #define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8 84 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0 85 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8 86 #define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400 87 #define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408 88 #define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420 89 #define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428 90 #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430 91 #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438 92 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440 93 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448 94 #define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460 95 #define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468 96 #define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470 97 #define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478 98 #define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480 99 #define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488 100 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490 101 #define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498 102 #define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0 103 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8 104 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0 105 #define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8 106 #define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0 107 #define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8 108 #define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0 109 #define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8 110 #define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0 111 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8 112 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0 113 #define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8 114 #define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500 115 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508 116 #define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510 117 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518 118 119 /******************************************************************************* 120 * Stream ID Security Config registers 121 ******************************************************************************/ 122 #define MC_STREAMID_SECURITY_CFG_PTCR 0x4 123 #define MC_STREAMID_SECURITY_CFG_AFIR 0x74 124 #define MC_STREAMID_SECURITY_CFG_HDAR 0xAC 125 #define MC_STREAMID_SECURITY_CFG_HOST1XDMAR 0xB4 126 #define MC_STREAMID_SECURITY_CFG_NVENCSRD 0xE4 127 #define MC_STREAMID_SECURITY_CFG_SATAR 0xFC 128 #define MC_STREAMID_SECURITY_CFG_HDAW 0x1AC 129 #define MC_STREAMID_SECURITY_CFG_MPCORER 0x13C 130 #define MC_STREAMID_SECURITY_CFG_NVENCSWR 0x15C 131 #define MC_STREAMID_SECURITY_CFG_AFIW 0x18C 132 #define MC_STREAMID_SECURITY_CFG_MPCOREW 0x1CC 133 #define MC_STREAMID_SECURITY_CFG_SATAW 0x1EC 134 #define MC_STREAMID_SECURITY_CFG_ISPRA 0x224 135 #define MC_STREAMID_SECURITY_CFG_ISPWA 0x234 136 #define MC_STREAMID_SECURITY_CFG_ISPWB 0x23C 137 #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR 0x254 138 #define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW 0x25C 139 #define MC_STREAMID_SECURITY_CFG_XUSB_DEVR 0x264 140 #define MC_STREAMID_SECURITY_CFG_XUSB_DEVW 0x26C 141 #define MC_STREAMID_SECURITY_CFG_TSECSRD 0x2A4 142 #define MC_STREAMID_SECURITY_CFG_TSECSWR 0x2AC 143 #define MC_STREAMID_SECURITY_CFG_GPUSRD 0x2C4 144 #define MC_STREAMID_SECURITY_CFG_GPUSWR 0x2CC 145 #define MC_STREAMID_SECURITY_CFG_SDMMCRA 0x304 146 #define MC_STREAMID_SECURITY_CFG_SDMMCRAA 0x30C 147 #define MC_STREAMID_SECURITY_CFG_SDMMCR 0x314 148 #define MC_STREAMID_SECURITY_CFG_SDMMCRAB 0x31C 149 #define MC_STREAMID_SECURITY_CFG_SDMMCWA 0x324 150 #define MC_STREAMID_SECURITY_CFG_SDMMCWAA 0x32C 151 #define MC_STREAMID_SECURITY_CFG_SDMMCW 0x334 152 #define MC_STREAMID_SECURITY_CFG_SDMMCWAB 0x33C 153 #define MC_STREAMID_SECURITY_CFG_VICSRD 0x364 154 #define MC_STREAMID_SECURITY_CFG_VICSWR 0x36C 155 #define MC_STREAMID_SECURITY_CFG_VIW 0x394 156 #define MC_STREAMID_SECURITY_CFG_NVDECSRD 0x3C4 157 #define MC_STREAMID_SECURITY_CFG_NVDECSWR 0x3CC 158 #define MC_STREAMID_SECURITY_CFG_APER 0x3D4 159 #define MC_STREAMID_SECURITY_CFG_APEW 0x3DC 160 #define MC_STREAMID_SECURITY_CFG_NVJPGSRD 0x3F4 161 #define MC_STREAMID_SECURITY_CFG_NVJPGSWR 0x3FC 162 #define MC_STREAMID_SECURITY_CFG_SESRD 0x404 163 #define MC_STREAMID_SECURITY_CFG_SESWR 0x40C 164 #define MC_STREAMID_SECURITY_CFG_ETRR 0x424 165 #define MC_STREAMID_SECURITY_CFG_ETRW 0x42C 166 #define MC_STREAMID_SECURITY_CFG_TSECSRDB 0x434 167 #define MC_STREAMID_SECURITY_CFG_TSECSWRB 0x43C 168 #define MC_STREAMID_SECURITY_CFG_GPUSRD2 0x444 169 #define MC_STREAMID_SECURITY_CFG_GPUSWR2 0x44C 170 #define MC_STREAMID_SECURITY_CFG_AXISR 0x464 171 #define MC_STREAMID_SECURITY_CFG_AXISW 0x46C 172 #define MC_STREAMID_SECURITY_CFG_EQOSR 0x474 173 #define MC_STREAMID_SECURITY_CFG_EQOSW 0x47C 174 #define MC_STREAMID_SECURITY_CFG_UFSHCR 0x484 175 #define MC_STREAMID_SECURITY_CFG_UFSHCW 0x48C 176 #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR 0x494 177 #define MC_STREAMID_SECURITY_CFG_BPMPR 0x49C 178 #define MC_STREAMID_SECURITY_CFG_BPMPW 0x4A4 179 #define MC_STREAMID_SECURITY_CFG_BPMPDMAR 0x4AC 180 #define MC_STREAMID_SECURITY_CFG_BPMPDMAW 0x4B4 181 #define MC_STREAMID_SECURITY_CFG_AONR 0x4BC 182 #define MC_STREAMID_SECURITY_CFG_AONW 0x4C4 183 #define MC_STREAMID_SECURITY_CFG_AONDMAR 0x4CC 184 #define MC_STREAMID_SECURITY_CFG_AONDMAW 0x4D4 185 #define MC_STREAMID_SECURITY_CFG_SCER 0x4DC 186 #define MC_STREAMID_SECURITY_CFG_SCEW 0x4E4 187 #define MC_STREAMID_SECURITY_CFG_SCEDMAR 0x4EC 188 #define MC_STREAMID_SECURITY_CFG_SCEDMAW 0x4F4 189 #define MC_STREAMID_SECURITY_CFG_APEDMAR 0x4FC 190 #define MC_STREAMID_SECURITY_CFG_APEDMAW 0x504 191 #define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1 0x50C 192 #define MC_STREAMID_SECURITY_CFG_VICSRD1 0x514 193 #define MC_STREAMID_SECURITY_CFG_NVDECSRD1 0x51C 194 195 /******************************************************************************* 196 * Memory Controller SMMU Bypass config register 197 ******************************************************************************/ 198 #define MC_SMMU_BYPASS_CONFIG 0x1820 199 #define MC_SMMU_BYPASS_CTRL_MASK 0x3 200 #define MC_SMMU_BYPASS_CTRL_SHIFT 0 201 #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT) 202 #define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT) 203 #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT) 204 #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT) 205 #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31) 206 #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 207 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 208 209 /******************************************************************************* 210 * Memory Controller transaction override config registers 211 ******************************************************************************/ 212 #define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 213 #define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 214 #define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 215 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 216 #define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 217 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 218 #define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 219 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328 220 #define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 221 #define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 222 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0 223 #define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 224 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 225 #define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 226 #define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 227 #define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 228 #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 229 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 230 #define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 231 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 232 #define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 233 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308 234 #define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 235 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 236 #define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 237 #define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 238 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8 239 #define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 240 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 241 #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 242 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440 243 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 244 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448 245 #define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 246 #define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 247 #define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 248 #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 249 #define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 250 #define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 251 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 252 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 253 #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 254 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 255 #define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 256 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 257 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 258 #define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 259 #define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 260 #define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 261 #define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 262 #define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 263 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 264 #define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 265 #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 266 #define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 267 #define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 268 #define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 269 #define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 270 #define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 271 #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 272 #define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070 273 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 274 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 275 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 276 #define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 277 #define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 278 #define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 279 #define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 280 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 281 #define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 282 #define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188 283 #define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 284 285 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0) 286 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4) 287 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12) 288 289 /******************************************************************************* 290 * Non-SO_DEV transactions override values for CGID_TAG bitfield for the 291 * MC_TXN_OVERRIDE_CONFIG_{module} registers 292 ******************************************************************************/ 293 #define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0 294 #define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1 295 #define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2 296 #define MC_TXN_OVERRIDE_CGID_TAG_ADR 3 297 #define MC_TXN_OVERRIDE_CGID_TAG_MASK 3 298 299 #ifndef __ASSEMBLY__ 300 301 #include <sys/types.h> 302 303 /******************************************************************************* 304 * Structure to hold the transaction override settings to use to override 305 * client inputs 306 ******************************************************************************/ 307 typedef struct mc_txn_override_cfg { 308 uint32_t offset; 309 uint8_t cgid_tag; 310 } mc_txn_override_cfg_t; 311 312 #define mc_make_txn_override_cfg(off, val) \ 313 { \ 314 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ 315 .cgid_tag = MC_TXN_OVERRIDE_ ## val \ 316 } 317 318 /******************************************************************************* 319 * Structure to hold the Stream ID to use to override client inputs 320 ******************************************************************************/ 321 typedef struct mc_streamid_override_cfg { 322 uint32_t offset; 323 uint8_t stream_id; 324 } mc_streamid_override_cfg_t; 325 326 /******************************************************************************* 327 * Structure to hold the Stream ID Security Configuration settings 328 ******************************************************************************/ 329 typedef struct mc_streamid_security_cfg { 330 char *name; 331 uint32_t offset; 332 int override_enable; 333 int override_client_inputs; 334 int override_client_ns_flag; 335 } mc_streamid_security_cfg_t; 336 337 #define OVERRIDE_DISABLE 1 338 #define OVERRIDE_ENABLE 0 339 #define CLIENT_FLAG_SECURE 0 340 #define CLIENT_FLAG_NON_SECURE 1 341 #define CLIENT_INPUTS_OVERRIDE 1 342 #define CLIENT_INPUTS_NO_OVERRIDE 0 343 344 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 345 { \ 346 .name = # off, \ 347 .offset = MC_STREAMID_SECURITY_CFG_ ## off, \ 348 .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 349 .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 350 .override_enable = OVERRIDE_ ## access \ 351 } 352 353 #endif /* __ASSEMBLY__ */ 354 355 /******************************************************************************* 356 * TZDRAM carveout configuration registers 357 ******************************************************************************/ 358 #define MC_SECURITY_CFG0_0 0x70 359 #define MC_SECURITY_CFG1_0 0x74 360 #define MC_SECURITY_CFG3_0 0x9BC 361 362 /******************************************************************************* 363 * Video Memory carveout configuration registers 364 ******************************************************************************/ 365 #define MC_VIDEO_PROTECT_BASE_HI 0x978 366 #define MC_VIDEO_PROTECT_BASE_LO 0x648 367 #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 368 369 /******************************************************************************* 370 * TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers 371 ******************************************************************************/ 372 #define MC_TZRAM_BASE_LO 0x2194 373 #define TZRAM_BASE_LO_SHIFT 12 374 #define TZRAM_BASE_LO_MASK 0xFFFFF 375 #define MC_TZRAM_BASE_HI 0x2198 376 #define TZRAM_BASE_HI_SHIFT 0 377 #define TZRAM_BASE_HI_MASK 3 378 #define MC_TZRAM_SIZE 0x219C 379 #define TZRAM_SIZE_RANGE_4KB_SHIFT 27 380 381 #define MC_TZRAM_CARVEOUT_CFG 0x2190 382 #define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) 383 #define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) 384 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 385 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 386 #define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) 387 #define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) 388 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 389 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC 390 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 391 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 392 393 #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8 394 #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC 395 #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0 396 #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4 397 #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8 398 #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC 399 400 /******************************************************************************* 401 * Memory Controller Reset Control registers 402 ******************************************************************************/ 403 #define MC_CLIENT_HOTRESET_CTRL0 0x200 404 #define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0 405 #define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1 << 0) 406 #define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1 << 6) 407 #define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1 << 7) 408 #define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1 << 8) 409 #define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1 << 9) 410 #define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1 << 11) 411 #define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1 << 15) 412 #define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1 << 17) 413 #define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1 << 18) 414 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1 << 19) 415 #define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1 << 20) 416 #define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1 << 22) 417 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1 << 29) 418 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1 << 30) 419 #define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1 << 31) 420 #define MC_CLIENT_HOTRESET_STATUS0 0x204 421 #define MC_CLIENT_HOTRESET_CTRL1 0x970 422 #define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0 423 #define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1 << 0) 424 #define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1 << 2) 425 #define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1 << 5) 426 #define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1 << 6) 427 #define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1 << 7) 428 #define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1 << 8) 429 #define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1 << 12) 430 #define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1 << 13) 431 #define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1 << 18) 432 #define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1 << 19) 433 #define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1 << 20) 434 #define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1 << 21) 435 #define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1 << 22) 436 #define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1 << 23) 437 #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1 << 24) 438 #define MC_CLIENT_HOTRESET_STATUS1 0x974 439 440 /******************************************************************************* 441 * TSA configuration registers 442 ******************************************************************************/ 443 #define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 444 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 445 #define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 446 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 447 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 448 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 449 #define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 450 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 451 #define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 452 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 453 #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 454 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 455 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 456 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 457 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 458 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 459 #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 460 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 461 #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 462 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 463 #define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 464 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 465 #define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 466 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 467 #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 468 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 469 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 470 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 471 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 472 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 473 474 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 475 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 476 477 /******************************************************************************* 478 * Memory Controller's PCFIFO client configuration registers 479 ******************************************************************************/ 480 #define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 481 #define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000 482 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0 << 17) 483 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1 << 17) 484 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0 << 21) 485 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1 << 21) 486 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0 << 29) 487 #define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1 << 29) 488 489 #define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 490 #define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000 491 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0 << 11) 492 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1 << 11) 493 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0 << 13) 494 #define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1 << 13) 495 496 #define MC_PCFIFO_CLIENT_CONFIG3 0xddc 497 #define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0 498 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0 << 7) 499 #define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1 << 7) 500 501 #define MC_PCFIFO_CLIENT_CONFIG4 0xde0 502 #define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0 503 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0 << 1) 504 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1 << 1) 505 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0 << 5) 506 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1 << 5) 507 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0 << 13) 508 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1 << 13) 509 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0 << 15) 510 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1 << 15) 511 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0 << 17) 512 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1 << 17) 513 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0 << 22) 514 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1 << 22) 515 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0 << 26) 516 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1 << 26) 517 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0 << 30) 518 #define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1 << 30) 519 520 #define MC_PCFIFO_CLIENT_CONFIG5 0xbf4 521 #define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0 522 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0 << 0) 523 #define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1 << 0) 524 525 /******************************************************************************* 526 * Memory Controller's SMMU client configuration registers 527 ******************************************************************************/ 528 #define MC_SMMU_CLIENT_CONFIG1 0x44 529 #define MC_SMMU_CLIENT_CONFIG1_RESET_VAL 0x20000 530 #define MC_SMMU_CLIENT_CONFIG1_AFIW_UNORDERED (0 << 17) 531 #define MC_SMMU_CLIENT_CONFIG1_AFIW_MASK (1 << 17) 532 #define MC_SMMU_CLIENT_CONFIG1_HDAW_UNORDERED (0 << 21) 533 #define MC_SMMU_CLIENT_CONFIG1_HDAW_MASK (1 << 21) 534 #define MC_SMMU_CLIENT_CONFIG1_SATAW_UNORDERED (0 << 29) 535 #define MC_SMMU_CLIENT_CONFIG1_SATAW_MASK (1 << 29) 536 537 #define MC_SMMU_CLIENT_CONFIG2 0x48 538 #define MC_SMMU_CLIENT_CONFIG2_RESET_VAL 0x20000 539 #define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_UNORDERED (0 << 11) 540 #define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_MASK (1 << 11) 541 #define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_UNORDERED (0 << 13) 542 #define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_MASK (1 << 13) 543 544 #define MC_SMMU_CLIENT_CONFIG3 0x4c 545 #define MC_SMMU_CLIENT_CONFIG3_RESET_VAL 0 546 #define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_UNORDERED (0 << 7) 547 #define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_MASK (1 << 7) 548 549 #define MC_SMMU_CLIENT_CONFIG4 0xb9c 550 #define MC_SMMU_CLIENT_CONFIG4_RESET_VAL 0 551 #define MC_SMMU_CLIENT_CONFIG4_SESWR_UNORDERED (0 << 1) 552 #define MC_SMMU_CLIENT_CONFIG4_SESWR_MASK (1 << 1) 553 #define MC_SMMU_CLIENT_CONFIG4_ETRW_UNORDERED (0 << 5) 554 #define MC_SMMU_CLIENT_CONFIG4_ETRW_MASK (1 << 5) 555 #define MC_SMMU_CLIENT_CONFIG4_AXISW_UNORDERED (0 << 13) 556 #define MC_SMMU_CLIENT_CONFIG4_AXISW_MASK (1 << 13) 557 #define MC_SMMU_CLIENT_CONFIG4_EQOSW_UNORDERED (0 << 15) 558 #define MC_SMMU_CLIENT_CONFIG4_EQOSW_MASK (1 << 15) 559 #define MC_SMMU_CLIENT_CONFIG4_UFSHCW_UNORDERED (0 << 17) 560 #define MC_SMMU_CLIENT_CONFIG4_UFSHCW_MASK (1 << 17) 561 #define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_UNORDERED (0 << 22) 562 #define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_MASK (1 << 22) 563 #define MC_SMMU_CLIENT_CONFIG4_AONDMAW_UNORDERED (0 << 26) 564 #define MC_SMMU_CLIENT_CONFIG4_AONDMAW_MASK (1 << 26) 565 #define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_UNORDERED (0 << 30) 566 #define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_MASK (1 << 30) 567 568 #define MC_SMMU_CLIENT_CONFIG5 0xbac 569 #define MC_SMMU_CLIENT_CONFIG5_RESET_VAL 0 570 #define MC_SMMU_CLIENT_CONFIG5_APEDMAW_UNORDERED (0 << 0) 571 #define MC_SMMU_CLIENT_CONFIG5_APEDMAW_MASK (1 << 0) 572 573 #ifndef __ASSEMBLY__ 574 575 #include <mmio.h> 576 577 static inline uint32_t tegra_mc_read_32(uint32_t off) 578 { 579 return mmio_read_32(TEGRA_MC_BASE + off); 580 } 581 582 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 583 { 584 mmio_write_32(TEGRA_MC_BASE + off, val); 585 } 586 587 static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 588 { 589 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 590 } 591 592 static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 593 { 594 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 595 } 596 597 #define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ 598 (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 599 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 600 601 #define mc_set_smmu_unordered_boot_so_mss(id, client) \ 602 (~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 603 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 604 605 #define mc_set_tsa_passthrough(client) \ 606 { \ 607 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ 608 (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \ 609 ~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ 610 TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ 611 } 612 613 #define mc_set_forced_coherent_cfg(client) \ 614 { \ 615 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 616 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV); \ 617 } 618 619 #define mc_set_forced_coherent_so_dev_cfg(client) \ 620 { \ 621 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 622 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ 623 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ 624 } 625 626 #define mc_set_forced_coherent_axid_so_dev_cfg(client) \ 627 { \ 628 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 629 MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \ 630 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \ 631 MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \ 632 } 633 #endif /* __ASSMEBLY__ */ 634 635 #endif /* __MEMCTRLV2_H__ */ 636