1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <console.h> 33 #include <debug.h> 34 #include <delay_timer.h> 35 #include <mmio.h> 36 #include <platform_def.h> 37 #include <plat_private.h> 38 #include <ddr_parameter.h> 39 #include <rk3328_def.h> 40 #include <soc.h> 41 42 /* Table of regions to map using the MMU. */ 43 const mmap_region_t plat_rk_mmap[] = { 44 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 47 MT_DEVICE | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE), 50 MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE, 51 MT_DEVICE | MT_RW | MT_SECURE), 52 MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE, 53 MT_DEVICE | MT_RW | MT_SECURE), 54 MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE, 55 MT_DEVICE | MT_RW | MT_SECURE), 56 MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE), 58 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, 61 MT_DEVICE | MT_RW | MT_SECURE), 62 MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE, 63 MT_DEVICE | MT_RW | MT_SECURE), 64 MAP_REGION_FLAT(FIREWALL_CFG_BASE, FIREWALL_CFG_SIZE, 65 MT_DEVICE | MT_RW | MT_SECURE), 66 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 67 MT_DEVICE | MT_RW | MT_SECURE), 68 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE, 69 MT_DEVICE | MT_RW | MT_SECURE), 70 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 71 MT_MEMORY | MT_RW | MT_SECURE), 72 MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE, 73 MT_DEVICE | MT_RW | MT_SECURE), 74 MAP_REGION_FLAT(DDR_GRF_BASE, DDR_GRF_SIZE, 75 MT_DEVICE | MT_RW | MT_SECURE), 76 MAP_REGION_FLAT(DDR_UPCTL_BASE, DDR_UPCTL_SIZE, 77 MT_DEVICE | MT_RW | MT_SECURE), 78 MAP_REGION_FLAT(PWM_BASE, PWM_SIZE, 79 MT_DEVICE | MT_RW | MT_SECURE), 80 MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE, 81 MT_DEVICE | MT_RW | MT_SECURE), 82 MAP_REGION_FLAT(EFUSE8_BASE, EFUSE8_SIZE, 83 MT_DEVICE | MT_RW | MT_SECURE), 84 MAP_REGION_FLAT(EFUSE32_BASE, EFUSE32_SIZE, 85 MT_DEVICE | MT_RW | MT_SECURE), 86 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE, 87 MT_DEVICE | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(SERVER_MSCH_BASE, SERVER_MSCH_SIZE, 89 MT_DEVICE | MT_RW | MT_SECURE), 90 MAP_REGION_FLAT(DDR_MONITOR_BASE, DDR_MONITOR_SIZE, 91 MT_DEVICE | MT_RW | MT_SECURE), 92 MAP_REGION_FLAT(VOP_BASE, VOP_SIZE, 93 MT_DEVICE | MT_RW | MT_SECURE), 94 95 { 0 } 96 }; 97 98 /* The RockChip power domain tree descriptor */ 99 const unsigned char rockchip_power_domain_tree_desc[] = { 100 /* No of root nodes */ 101 PLATFORM_SYSTEM_COUNT, 102 /* No of children for the root node */ 103 PLATFORM_CLUSTER_COUNT, 104 /* No of children for the first cluster node */ 105 PLATFORM_CLUSTER0_CORE_COUNT, 106 }; 107 108 void secure_timer_init(void) 109 { 110 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT0, 0xffffffff); 111 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT1, 0xffffffff); 112 /* auto reload & enable the timer */ 113 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); 114 } 115 116 void sgrf_init(void) 117 { 118 uint32_t i, val; 119 struct param_ddr_usage usg; 120 121 /* general secure regions */ 122 usg = ddr_region_usage_parse(DDR_PARAM_BASE, 123 PLAT_MAX_DDR_CAPACITY_MB); 124 for (i = 0; i < usg.s_nr; i++) { 125 /* enable secure */ 126 val = mmio_read_32(FIREWALL_DDR_BASE + 127 FIREWALL_DDR_FW_DDR_CON_REG); 128 val |= BIT(7 - i); 129 mmio_write_32(FIREWALL_DDR_BASE + 130 FIREWALL_DDR_FW_DDR_CON_REG, val); 131 /* map top and base */ 132 mmio_write_32(FIREWALL_DDR_BASE + 133 FIREWALL_DDR_FW_DDR_RGN(7 - i), 134 RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); 135 } 136 137 /* set ddr rgn0_top and rga0_top as 0 */ 138 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); 139 140 /* set all slave ip into no-secure, except stimer */ 141 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(0), 142 SGRF_SLV_S_ALL_NS); 143 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(1), 144 SGRF_SLV_S_ALL_NS); 145 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(2), 146 SGRF_SLV_S_ALL_NS | STIMER_S); 147 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(3), 148 SGRF_SLV_S_ALL_NS); 149 150 /* set all master ip into no-secure */ 151 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), 0xf0000000); 152 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_MST_S_ALL_NS); 153 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_MST_S_ALL_NS); 154 155 /* set DMAC into no-secure */ 156 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_IRQ_BOOT_NS); 157 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(4), DMA_PERI_CH_NS_15_0); 158 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_PERI_CH_NS_19_16); 159 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_MANAGER_BOOT_NS); 160 161 /* soft reset dma before use */ 162 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ); 163 udelay(5); 164 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS); 165 } 166 167 void plat_rockchip_soc_init(void) 168 { 169 secure_timer_init(); 170 sgrf_init(); 171 172 NOTICE("BL31:Rockchip release version: v%d.%d\n", 173 MAJOR_VERSION, MINOR_VERSION); 174 } 175