1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <mmio.h> 34 #include <m0_ctl.h> 35 #include <plat_private.h> 36 #include "dfs.h" 37 #include "dram.h" 38 #include "dram_spec_timing.h" 39 #include "string.h" 40 #include "soc.h" 41 #include "pmu.h" 42 43 #include <delay_timer.h> 44 45 #define ENPER_CS_TRAINING_FREQ (666) 46 #define TDFI_LAT_THRESHOLD_FREQ (928) 47 #define PHY_DLL_BYPASS_FREQ (260) 48 49 static const struct pll_div dpll_rates_table[] = { 50 51 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 52 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}, 53 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 54 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 55 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 56 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 57 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 58 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 59 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 60 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 61 }; 62 63 struct rk3399_dram_status { 64 uint32_t current_index; 65 uint32_t index_freq[2]; 66 uint32_t boot_freq; 67 uint32_t low_power_stat; 68 struct timing_related_config timing_config; 69 struct drv_odt_lp_config drv_odt_lp_cfg; 70 }; 71 72 struct rk3399_saved_status { 73 uint32_t freq; 74 uint32_t low_power_stat; 75 uint32_t odt; 76 }; 77 78 static struct rk3399_dram_status rk3399_dram_status; 79 static struct rk3399_saved_status rk3399_suspend_status; 80 static uint32_t wrdqs_delay_val[2][2][4]; 81 82 static struct rk3399_sdram_default_config ddr3_default_config = { 83 .bl = 8, 84 .ap = 0, 85 .burst_ref_cnt = 1, 86 .zqcsi = 0 87 }; 88 89 static struct rk3399_sdram_default_config lpddr3_default_config = { 90 .bl = 8, 91 .ap = 0, 92 .burst_ref_cnt = 1, 93 .zqcsi = 0 94 }; 95 96 static struct rk3399_sdram_default_config lpddr4_default_config = { 97 .bl = 16, 98 .ap = 0, 99 .caodt = 240, 100 .burst_ref_cnt = 1, 101 .zqcsi = 0 102 }; 103 104 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 105 uint8_t channel, uint8_t cs) 106 { 107 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 108 uint32_t bandwidth; 109 uint32_t die_bandwidth; 110 uint32_t die; 111 uint32_t cs_cap; 112 uint32_t row; 113 114 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 115 bandwidth = 8 * (1 << ch->bw); 116 die_bandwidth = 8 * (1 << ch->dbw); 117 die = bandwidth / die_bandwidth; 118 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 119 (bandwidth / 16))); 120 if (ch->row_3_4) 121 cs_cap = cs_cap * 3 / 4; 122 123 return (cs_cap / die); 124 } 125 126 static void get_dram_drv_odt_val(uint32_t dram_type, 127 struct drv_odt_lp_config *drv_config) 128 { 129 uint32_t tmp; 130 uint32_t mr1_val, mr3_val, mr11_val; 131 132 switch (dram_type) { 133 case DDR3: 134 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 135 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 136 if (tmp) 137 drv_config->dram_side_drv = 34; 138 else 139 drv_config->dram_side_drv = 40; 140 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 141 ((mr1_val >> 7) & 1); 142 if (tmp == 0) 143 drv_config->dram_side_dq_odt = 0; 144 else if (tmp == 1) 145 drv_config->dram_side_dq_odt = 60; 146 else if (tmp == 3) 147 drv_config->dram_side_dq_odt = 40; 148 else 149 drv_config->dram_side_dq_odt = 120; 150 break; 151 case LPDDR3: 152 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 153 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 154 if (mr3_val == 0xb) 155 drv_config->dram_side_drv = 3448; 156 else if (mr3_val == 0xa) 157 drv_config->dram_side_drv = 4048; 158 else if (mr3_val == 0x9) 159 drv_config->dram_side_drv = 3440; 160 else if (mr3_val == 0x4) 161 drv_config->dram_side_drv = 60; 162 else if (mr3_val == 0x3) 163 drv_config->dram_side_drv = 48; 164 else if (mr3_val == 0x2) 165 drv_config->dram_side_drv = 40; 166 else 167 drv_config->dram_side_drv = 34; 168 169 if (mr11_val == 1) 170 drv_config->dram_side_dq_odt = 60; 171 else if (mr11_val == 2) 172 drv_config->dram_side_dq_odt = 120; 173 else if (mr11_val == 0) 174 drv_config->dram_side_dq_odt = 0; 175 else 176 drv_config->dram_side_dq_odt = 240; 177 break; 178 case LPDDR4: 179 default: 180 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 181 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 182 183 if ((mr3_val == 0) || (mr3_val == 7)) 184 drv_config->dram_side_drv = 40; 185 else 186 drv_config->dram_side_drv = 240 / mr3_val; 187 188 tmp = mr11_val & 0x7; 189 if ((tmp == 7) || (tmp == 0)) 190 drv_config->dram_side_dq_odt = 0; 191 else 192 drv_config->dram_side_dq_odt = 240 / tmp; 193 194 tmp = (mr11_val >> 4) & 0x7; 195 if ((tmp == 7) || (tmp == 0)) 196 drv_config->dram_side_ca_odt = 0; 197 else 198 drv_config->dram_side_ca_odt = 240 / tmp; 199 break; 200 } 201 } 202 203 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 204 struct rk3399_sdram_params *sdram_params, 205 struct drv_odt_lp_config *drv_config) 206 { 207 uint32_t i, j; 208 209 for (i = 0; i < sdram_params->num_channels; i++) { 210 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 211 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 212 for (j = 0; j < sdram_params->ch[i].rank; j++) { 213 ptiming_config->dram_info[i].per_die_capability[j] = 214 get_cs_die_capability(sdram_params, i, j); 215 } 216 } 217 ptiming_config->dram_type = sdram_params->dramtype; 218 ptiming_config->ch_cnt = sdram_params->num_channels; 219 switch (sdram_params->dramtype) { 220 case DDR3: 221 ptiming_config->bl = ddr3_default_config.bl; 222 ptiming_config->ap = ddr3_default_config.ap; 223 break; 224 case LPDDR3: 225 ptiming_config->bl = lpddr3_default_config.bl; 226 ptiming_config->ap = lpddr3_default_config.ap; 227 break; 228 case LPDDR4: 229 ptiming_config->bl = lpddr4_default_config.bl; 230 ptiming_config->ap = lpddr4_default_config.ap; 231 ptiming_config->rdbi = 0; 232 ptiming_config->wdbi = 0; 233 break; 234 } 235 ptiming_config->dramds = drv_config->dram_side_drv; 236 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 237 ptiming_config->caodt = drv_config->dram_side_ca_odt; 238 ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; 239 } 240 241 struct lat_adj_pair { 242 uint32_t cl; 243 uint32_t rdlat_adj; 244 uint32_t cwl; 245 uint32_t wrlat_adj; 246 }; 247 248 const struct lat_adj_pair ddr3_lat_adj[] = { 249 {6, 5, 5, 4}, 250 {8, 7, 6, 5}, 251 {10, 9, 7, 6}, 252 {11, 9, 8, 7}, 253 {13, 0xb, 9, 8}, 254 {14, 0xb, 0xa, 9} 255 }; 256 257 const struct lat_adj_pair lpddr3_lat_adj[] = { 258 {3, 2, 1, 0}, 259 {6, 5, 3, 2}, 260 {8, 7, 4, 3}, 261 {9, 8, 5, 4}, 262 {10, 9, 6, 5}, 263 {11, 9, 6, 5}, 264 {12, 0xa, 6, 5}, 265 {14, 0xc, 8, 7}, 266 {16, 0xd, 8, 7} 267 }; 268 269 const struct lat_adj_pair lpddr4_lat_adj[] = { 270 {6, 5, 4, 2}, 271 {10, 9, 6, 4}, 272 {14, 0xc, 8, 6}, 273 {20, 0x11, 0xa, 8}, 274 {24, 0x15, 0xc, 0xa}, 275 {28, 0x18, 0xe, 0xc}, 276 {32, 0x1b, 0x10, 0xe}, 277 {36, 0x1e, 0x12, 0x10} 278 }; 279 280 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 281 { 282 const struct lat_adj_pair *p; 283 uint32_t cnt; 284 uint32_t i; 285 286 if (dram_type == DDR3) { 287 p = ddr3_lat_adj; 288 cnt = ARRAY_SIZE(ddr3_lat_adj); 289 } else if (dram_type == LPDDR3) { 290 p = lpddr3_lat_adj; 291 cnt = ARRAY_SIZE(lpddr3_lat_adj); 292 } else { 293 p = lpddr4_lat_adj; 294 cnt = ARRAY_SIZE(lpddr4_lat_adj); 295 } 296 297 for (i = 0; i < cnt; i++) { 298 if (cl == p[i].cl) 299 return p[i].rdlat_adj; 300 } 301 /* fail */ 302 return 0xff; 303 } 304 305 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 306 { 307 const struct lat_adj_pair *p; 308 uint32_t cnt; 309 uint32_t i; 310 311 if (dram_type == DDR3) { 312 p = ddr3_lat_adj; 313 cnt = ARRAY_SIZE(ddr3_lat_adj); 314 } else if (dram_type == LPDDR3) { 315 p = lpddr3_lat_adj; 316 cnt = ARRAY_SIZE(lpddr3_lat_adj); 317 } else { 318 p = lpddr4_lat_adj; 319 cnt = ARRAY_SIZE(lpddr4_lat_adj); 320 } 321 322 for (i = 0; i < cnt; i++) { 323 if (cwl == p[i].cwl) 324 return p[i].wrlat_adj; 325 } 326 /* fail */ 327 return 0xff; 328 } 329 330 #define PI_REGS_DIMM_SUPPORT (0) 331 #define PI_ADD_LATENCY (0) 332 #define PI_DOUBLEFREEK (1) 333 334 #define PI_PAD_DELAY_PS_VALUE (1000) 335 #define PI_IE_ENABLE_VALUE (3000) 336 #define PI_TSEL_ENABLE_VALUE (700) 337 338 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 339 { 340 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 341 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 342 extra_adder, tsel_enable; 343 344 ie_enable = PI_IE_ENABLE_VALUE; 345 tsel_enable = PI_TSEL_ENABLE_VALUE; 346 347 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 348 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 349 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 350 delay_adder++; 351 hs_offset = 0; 352 tsel_adder = 0; 353 extra_adder = 0; 354 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 355 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 356 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 357 tsel_adder++; 358 delay_adder = delay_adder - 1; 359 if (tsel_adder > delay_adder) 360 extra_adder = tsel_adder - delay_adder; 361 else 362 extra_adder = 0; 363 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 364 hs_offset = 2; 365 else 366 hs_offset = 1; 367 368 if (delay_adder > (rdlat - 1 - hs_offset)) { 369 rdlat = rdlat - tsel_adder; 370 } else { 371 if ((rdlat - delay_adder) < 2) 372 rdlat = 2; 373 else 374 rdlat = rdlat - delay_adder - extra_adder; 375 } 376 377 return rdlat; 378 } 379 380 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 381 struct timing_related_config *timing_config) 382 { 383 uint32_t tmp; 384 385 if (timing_config->dram_type == LPDDR3) { 386 tmp = pdram_timing->cl; 387 if (tmp >= 14) 388 tmp = 8; 389 else if (tmp >= 10) 390 tmp = 6; 391 else if (tmp == 9) 392 tmp = 5; 393 else if (tmp == 8) 394 tmp = 4; 395 else if (tmp == 6) 396 tmp = 3; 397 else 398 tmp = 1; 399 } else { 400 tmp = 1; 401 } 402 403 return tmp; 404 } 405 406 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 407 struct timing_related_config *timing_config) 408 { 409 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 410 } 411 412 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 413 struct timing_related_config *timing_config) 414 { 415 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 416 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 417 uint32_t mem_delay_ps, round_trip_ps; 418 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 419 420 ie_enable = PI_IE_ENABLE_VALUE; 421 422 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 423 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 424 delay_adder++; 425 delay_adder = delay_adder - 1; 426 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 427 hs_offset = 2; 428 else 429 hs_offset = 1; 430 431 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 432 433 if (delay_adder > (cas_lat - 1 - hs_offset)) { 434 ie_delay_adder = 0; 435 } else { 436 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 437 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 438 ie_delay_adder++; 439 } 440 441 if (timing_config->dram_type == DDR3) { 442 mem_delay_ps = 0; 443 } else if (timing_config->dram_type == LPDDR4) { 444 mem_delay_ps = 3600; 445 } else if (timing_config->dram_type == LPDDR3) { 446 mem_delay_ps = 5500; 447 } else { 448 printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 449 return 0; 450 } 451 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 452 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 453 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 454 delay_adder++; 455 456 phy_internal_delay = 5 + 2 + 4; 457 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 458 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 459 lpddr_adder++; 460 dfi_adder = 0; 461 phy_internal_delay = phy_internal_delay + 2; 462 rdlat_delay = delay_adder + phy_internal_delay + 463 ie_delay_adder + lpddr_adder + dfi_adder; 464 465 rdlat_delay = rdlat_delay + 2; 466 return rdlat_delay; 467 } 468 469 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 470 struct timing_related_config *timing_config) 471 { 472 uint32_t tmp, todtoff_min_ps; 473 474 if (timing_config->dram_type == LPDDR3) 475 todtoff_min_ps = 2500; 476 else if (timing_config->dram_type == LPDDR4) 477 todtoff_min_ps = 1500; 478 else 479 todtoff_min_ps = 0; 480 /* todtoff_min */ 481 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 482 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 483 tmp++; 484 return tmp; 485 } 486 487 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 488 struct timing_related_config *timing_config) 489 { 490 uint32_t tmp, todtoff_max_ps; 491 492 if ((timing_config->dram_type == LPDDR4) 493 || (timing_config->dram_type == LPDDR3)) 494 todtoff_max_ps = 3500; 495 else 496 todtoff_max_ps = 0; 497 498 /* todtoff_max */ 499 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 500 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 501 tmp++; 502 return tmp; 503 } 504 505 static void gen_rk3399_ctl_params_f0(struct timing_related_config 506 *timing_config, 507 struct dram_timing_t *pdram_timing) 508 { 509 uint32_t i; 510 uint32_t tmp, tmp1; 511 512 for (i = 0; i < timing_config->ch_cnt; i++) { 513 if (timing_config->dram_type == DDR3) { 514 tmp = ((700000 + 10) * timing_config->freq + 515 999) / 1000; 516 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 517 pdram_timing->tmod + pdram_timing->tzqinit; 518 mmio_write_32(CTL_REG(i, 5), tmp); 519 520 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 521 pdram_timing->tdllk); 522 523 mmio_write_32(CTL_REG(i, 32), 524 (pdram_timing->tmod << 8) | 525 pdram_timing->tmrd); 526 527 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 528 (pdram_timing->txsr - 529 pdram_timing->trcd) << 16); 530 } else if (timing_config->dram_type == LPDDR4) { 531 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 532 pdram_timing->tinit3); 533 mmio_write_32(CTL_REG(i, 32), 534 (pdram_timing->tmrd << 8) | 535 pdram_timing->tmrd); 536 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 537 pdram_timing->txsr << 16); 538 } else { 539 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 540 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 541 mmio_write_32(CTL_REG(i, 32), 542 (pdram_timing->tmrd << 8) | 543 pdram_timing->tmrd); 544 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 545 pdram_timing->txsr << 16); 546 } 547 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 548 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 549 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 550 ((pdram_timing->cl * 2) << 16)); 551 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 552 (pdram_timing->cwl << 24)); 553 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 554 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16, 555 (pdram_timing->trc << 24) | 556 (pdram_timing->trrd << 16)); 557 mmio_write_32(CTL_REG(i, 27), 558 (pdram_timing->tfaw << 24) | 559 (pdram_timing->trppb << 16) | 560 (pdram_timing->twtr << 8) | 561 pdram_timing->tras_min); 562 563 mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24, 564 max(4, pdram_timing->trtp) << 24); 565 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 566 pdram_timing->tras_max); 567 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 568 max(1, pdram_timing->tckesr)); 569 mmio_clrsetbits_32(CTL_REG(i, 39), 570 (0x3f << 16) | (0xff << 8), 571 (pdram_timing->twr << 16) | 572 (pdram_timing->trcd << 8)); 573 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 574 pdram_timing->tmrz << 16); 575 tmp = pdram_timing->tdal ? pdram_timing->tdal : 576 (pdram_timing->twr + pdram_timing->trp); 577 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 578 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 579 mmio_write_32(CTL_REG(i, 48), 580 ((pdram_timing->trefi - 8) << 16) | 581 pdram_timing->trfc); 582 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 583 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16, 584 pdram_timing->txpdll << 16); 585 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 586 pdram_timing->tcscke << 24); 587 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 588 mmio_write_32(CTL_REG(i, 56), 589 (pdram_timing->tzqcke << 24) | 590 (pdram_timing->tmrwckel << 16) | 591 (pdram_timing->tckehcs << 8) | 592 pdram_timing->tckelcs); 593 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 594 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16, 595 (pdram_timing->tckehcmd << 24) | 596 (pdram_timing->tckelcmd << 16)); 597 mmio_write_32(CTL_REG(i, 63), 598 (pdram_timing->tckelpd << 24) | 599 (pdram_timing->tescke << 16) | 600 (pdram_timing->tsr << 8) | 601 pdram_timing->tckckel); 602 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 603 (pdram_timing->tcmdcke << 8) | 604 pdram_timing->tcsckeh); 605 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 606 (pdram_timing->tcksrx << 16) | 607 (pdram_timing->tcksre << 8)); 608 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 609 (timing_config->dllbp << 24)); 610 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 611 (pdram_timing->tvrcg_enable << 16)); 612 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 613 pdram_timing->tvrcg_disable); 614 mmio_write_32(CTL_REG(i, 124), 615 (pdram_timing->tvref_long << 16) | 616 (pdram_timing->tckfspx << 8) | 617 pdram_timing->tckfspe); 618 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 619 pdram_timing->mr[0]); 620 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 621 pdram_timing->mr[2]); 622 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 623 pdram_timing->mr[3]); 624 mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24, 625 pdram_timing->mr11 << 24); 626 mmio_write_32(CTL_REG(i, 147), 627 (pdram_timing->mr[1] << 16) | 628 pdram_timing->mr[0]); 629 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 630 pdram_timing->mr[2]); 631 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 632 pdram_timing->mr[3]); 633 mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24, 634 pdram_timing->mr11 << 24); 635 if (timing_config->dram_type == LPDDR4) { 636 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16, 637 pdram_timing->mr12 << 16); 638 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16, 639 pdram_timing->mr14 << 16); 640 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16, 641 pdram_timing->mr22 << 16); 642 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16, 643 pdram_timing->mr12 << 16); 644 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16, 645 pdram_timing->mr14 << 16); 646 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16, 647 pdram_timing->mr22 << 16); 648 } 649 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 650 pdram_timing->tzqinit << 8); 651 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 652 (pdram_timing->tzqinit / 2)); 653 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 654 pdram_timing->tzqcal); 655 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 656 pdram_timing->todton << 8); 657 658 if (timing_config->odt) { 659 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 660 if (timing_config->freq < 400) 661 tmp = 4 << 24; 662 else 663 tmp = 8 << 24; 664 } else { 665 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 666 tmp = 2 << 24; 667 } 668 669 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 670 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 671 (pdram_timing->tdqsck << 16) | 672 (pdram_timing->tdqsck_max << 8)); 673 tmp = 674 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 675 << 8) | get_rdlat_adj(timing_config->dram_type, 676 pdram_timing->cl); 677 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 678 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16, 679 (4 * pdram_timing->trefi) << 16); 680 681 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 682 (2 * pdram_timing->trefi) & 0xffff); 683 684 if ((timing_config->dram_type == LPDDR3) || 685 (timing_config->dram_type == LPDDR4)) { 686 tmp = get_pi_wrlat(pdram_timing, timing_config); 687 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 688 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 689 } else { 690 tmp = 0; 691 } 692 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 693 (tmp & 0x3f) << 16); 694 695 if ((timing_config->dram_type == LPDDR3) || 696 (timing_config->dram_type == LPDDR4)) { 697 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 698 tmp = pdram_timing->cl + 699 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 700 /* todtoff_max */ 701 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 702 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 703 } else { 704 tmp = pdram_timing->cl - pdram_timing->cwl; 705 } 706 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 707 (tmp & 0x3f) << 8); 708 709 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 710 (get_pi_tdfi_phy_rdlat(pdram_timing, 711 timing_config) & 712 0xff) << 16); 713 714 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 715 (2 * pdram_timing->trefi) & 0xffff); 716 717 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 718 (2 * pdram_timing->trefi) & 0xffff); 719 720 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 721 722 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 723 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 724 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 725 tmp1++; 726 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 727 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 728 729 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 730 tmp = tmp + 18; 731 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 732 733 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 734 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 735 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 736 if (tmp1 == 0) 737 tmp = 0; 738 else if (tmp1 < 5) 739 tmp = tmp1 - 1; 740 else 741 tmp = tmp1 - 5; 742 } else { 743 tmp = tmp1 - 2; 744 } 745 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 746 747 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 748 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 749 (pdram_timing->cl >= 5)) 750 tmp = pdram_timing->cl - 5; 751 else 752 tmp = pdram_timing->cl - 2; 753 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 754 } 755 } 756 757 static void gen_rk3399_ctl_params_f1(struct timing_related_config 758 *timing_config, 759 struct dram_timing_t *pdram_timing) 760 { 761 uint32_t i; 762 uint32_t tmp, tmp1; 763 764 for (i = 0; i < timing_config->ch_cnt; i++) { 765 if (timing_config->dram_type == DDR3) { 766 tmp = 767 ((700000 + 10) * timing_config->freq + 999) / 1000; 768 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 769 pdram_timing->tmod + pdram_timing->tzqinit; 770 mmio_write_32(CTL_REG(i, 9), tmp); 771 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16, 772 pdram_timing->tdllk << 16); 773 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 774 (pdram_timing->tmod << 24) | 775 (pdram_timing->tmrd << 16) | 776 (pdram_timing->trtp << 8)); 777 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 778 (pdram_timing->txsr - 779 pdram_timing->trcd) << 16); 780 } else if (timing_config->dram_type == LPDDR4) { 781 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 782 pdram_timing->tinit3); 783 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 784 (pdram_timing->tmrd << 24) | 785 (pdram_timing->tmrd << 16) | 786 (pdram_timing->trtp << 8)); 787 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 788 pdram_timing->txsr << 16); 789 } else { 790 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 791 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 792 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 793 (pdram_timing->tmrd << 24) | 794 (pdram_timing->tmrd << 16) | 795 (pdram_timing->trtp << 8)); 796 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 797 pdram_timing->txsr << 16); 798 } 799 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 800 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 801 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 802 ((pdram_timing->cl * 2) << 8)); 803 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 804 (pdram_timing->cwl << 16)); 805 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 806 pdram_timing->al << 24); 807 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 808 (pdram_timing->tras_min << 24) | 809 (pdram_timing->trc << 16) | 810 (pdram_timing->trrd << 8)); 811 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 812 (pdram_timing->tfaw << 16) | 813 (pdram_timing->trppb << 8) | 814 pdram_timing->twtr); 815 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 816 pdram_timing->tras_max); 817 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 818 max(1, pdram_timing->tckesr)); 819 mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24), 820 (pdram_timing->trcd << 24)); 821 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 822 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 823 pdram_timing->tmrz << 24); 824 tmp = pdram_timing->tdal ? pdram_timing->tdal : 825 (pdram_timing->twr + pdram_timing->trp); 826 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 827 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 828 pdram_timing->trp << 8); 829 mmio_write_32(CTL_REG(i, 49), 830 ((pdram_timing->trefi - 8) << 16) | 831 pdram_timing->trfc); 832 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16, 833 pdram_timing->txp << 16); 834 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 835 pdram_timing->txpdll); 836 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 837 pdram_timing->tmrri << 8); 838 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 839 (pdram_timing->tckehcs << 16) | 840 (pdram_timing->tckelcs << 8) | 841 pdram_timing->tcscke); 842 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 843 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 844 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16, 845 (pdram_timing->tckehcmd << 24) | 846 (pdram_timing->tckelcmd << 16)); 847 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 848 (pdram_timing->tescke << 16) | 849 (pdram_timing->tsr << 8) | 850 pdram_timing->tckckel); 851 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 852 (pdram_timing->tcmdcke << 8) | 853 pdram_timing->tcsckeh); 854 mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24), 855 (pdram_timing->tcksre << 24)); 856 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 857 pdram_timing->tcksrx); 858 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 859 (timing_config->dllbp << 25)); 860 mmio_write_32(CTL_REG(i, 125), 861 (pdram_timing->tvrcg_disable << 16) | 862 pdram_timing->tvrcg_enable); 863 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 864 (pdram_timing->tckfspe << 16) | 865 pdram_timing->tfc_long); 866 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 867 pdram_timing->tvref_long); 868 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16, 869 pdram_timing->mr[0] << 16); 870 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 871 pdram_timing->mr[1]); 872 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16, 873 pdram_timing->mr[3] << 16); 874 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 875 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16, 876 pdram_timing->mr[0] << 16); 877 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 878 pdram_timing->mr[1]); 879 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16, 880 pdram_timing->mr[3] << 16); 881 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 882 if (timing_config->dram_type == LPDDR4) { 883 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 884 pdram_timing->mr12); 885 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 886 pdram_timing->mr14); 887 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 888 pdram_timing->mr22); 889 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 890 pdram_timing->mr12); 891 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 892 pdram_timing->mr14); 893 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 894 pdram_timing->mr22); 895 } 896 mmio_write_32(CTL_REG(i, 182), 897 ((pdram_timing->tzqinit / 2) << 16) | 898 pdram_timing->tzqinit); 899 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 900 pdram_timing->tzqcs); 901 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 902 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 903 pdram_timing->tzqreset); 904 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 905 pdram_timing->todton << 16); 906 907 if (timing_config->odt) { 908 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 909 if (timing_config->freq < 400) 910 tmp = 4 << 24; 911 else 912 tmp = 8 << 24; 913 } else { 914 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 915 tmp = 2 << 24; 916 } 917 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 918 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 919 (pdram_timing->tdqsck_max << 24)); 920 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 921 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 922 (get_wrlat_adj(timing_config->dram_type, 923 pdram_timing->cwl) << 8) | 924 get_rdlat_adj(timing_config->dram_type, 925 pdram_timing->cl)); 926 927 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 928 (4 * pdram_timing->trefi) & 0xffff); 929 930 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16, 931 ((2 * pdram_timing->trefi) & 0xffff) << 16); 932 933 if ((timing_config->dram_type == LPDDR3) || 934 (timing_config->dram_type == LPDDR4)) { 935 tmp = get_pi_wrlat(pdram_timing, timing_config); 936 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 937 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 938 } else { 939 tmp = 0; 940 } 941 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 942 (tmp & 0x3f) << 24); 943 944 if ((timing_config->dram_type == LPDDR3) || 945 (timing_config->dram_type == LPDDR4)) { 946 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 947 tmp = pdram_timing->cl + 948 get_pi_todtoff_min(pdram_timing, timing_config); 949 tmp--; 950 /* todtoff_max */ 951 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 952 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 953 } else { 954 tmp = pdram_timing->cl - pdram_timing->cwl; 955 } 956 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 957 (tmp & 0x3f) << 16); 958 959 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24, 960 (get_pi_tdfi_phy_rdlat(pdram_timing, 961 timing_config) & 962 0xff) << 24); 963 964 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16, 965 ((2 * pdram_timing->trefi) & 0xffff) << 16); 966 967 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 968 (2 * pdram_timing->trefi) & 0xffff); 969 970 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 971 972 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 973 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 974 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 975 tmp1++; 976 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 977 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 978 979 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 980 tmp = tmp + 18; 981 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 982 983 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 984 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 985 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 986 if (tmp1 == 0) 987 tmp = 0; 988 else if (tmp1 < 5) 989 tmp = tmp1 - 1; 990 else 991 tmp = tmp1 - 5; 992 } else { 993 tmp = tmp1 - 2; 994 } 995 996 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); 997 998 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 999 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 1000 (pdram_timing->cl >= 5)) 1001 tmp = pdram_timing->cl - 5; 1002 else 1003 tmp = pdram_timing->cl - 2; 1004 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 1005 } 1006 } 1007 1008 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) 1009 { 1010 uint32_t i, tmp; 1011 1012 if (nmhz <= PHY_DLL_BYPASS_FREQ) 1013 tmp = 0; 1014 else 1015 tmp = 1; 1016 1017 for (i = 0; i < ch_cnt; i++) { 1018 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); 1019 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); 1020 mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); 1021 } 1022 } 1023 1024 static void gen_rk3399_disable_training(uint32_t ch_cnt) 1025 { 1026 uint32_t i; 1027 1028 for (i = 0; i < ch_cnt; i++) { 1029 mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); 1030 mmio_clrbits_32(CTL_REG(i, 71), 1); 1031 mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); 1032 } 1033 } 1034 1035 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1036 struct dram_timing_t *pdram_timing, 1037 uint32_t fn) 1038 { 1039 if (fn == 0) 1040 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1041 else 1042 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1043 } 1044 1045 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1046 struct dram_timing_t *pdram_timing) 1047 { 1048 uint32_t tmp, tmp1, tmp2; 1049 uint32_t i; 1050 1051 for (i = 0; i < timing_config->ch_cnt; i++) { 1052 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1053 tmp = 4 * pdram_timing->trefi; 1054 mmio_write_32(PI_REG(i, 2), tmp); 1055 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1056 tmp = 2 * pdram_timing->trefi; 1057 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1058 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1059 mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16); 1060 1061 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1062 if (timing_config->dram_type == LPDDR4) 1063 tmp = 2; 1064 else 1065 tmp = 0; 1066 tmp = (pdram_timing->bl / 2) + 4 + 1067 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1068 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1069 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1070 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1071 if (timing_config->dram_type == LPDDR3) { 1072 tmp = get_pi_wrlat(pdram_timing, timing_config); 1073 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1074 } 1075 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1076 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1077 PI_ADD_LATENCY << 8); 1078 1079 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1080 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1081 (pdram_timing->cl * 2) << 16); 1082 /* PI_46 PI_TREF_F0:RW:16:16 */ 1083 mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16, 1084 pdram_timing->trefi << 16); 1085 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1086 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1087 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1088 if (timing_config->dram_type == LPDDR3) { 1089 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1090 mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24, 1091 tmp << 24); 1092 } 1093 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1094 if ((timing_config->dram_type == LPDDR3) || 1095 (timing_config->dram_type == LPDDR4)) { 1096 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1097 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1098 if (tmp1 > tmp2) 1099 tmp = tmp1 - tmp2; 1100 else 1101 tmp = 0; 1102 } else if (timing_config->dram_type == DDR3) { 1103 tmp = 0; 1104 } 1105 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1106 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1107 if ((timing_config->dram_type == LPDDR3) || 1108 (timing_config->dram_type == LPDDR4)) { 1109 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1110 tmp1 = pdram_timing->cl; 1111 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1112 tmp1--; 1113 /* todtoff_max */ 1114 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1115 if (tmp1 > tmp2) 1116 tmp = tmp1 - tmp2; 1117 else 1118 tmp = 0; 1119 } else if (timing_config->dram_type == DDR3) { 1120 tmp = pdram_timing->cl - pdram_timing->cwl; 1121 } 1122 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1123 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1124 tmp = get_pi_rdlat_adj(pdram_timing); 1125 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1126 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1127 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1128 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1129 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1130 tmp1 = tmp; 1131 if (tmp1 == 0) 1132 tmp = 0; 1133 else if (tmp1 < 5) 1134 tmp = tmp1 - 1; 1135 else 1136 tmp = tmp1 - 5; 1137 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1138 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1139 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1140 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1141 tmp1++; 1142 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1143 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1144 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1145 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1146 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1147 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1148 pdram_timing->tmrz << 8); 1149 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1150 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1151 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1152 tmp1++; 1153 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1154 tmp = tmp1 + 5; 1155 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1156 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1157 tmp = 10000 / (1000000 / pdram_timing->mhz); 1158 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1159 tmp++; 1160 if (pdram_timing->mhz <= 100) 1161 tmp = tmp + 1; 1162 else 1163 tmp = tmp + 8; 1164 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1165 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1166 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1167 pdram_timing->mr[1] << 8); 1168 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1169 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1170 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1171 mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16, 1172 pdram_timing->mr[1] << 16); 1173 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1174 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1175 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1176 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1177 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1178 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16, 1179 pdram_timing->mr[2] << 16); 1180 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1181 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1182 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1183 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, 1184 pdram_timing->mr[2] << 16); 1185 /* PI_156 PI_TFC_F0:RW:0:10 */ 1186 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, pdram_timing->trfc); 1187 /* PI_158 PI_TWR_F0:RW:24:6 */ 1188 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1189 pdram_timing->twr << 24); 1190 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1191 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1192 pdram_timing->twtr << 16); 1193 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1194 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1195 pdram_timing->trcd << 8); 1196 /* PI_158 PI_TRP_F0:RW:0:8 */ 1197 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1198 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1199 mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24, 1200 pdram_timing->trtp << 24); 1201 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1202 mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24, 1203 pdram_timing->tras_min << 24); 1204 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1205 tmp = pdram_timing->tras_max * 99 / 100; 1206 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1207 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1208 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1209 pdram_timing->tmrd << 16); 1210 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1211 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1212 pdram_timing->tdqsck_max); 1213 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1214 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1215 (2 * pdram_timing->trefi) << 8); 1216 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1217 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1218 20 * pdram_timing->trefi); 1219 } 1220 } 1221 1222 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1223 struct dram_timing_t *pdram_timing) 1224 { 1225 uint32_t tmp, tmp1, tmp2; 1226 uint32_t i; 1227 1228 for (i = 0; i < timing_config->ch_cnt; i++) { 1229 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1230 tmp = 4 * pdram_timing->trefi; 1231 mmio_write_32(PI_REG(i, 4), tmp); 1232 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1233 tmp = 2 * pdram_timing->trefi; 1234 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1235 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1236 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1237 1238 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1239 if (timing_config->dram_type == LPDDR4) 1240 tmp = 2; 1241 else 1242 tmp = 0; 1243 tmp = (pdram_timing->bl / 2) + 4 + 1244 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1245 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1246 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1247 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1248 if (timing_config->dram_type == LPDDR3) { 1249 tmp = get_pi_wrlat(pdram_timing, timing_config); 1250 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1251 tmp << 24); 1252 } 1253 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1254 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1255 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1256 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1257 (pdram_timing->cl * 2) << 8); 1258 /* PI_47 PI_TREF_F1:RW:16:16 */ 1259 mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, 1260 pdram_timing->trefi << 16); 1261 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1262 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1263 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1264 if (timing_config->dram_type == LPDDR3) { 1265 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1266 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1267 } 1268 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1269 if ((timing_config->dram_type == LPDDR3) || 1270 (timing_config->dram_type == LPDDR4)) { 1271 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1272 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1273 if (tmp1 > tmp2) 1274 tmp = tmp1 - tmp2; 1275 else 1276 tmp = 0; 1277 } else if (timing_config->dram_type == DDR3) { 1278 tmp = 0; 1279 } 1280 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1281 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1282 if ((timing_config->dram_type == LPDDR3) || 1283 (timing_config->dram_type == LPDDR4)) { 1284 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1285 tmp1 = pdram_timing->cl + 1286 get_pi_todtoff_min(pdram_timing, timing_config); 1287 tmp1--; 1288 /* todtoff_max */ 1289 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1290 if (tmp1 > tmp2) 1291 tmp = tmp1 - tmp2; 1292 else 1293 tmp = 0; 1294 } else if (timing_config->dram_type == DDR3) 1295 tmp = pdram_timing->cl - pdram_timing->cwl; 1296 1297 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1298 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1299 tmp = get_pi_rdlat_adj(pdram_timing); 1300 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24); 1301 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1302 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1303 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24); 1304 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1305 tmp1 = tmp; 1306 if (tmp1 == 0) 1307 tmp = 0; 1308 else if (tmp1 < 5) 1309 tmp = tmp1 - 1; 1310 else 1311 tmp = tmp1 - 5; 1312 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24); 1313 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1314 /* tadr=20ns */ 1315 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1316 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1317 tmp1++; 1318 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1319 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1320 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1321 tmp = tmp + 18; 1322 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1323 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1324 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1325 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1326 /* tds_train=ceil(2/ns) */ 1327 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1328 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1329 tmp1++; 1330 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1331 tmp = tmp1 + 5; 1332 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1333 tmp << 16); 1334 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1335 tmp = 10000 / (1000000 / pdram_timing->mhz); 1336 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1337 tmp++; 1338 if (pdram_timing->mhz <= 100) 1339 tmp = tmp + 1; 1340 else 1341 tmp = tmp + 8; 1342 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1343 tmp << 24); 1344 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1345 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1346 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1347 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1348 pdram_timing->mr[1] << 8); 1349 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1350 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1351 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1352 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1353 pdram_timing->mr[1] << 8); 1354 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1355 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16, 1356 pdram_timing->mr[2] << 16); 1357 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1358 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1359 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1360 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16, 1361 pdram_timing->mr[2] << 16); 1362 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1363 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1364 /* PI_156 PI_TFC_F1:RW:16:10 */ 1365 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1366 pdram_timing->trfc << 16); 1367 /* PI_162 PI_TWR_F1:RW:8:6 */ 1368 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1369 pdram_timing->twr << 8); 1370 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1371 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1372 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1373 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24, 1374 pdram_timing->trcd << 24); 1375 /* PI_161 PI_TRP_F1:RW:16:8 */ 1376 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1377 pdram_timing->trp << 16); 1378 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1379 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1380 pdram_timing->trtp << 8); 1381 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1382 mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24, 1383 pdram_timing->tras_min << 24); 1384 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1385 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1386 pdram_timing->tras_max * 99 / 100); 1387 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1388 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1389 pdram_timing->tmrd << 16); 1390 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1391 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1392 pdram_timing->tdqsck_max); 1393 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1394 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1395 2 * pdram_timing->trefi); 1396 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1397 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1398 20 * pdram_timing->trefi); 1399 } 1400 } 1401 1402 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1403 struct dram_timing_t *pdram_timing, 1404 uint32_t fn) 1405 { 1406 if (fn == 0) 1407 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1408 else 1409 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1410 } 1411 1412 static void gen_rk3399_set_odt(uint32_t odt_en) 1413 { 1414 uint32_t drv_odt_val; 1415 uint32_t i; 1416 1417 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1418 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1419 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1420 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1421 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1422 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1423 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1424 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1425 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1426 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1427 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1428 } 1429 } 1430 1431 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, 1432 uint32_t index, uint32_t dram_type) 1433 { 1434 uint32_t sw_master_mode = 0; 1435 uint32_t rddqs_gate_delay, rddqs_latency, total_delay; 1436 uint32_t i; 1437 1438 if (dram_type == DDR3) 1439 total_delay = PI_PAD_DELAY_PS_VALUE; 1440 else if (dram_type == LPDDR3) 1441 total_delay = PI_PAD_DELAY_PS_VALUE + 2500; 1442 else 1443 total_delay = PI_PAD_DELAY_PS_VALUE + 1500; 1444 /* total_delay + 0.55tck */ 1445 total_delay += (55 * 10000)/mhz; 1446 rddqs_latency = total_delay * mhz / 1000000; 1447 total_delay -= rddqs_latency * 1000000 / mhz; 1448 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; 1449 if (mhz <= PHY_DLL_BYPASS_FREQ) { 1450 sw_master_mode = 0xc; 1451 mmio_setbits_32(PHY_REG(ch, 514), 1); 1452 mmio_setbits_32(PHY_REG(ch, 642), 1); 1453 mmio_setbits_32(PHY_REG(ch, 770), 1); 1454 1455 /* setting bypass mode slave delay */ 1456 for (i = 0; i < 4; i++) { 1457 /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ 1458 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, 1459 0x4a0 << 8); 1460 /* rd dqs/dq delay = (0x60 / 4) * 20ps */ 1461 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, 1462 0xa0); 1463 /* rd rddqs_gate delay */ 1464 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, 1465 rddqs_gate_delay); 1466 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, 1467 rddqs_latency); 1468 } 1469 for (i = 0; i < 3; i++) 1470 /* adr delay */ 1471 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), 1472 0x7ff << 16, 0x80 << 16); 1473 1474 if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { 1475 /* 1476 * old status is normal mode, 1477 * and saving the wrdqs slave delay 1478 */ 1479 for (i = 0; i < 4; i++) { 1480 /* save and clear wr dqs slave delay */ 1481 wrdqs_delay_val[ch][index][i] = 0x3ff & 1482 (mmio_read_32(PHY_REG(ch, 63 + i * 128)) 1483 >> 16); 1484 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1485 0x03ff << 16, 0 << 16); 1486 /* 1487 * in normal mode the cmd may delay 1cycle by 1488 * wrlvl and in bypass mode making dqs also 1489 * delay 1cycle. 1490 */ 1491 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), 1492 0x07 << 8, 0x1 << 8); 1493 } 1494 } 1495 } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { 1496 /* old status is bypass mode and restore wrlvl resume */ 1497 for (i = 0; i < 4; i++) { 1498 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1499 0x03ff << 16, 1500 (wrdqs_delay_val[ch][index][i] & 1501 0x3ff) << 16); 1502 /* resume phy_write_path_lat_add */ 1503 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); 1504 } 1505 } 1506 1507 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 1508 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); 1509 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); 1510 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); 1511 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); 1512 1513 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 1514 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); 1515 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); 1516 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); 1517 } 1518 1519 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1520 struct drv_odt_lp_config *drv_config, 1521 struct dram_timing_t *pdram_timing, 1522 uint32_t fn) 1523 { 1524 uint32_t tmp, i, div, j; 1525 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1526 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1527 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1528 uint32_t extra_adder, delta, hs_offset; 1529 1530 for (i = 0; i < timing_config->ch_cnt; i++) { 1531 1532 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1533 ie_enable = PI_IE_ENABLE_VALUE; 1534 tsel_enable = PI_TSEL_ENABLE_VALUE; 1535 1536 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1537 1538 /* PHY_LOW_FREQ_SEL */ 1539 /* DENALI_PHY_913 1bit offset_0 */ 1540 if (timing_config->freq > 400) 1541 mmio_clrbits_32(PHY_REG(i, 913), 1); 1542 else 1543 mmio_setbits_32(PHY_REG(i, 913), 1); 1544 1545 /* PHY_RPTR_UPDATE_x */ 1546 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1547 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1548 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1549 tmp++; 1550 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1551 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1552 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1553 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1554 1555 /* PHY_PLL_CTRL */ 1556 /* DENALI_PHY_911 13bits offset_0 */ 1557 /* PHY_LP4_BOOT_PLL_CTRL */ 1558 /* DENALI_PHY_919 13bits offset_0 */ 1559 tmp = (1 << 12) | (2 << 7) | (1 << 1); 1560 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1561 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1562 1563 /* PHY_PLL_CTRL_CA */ 1564 /* DENALI_PHY_911 13bits offset_16 */ 1565 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1566 /* DENALI_PHY_919 13bits offset_16 */ 1567 tmp = (2 << 7) | (1 << 5) | (1 << 1); 1568 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1569 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1570 1571 /* PHY_TCKSRE_WAIT */ 1572 /* DENALI_PHY_922 4bits offset_24 */ 1573 if (pdram_timing->mhz <= 400) 1574 tmp = 1; 1575 else if (pdram_timing->mhz <= 800) 1576 tmp = 3; 1577 else if (pdram_timing->mhz <= 1000) 1578 tmp = 4; 1579 else 1580 tmp = 5; 1581 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1582 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1583 div = pdram_timing->mhz / (2 * 20); 1584 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1585 if (div < j) 1586 break; 1587 } 1588 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1589 1590 if (timing_config->dram_type == DDR3) { 1591 mem_delay_ps = 0; 1592 trpre_min_ps = 1000; 1593 } else if (timing_config->dram_type == LPDDR4) { 1594 mem_delay_ps = 1500; 1595 trpre_min_ps = 900; 1596 } else if (timing_config->dram_type == LPDDR3) { 1597 mem_delay_ps = 2500; 1598 trpre_min_ps = 900; 1599 } else { 1600 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1601 return; 1602 } 1603 total_delay_ps = mem_delay_ps + pad_delay_ps; 1604 delay_frac_ps = 1000 * total_delay_ps / 1605 (1000000 / pdram_timing->mhz); 1606 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1607 gate_delay_frac_ps = gate_delay_ps % 1000; 1608 tmp = gate_delay_frac_ps * 0x200 / 1000; 1609 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1610 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1611 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1612 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1613 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1614 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1615 1616 tmp = gate_delay_ps / 1000; 1617 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1618 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1619 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1620 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1621 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1622 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1623 /* PHY_GTLVL_LAT_ADJ_START */ 1624 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1625 tmp = delay_frac_ps / 1000; 1626 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1627 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1628 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1629 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1630 1631 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1632 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1633 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1634 rddata_en_ie_dly++; 1635 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1636 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1637 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1638 tsel_adder++; 1639 if (rddata_en_ie_dly > tsel_adder) 1640 extra_adder = rddata_en_ie_dly - tsel_adder; 1641 else 1642 extra_adder = 0; 1643 delta = cas_lat - rddata_en_ie_dly; 1644 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1645 hs_offset = 2; 1646 else 1647 hs_offset = 1; 1648 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1649 tmp = 0; 1650 else if ((delta == 2) || (delta == 1)) 1651 tmp = rddata_en_ie_dly - 0 - extra_adder; 1652 else 1653 tmp = extra_adder; 1654 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1655 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1656 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1657 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1658 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1659 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1660 /* PHY_RDDATA_EN_TSEL_DLY */ 1661 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1662 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1663 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1664 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1665 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1666 1667 if (tsel_adder > rddata_en_ie_dly) 1668 extra_adder = tsel_adder - rddata_en_ie_dly; 1669 else 1670 extra_adder = 0; 1671 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1672 tmp = tsel_adder; 1673 else 1674 tmp = rddata_en_ie_dly - 0 + extra_adder; 1675 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1676 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1677 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1678 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1679 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1680 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1681 /* PHY_RDDATA_EN_DLY */ 1682 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1683 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1684 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1685 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1686 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1687 1688 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1689 /* 1690 * Note:Per-CS Training is not compatible at speeds 1691 * under 533 MHz. If the PHY is running at a speed 1692 * less than 533MHz, all phy_per_cs_training_en_X 1693 * parameters must be cleared to 0. 1694 */ 1695 1696 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1697 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1698 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1699 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1700 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1701 } else { 1702 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1703 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1704 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1705 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1706 } 1707 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, 1708 timing_config->dram_type); 1709 } 1710 } 1711 1712 static int to_get_clk_index(unsigned int mhz) 1713 { 1714 int pll_cnt, i; 1715 1716 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1717 1718 /* Assumming rate_table is in descending order */ 1719 for (i = 0; i < pll_cnt; i++) { 1720 if (mhz >= dpll_rates_table[i].mhz) 1721 break; 1722 } 1723 1724 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1725 if (i == pll_cnt) 1726 i = pll_cnt - 1; 1727 1728 return i; 1729 } 1730 1731 uint32_t ddr_get_rate(void) 1732 { 1733 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1734 1735 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1736 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1737 postdiv1 = 1738 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1739 postdiv2 = 1740 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1741 1742 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1743 } 1744 1745 /* 1746 * return: bit12: channel 1, external self-refresh 1747 * bit11: channel 1, stdby_mode 1748 * bit10: channel 1, self-refresh with controller and memory clock gate 1749 * bit9: channel 1, self-refresh 1750 * bit8: channel 1, power-down 1751 * 1752 * bit4: channel 1, external self-refresh 1753 * bit3: channel 0, stdby_mode 1754 * bit2: channel 0, self-refresh with controller and memory clock gate 1755 * bit1: channel 0, self-refresh 1756 * bit0: channel 0, power-down 1757 */ 1758 uint32_t exit_low_power(void) 1759 { 1760 uint32_t low_power = 0; 1761 uint32_t channel_mask; 1762 uint32_t tmp, i; 1763 1764 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1765 0x3; 1766 for (i = 0; i < 2; i++) { 1767 if (!(channel_mask & (1 << i))) 1768 continue; 1769 1770 /* exit stdby mode */ 1771 mmio_write_32(CIC_BASE + CIC_CTRL1, 1772 (1 << (i + 16)) | (0 << i)); 1773 /* exit external self-refresh */ 1774 tmp = i ? 12 : 8; 1775 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1776 0x1) << (4 + 8 * i); 1777 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1778 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1779 ; 1780 /* exit auto low-power */ 1781 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1782 /* lp_cmd to exit */ 1783 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1784 0x40) { 1785 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1786 ; 1787 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24, 1788 0x69 << 24); 1789 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1790 0x40) 1791 ; 1792 } 1793 } 1794 return low_power; 1795 } 1796 1797 void resume_low_power(uint32_t low_power) 1798 { 1799 uint32_t channel_mask; 1800 uint32_t tmp, i, val; 1801 1802 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1803 0x3; 1804 for (i = 0; i < 2; i++) { 1805 if (!(channel_mask & (1 << i))) 1806 continue; 1807 1808 /* resume external self-refresh */ 1809 tmp = i ? 12 : 8; 1810 val = (low_power >> (4 + 8 * i)) & 0x1; 1811 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1812 /* resume auto low-power */ 1813 val = (low_power >> (8 * i)) & 0x7; 1814 mmio_setbits_32(CTL_REG(i, 101), val); 1815 /* resume stdby mode */ 1816 val = (low_power >> (3 + 8 * i)) & 0x1; 1817 mmio_write_32(CIC_BASE + CIC_CTRL1, 1818 (1 << (i + 16)) | (val << i)); 1819 } 1820 } 1821 1822 static void dram_low_power_config(void) 1823 { 1824 uint32_t tmp, i; 1825 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1826 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1827 1828 if (dram_type == DDR3) 1829 tmp = (2 << 16) | (0x7 << 8); 1830 else 1831 tmp = (3 << 16) | (0x7 << 8); 1832 1833 for (i = 0; i < ch_cnt; i++) 1834 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1835 1836 /* standby idle */ 1837 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1838 1839 if (ch_cnt == 2) { 1840 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1841 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1842 (0x1<<7)) << 16) | 1843 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1844 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1845 } 1846 1847 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1848 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1849 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1850 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1851 } 1852 1853 void dram_dfs_init(void) 1854 { 1855 uint32_t trefi0, trefi1, boot_freq; 1856 1857 /* get sdram config for os reg */ 1858 get_dram_drv_odt_val(sdram_config.dramtype, 1859 &rk3399_dram_status.drv_odt_lp_cfg); 1860 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1861 &sdram_config, 1862 &rk3399_dram_status.drv_odt_lp_cfg); 1863 1864 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1865 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1866 1867 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1868 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1869 rk3399_dram_status.current_index = 1870 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1871 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1872 rk3399_dram_status.index_freq[0] /= 2; 1873 rk3399_dram_status.index_freq[1] /= 2; 1874 } 1875 boot_freq = 1876 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 1877 boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz; 1878 rk3399_dram_status.boot_freq = boot_freq; 1879 rk3399_dram_status.index_freq[rk3399_dram_status.current_index] = 1880 boot_freq; 1881 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) & 1882 0x1] = 0; 1883 rk3399_dram_status.low_power_stat = 0; 1884 /* 1885 * following register decide if NOC stall the access request 1886 * or return error when NOC being idled. when doing ddr frequency 1887 * scaling in M0 or DCF, we need to make sure noc stall the access 1888 * request, if return error cpu may data abort when ddr frequency 1889 * changing. it don't need to set this register every times, 1890 * so we init this register in function dram_dfs_init(). 1891 */ 1892 mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); 1893 mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); 1894 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); 1895 mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); 1896 mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); 1897 1898 /* Disable multicast */ 1899 mmio_clrbits_32(PHY_REG(0, 896), 1); 1900 mmio_clrbits_32(PHY_REG(1, 896), 1); 1901 1902 dram_low_power_config(); 1903 } 1904 1905 /* 1906 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1907 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1908 * arg2: bit0: if odt en 1909 */ 1910 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1911 { 1912 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1913 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1914 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1915 1916 dram_type = rk3399_dram_status.timing_config.dram_type; 1917 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1918 1919 lp_cfg->sr_idle = arg0 & 0xff; 1920 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1921 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1922 lp_cfg->pd_idle = arg1 & 0xfff; 1923 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1924 1925 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1926 1927 exit_low_power(); 1928 1929 *low_power = 0; 1930 1931 /* pd_idle en */ 1932 if (lp_cfg->pd_idle) 1933 *low_power |= ((1 << 0) | (1 << 8)); 1934 /* sr_idle en srpd_lite_idle */ 1935 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1936 *low_power |= ((1 << 1) | (1 << 9)); 1937 /* sr_mc_gate_idle */ 1938 if (lp_cfg->sr_mc_gate_idle) 1939 *low_power |= ((1 << 2) | (1 << 10)); 1940 /* standbyidle */ 1941 if (lp_cfg->standby_idle) { 1942 if (rk3399_dram_status.timing_config.ch_cnt == 2) 1943 *low_power |= ((1 << 3) | (1 << 11)); 1944 else 1945 *low_power |= (1 << 3); 1946 } 1947 1948 pd_tmp = arg1; 1949 if (dram_type != LPDDR4) 1950 pd_tmp = arg1 & 0xfff; 1951 sr_tmp = arg0 & 0xffff; 1952 for (i = 0; i < ch_count; i++) { 1953 mmio_write_32(CTL_REG(i, 102), pd_tmp); 1954 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 1955 } 1956 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 1957 1958 return 0; 1959 } 1960 1961 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) 1962 { 1963 /* set PARAM to M0_FUNC_DRAM */ 1964 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_DRAM); 1965 1966 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(pll_div.fbdiv)); 1967 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON1, 1968 POSTDIV2(pll_div.postdiv2) | POSTDIV1(pll_div.postdiv1) | 1969 REFDIV(pll_div.refdiv)); 1970 1971 mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz); 1972 1973 mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4); 1974 dmbst(); 1975 } 1976 1977 static uint32_t prepare_ddr_timing(uint32_t mhz) 1978 { 1979 uint32_t index; 1980 struct dram_timing_t dram_timing; 1981 1982 rk3399_dram_status.timing_config.freq = mhz; 1983 1984 if (mhz < 300) 1985 rk3399_dram_status.timing_config.dllbp = 1; 1986 else 1987 rk3399_dram_status.timing_config.dllbp = 0; 1988 1989 if (rk3399_dram_status.timing_config.odt == 1) 1990 gen_rk3399_set_odt(1); 1991 1992 index = (rk3399_dram_status.current_index + 1) & 0x1; 1993 1994 /* 1995 * checking if having available gate traiing timing for 1996 * target freq. 1997 */ 1998 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 1999 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2000 &dram_timing, index); 2001 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2002 &dram_timing, index); 2003 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2004 &rk3399_dram_status.drv_odt_lp_cfg, 2005 &dram_timing, index); 2006 rk3399_dram_status.index_freq[index] = mhz; 2007 2008 return index; 2009 } 2010 2011 void print_dram_status_info(void) 2012 { 2013 uint32_t *p; 2014 uint32_t i; 2015 2016 p = (uint32_t *) &rk3399_dram_status.timing_config; 2017 INFO("rk3399_dram_status.timing_config:\n"); 2018 for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) 2019 tf_printf("%u\n", p[i]); 2020 p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; 2021 INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); 2022 for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) 2023 tf_printf("%u\n", p[i]); 2024 } 2025 2026 uint32_t ddr_set_rate(uint32_t hz) 2027 { 2028 uint32_t low_power, index, ddr_index; 2029 uint32_t mhz = hz / (1000 * 1000); 2030 2031 if (mhz == 2032 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2033 return mhz; 2034 2035 index = to_get_clk_index(mhz); 2036 mhz = dpll_rates_table[index].mhz; 2037 2038 ddr_index = prepare_ddr_timing(mhz); 2039 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, 2040 mhz); 2041 if (ddr_index > 1) 2042 goto out; 2043 2044 /* 2045 * Make sure the clock is enabled. The M0 clocks should be on all of the 2046 * time during S0. 2047 */ 2048 m0_configure_ddr(dpll_rates_table[index], ddr_index); 2049 m0_start(); 2050 m0_wait_done(); 2051 m0_stop(); 2052 2053 if (rk3399_dram_status.timing_config.odt == 0) 2054 gen_rk3399_set_odt(0); 2055 2056 rk3399_dram_status.current_index = ddr_index; 2057 low_power = rk3399_dram_status.low_power_stat; 2058 resume_low_power(low_power); 2059 out: 2060 gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt); 2061 return mhz; 2062 } 2063 2064 uint32_t ddr_round_rate(uint32_t hz) 2065 { 2066 int index; 2067 uint32_t mhz = hz / (1000 * 1000); 2068 2069 index = to_get_clk_index(mhz); 2070 2071 return dpll_rates_table[index].mhz * 1000 * 1000; 2072 } 2073 2074 void ddr_prepare_for_sys_suspend(void) 2075 { 2076 uint32_t mhz = 2077 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 2078 2079 /* 2080 * If we're not currently at the boot (assumed highest) frequency, we 2081 * need to change frequencies to configure out current index. 2082 */ 2083 rk3399_suspend_status.freq = mhz; 2084 exit_low_power(); 2085 rk3399_suspend_status.low_power_stat = 2086 rk3399_dram_status.low_power_stat; 2087 rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt; 2088 rk3399_dram_status.low_power_stat = 0; 2089 rk3399_dram_status.timing_config.odt = 1; 2090 if (mhz != rk3399_dram_status.boot_freq) 2091 ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000); 2092 2093 /* 2094 * This will configure the other index to be the same frequency as the 2095 * current one. We retrain both indices on resume, so both have to be 2096 * setup for the same frequency. 2097 */ 2098 prepare_ddr_timing(rk3399_dram_status.boot_freq); 2099 } 2100 2101 void ddr_prepare_for_sys_resume(void) 2102 { 2103 /* Disable multicast */ 2104 mmio_clrbits_32(PHY_REG(0, 896), 1); 2105 mmio_clrbits_32(PHY_REG(1, 896), 1); 2106 2107 /* The suspend code changes the current index, so reset it now. */ 2108 rk3399_dram_status.current_index = 2109 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 2110 rk3399_dram_status.low_power_stat = 2111 rk3399_suspend_status.low_power_stat; 2112 rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt; 2113 2114 /* 2115 * Set the saved frequency from suspend if it's different than the 2116 * current frequency. 2117 */ 2118 if (rk3399_suspend_status.freq != 2119 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) { 2120 ddr_set_rate(rk3399_suspend_status.freq * 1000 * 1000); 2121 return; 2122 } 2123 2124 gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt); 2125 resume_low_power(rk3399_dram_status.low_power_stat); 2126 } 2127