1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <common_def.h> 34#include <memctrl_v2.h> 35#include <tegra_def.h> 36 37#define TEGRA186_SMMU_CTX_SIZE 0x420 38 39 .align 4 40 .globl tegra186_cpu_reset_handler 41 42/* CPU reset handler routine */ 43func tegra186_cpu_reset_handler 44 /* 45 * The Memory Controller loses state during System Suspend. We 46 * use this information to decide if the reset handler is running 47 * after a System Suspend. Resume from system suspend requires 48 * restoring the entire state from TZDRAM to TZRAM. 49 */ 50 mov x1, #TEGRA_MC_BASE 51 ldr w0, [x1, #MC_SECURITY_CFG3_0] 52 lsl x0, x0, #32 53 ldr w0, [x1, #MC_SECURITY_CFG0_0] 54 adr x1, tegra186_cpu_reset_handler 55 cmp x0, x1 56 beq boot_cpu 57 58 /* resume from system suspend */ 59 mov x0, #BL31_BASE 60 adr x1, __tegra186_cpu_reset_handler_end 61 adr x2, __tegra186_cpu_reset_handler_data 62 ldr x2, [x2, #8] 63 64 /* memcpy16 */ 65m_loop16: 66 cmp x2, #16 67 b.lt m_loop1 68 ldp x3, x4, [x1], #16 69 stp x3, x4, [x0], #16 70 sub x2, x2, #16 71 b m_loop16 72 /* copy byte per byte */ 73m_loop1: 74 cbz x2, boot_cpu 75 ldrb w3, [x1], #1 76 strb w3, [x0], #1 77 subs x2, x2, #1 78 b.ne m_loop1 79 80boot_cpu: 81 adr x0, __tegra186_cpu_reset_handler_data 82 ldr x0, [x0] 83 br x0 84endfunc tegra186_cpu_reset_handler 85 86 /* 87 * Tegra186 reset data (offset 0x0 - 0x430) 88 * 89 * 0x000: secure world's entrypoint 90 * 0x008: BL31 size (RO + RW) 91 * 0x00C: SMMU context start 92 * 0x42C: SMMU context end 93 */ 94 95 .align 4 96 .type __tegra186_cpu_reset_handler_data, %object 97 .globl __tegra186_cpu_reset_handler_data 98__tegra186_cpu_reset_handler_data: 99 .quad tegra_secure_entrypoint 100 .quad __BL31_END__ - BL31_BASE 101 .rept TEGRA186_SMMU_CTX_SIZE 102 .quad 0 103 .endr 104 .size __tegra186_cpu_reset_handler_data, \ 105 . - __tegra186_cpu_reset_handler_data 106 107 .align 4 108 .globl __tegra186_cpu_reset_handler_end 109__tegra186_cpu_reset_handler_end: 110