1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <assert.h> 34 #include <bl_common.h> 35 #include <context.h> 36 #include <context_mgmt.h> 37 #include <debug.h> 38 #include <denver.h> 39 #include <mce.h> 40 #include <platform.h> 41 #include <psci.h> 42 #include <smmu.h> 43 #include <string.h> 44 #include <t18x_ari.h> 45 #include <tegra_private.h> 46 47 extern void prepare_cpu_pwr_dwn(void); 48 extern void tegra186_cpu_reset_handler(void); 49 extern uint32_t __tegra186_cpu_reset_handler_data, 50 __tegra186_cpu_reset_handler_end; 51 52 /* TZDRAM offset for saving SMMU context */ 53 #define TEGRA186_SMMU_CTX_OFFSET 16 54 55 /* state id mask */ 56 #define TEGRA186_STATE_ID_MASK 0xF 57 /* constants to get power state's wake time */ 58 #define TEGRA186_WAKE_TIME_MASK 0xFFFFFF 59 #define TEGRA186_WAKE_TIME_SHIFT 4 60 /* default core wake mask for CPU_SUSPEND */ 61 #define TEGRA186_CORE_WAKE_MASK 0x180c 62 /* context size to save during system suspend */ 63 #define TEGRA186_SE_CONTEXT_SIZE 3 64 65 static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; 66 static unsigned int wake_time[PLATFORM_CORE_COUNT]; 67 68 /* System power down state */ 69 uint32_t tegra186_system_powerdn_state = TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF; 70 71 int32_t tegra_soc_validate_power_state(unsigned int power_state, 72 psci_power_state_t *req_state) 73 { 74 int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; 75 int cpu = plat_my_core_pos(); 76 77 /* save the core wake time (us) */ 78 wake_time[cpu] = (power_state >> TEGRA186_WAKE_TIME_SHIFT) & 79 TEGRA186_WAKE_TIME_MASK; 80 81 /* Sanity check the requested state id */ 82 switch (state_id) { 83 case PSTATE_ID_CORE_IDLE: 84 case PSTATE_ID_CORE_POWERDN: 85 86 /* Core powerdown request */ 87 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; 88 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 89 90 break; 91 92 default: 93 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 94 return PSCI_E_INVALID_PARAMS; 95 } 96 97 return PSCI_E_SUCCESS; 98 } 99 100 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 101 { 102 const plat_local_state_t *pwr_domain_state; 103 unsigned int stateid_afflvl0, stateid_afflvl2; 104 int cpu = plat_my_core_pos(); 105 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 106 mce_cstate_info_t cstate_info = { 0 }; 107 uint64_t smmu_ctx_base; 108 uint32_t val; 109 110 /* get the state ID */ 111 pwr_domain_state = target_state->pwr_domain_state; 112 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & 113 TEGRA186_STATE_ID_MASK; 114 stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 115 TEGRA186_STATE_ID_MASK; 116 117 if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || 118 (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { 119 120 /* Enter CPU idle/powerdown */ 121 val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? 122 TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7; 123 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, val, 124 wake_time[cpu], 0); 125 126 } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 127 128 /* save SE registers */ 129 se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + 130 SE_MUTEX_WATCHDOG_NS_LIMIT); 131 se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE + 132 RNG_MUTEX_WATCHDOG_NS_LIMIT); 133 se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + 134 PKA_MUTEX_WATCHDOG_NS_LIMIT); 135 136 /* save 'Secure Boot' Processor Feature Config Register */ 137 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); 138 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); 139 140 /* save SMMU context to TZDRAM */ 141 smmu_ctx_base = params_from_bl2->tzdram_base + 142 ((uintptr_t)&__tegra186_cpu_reset_handler_data - 143 (uintptr_t)tegra186_cpu_reset_handler) + 144 TEGRA186_SMMU_CTX_OFFSET; 145 tegra_smmu_save_context((uintptr_t)smmu_ctx_base); 146 147 /* Prepare for system suspend */ 148 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 149 cstate_info.system = TEGRA_ARI_SYSTEM_SC7; 150 cstate_info.system_state_force = 1; 151 cstate_info.update_wake_mask = 1; 152 mce_update_cstate_info(&cstate_info); 153 154 /* Loop until system suspend is allowed */ 155 do { 156 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 157 TEGRA_ARI_CORE_C7, 158 MCE_CORE_SLEEP_TIME_INFINITE, 159 0); 160 } while (val == 0); 161 162 /* Instruct the MCE to enter system suspend state */ 163 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 164 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 165 } 166 167 return PSCI_E_SUCCESS; 168 } 169 170 /******************************************************************************* 171 * Platform handler to calculate the proper target power level at the 172 * specified affinity level 173 ******************************************************************************/ 174 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 175 const plat_local_state_t *states, 176 unsigned int ncpu) 177 { 178 plat_local_state_t target = *states; 179 int cpu = plat_my_core_pos(), ret, cluster_powerdn = 1; 180 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 181 mce_cstate_info_t cstate_info = { 0 }; 182 183 /* get the current core's power state */ 184 target = *(states + core_pos); 185 186 /* CPU suspend */ 187 if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { 188 189 /* Program default wake mask */ 190 cstate_info.wake_mask = TEGRA186_CORE_WAKE_MASK; 191 cstate_info.update_wake_mask = 1; 192 mce_update_cstate_info(&cstate_info); 193 194 /* Check if CCx state is allowed. */ 195 ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, 196 TEGRA_ARI_CORE_C7, wake_time[cpu], 0); 197 if (ret) 198 return PSTATE_ID_CORE_POWERDN; 199 } 200 201 /* CPU off */ 202 if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { 203 204 /* find out the number of ON cpus in the cluster */ 205 do { 206 target = *states++; 207 if (target != PLAT_MAX_OFF_STATE) 208 cluster_powerdn = 0; 209 } while (--ncpu); 210 211 /* Enable cluster powerdn from last CPU in the cluster */ 212 if (cluster_powerdn) { 213 214 /* Enable CC7 state and turn off wake mask */ 215 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 216 cstate_info.update_wake_mask = 1; 217 mce_update_cstate_info(&cstate_info); 218 219 /* Check if CCx state is allowed. */ 220 ret = mce_command_handler(MCE_CMD_IS_CCX_ALLOWED, 221 TEGRA_ARI_CORE_C7, 222 MCE_CORE_SLEEP_TIME_INFINITE, 223 0); 224 if (ret) 225 return PSTATE_ID_CORE_POWERDN; 226 227 } else { 228 229 /* Turn off wake_mask */ 230 cstate_info.update_wake_mask = 1; 231 mce_update_cstate_info(&cstate_info); 232 } 233 } 234 235 /* System Suspend */ 236 if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) 237 return PSTATE_ID_SOC_POWERDN; 238 239 /* default state */ 240 return PSCI_LOCAL_STATE_RUN; 241 } 242 243 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 244 { 245 const plat_local_state_t *pwr_domain_state = 246 target_state->pwr_domain_state; 247 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 248 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & 249 TEGRA186_STATE_ID_MASK; 250 uint32_t val; 251 252 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 253 /* 254 * The TZRAM loses power when we enter system suspend. To 255 * allow graceful exit from system suspend, we need to copy 256 * BL3-1 over to TZDRAM. 257 */ 258 val = params_from_bl2->tzdram_base + 259 ((uintptr_t)&__tegra186_cpu_reset_handler_end - 260 (uintptr_t)tegra186_cpu_reset_handler); 261 memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, 262 (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); 263 } 264 265 return PSCI_E_SUCCESS; 266 } 267 268 int tegra_soc_pwr_domain_on(u_register_t mpidr) 269 { 270 int target_cpu = mpidr & MPIDR_CPU_MASK; 271 int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> 272 MPIDR_AFFINITY_BITS; 273 274 if (target_cluster > MPIDR_AFFLVL1) { 275 ERROR("%s: unsupported CPU (0x%lx)\n", __func__, mpidr); 276 return PSCI_E_NOT_PRESENT; 277 } 278 279 /* construct the target CPU # */ 280 target_cpu |= (target_cluster << 2); 281 282 mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); 283 284 return PSCI_E_SUCCESS; 285 } 286 287 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 288 { 289 int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 290 int stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; 291 mce_cstate_info_t cstate_info = { 0 }; 292 293 /* 294 * Reset power state info for CPUs when onlining, we set 295 * deepest power when offlining a core but that may not be 296 * requested by non-secure sw which controls idle states. It 297 * will re-init this info from non-secure software when the 298 * core come online. 299 */ 300 if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) { 301 302 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1; 303 cstate_info.update_wake_mask = 1; 304 mce_update_cstate_info(&cstate_info); 305 } 306 307 /* 308 * Check if we are exiting from deep sleep and restore SE 309 * context if we are. 310 */ 311 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 312 313 mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, 314 se_regs[0]); 315 mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT, 316 se_regs[1]); 317 mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, 318 se_regs[2]); 319 320 /* Init SMMU */ 321 tegra_smmu_init(); 322 323 /* 324 * Reset power state info for the last core doing SC7 325 * entry and exit, we set deepest power state as CC7 326 * and SC7 for SC7 entry which may not be requested by 327 * non-secure SW which controls idle states. 328 */ 329 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 330 cstate_info.system = TEGRA_ARI_SYSTEM_SC1; 331 cstate_info.update_wake_mask = 1; 332 mce_update_cstate_info(&cstate_info); 333 } 334 335 return PSCI_E_SUCCESS; 336 } 337 338 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 339 { 340 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 341 342 /* Disable Denver's DCO operations */ 343 if (impl == DENVER_IMPL) 344 denver_disable_dco(); 345 346 /* Turn off CPU */ 347 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7, 348 MCE_CORE_SLEEP_TIME_INFINITE, 0); 349 350 return PSCI_E_SUCCESS; 351 } 352 353 __dead2 void tegra_soc_prepare_system_off(void) 354 { 355 mce_cstate_info_t cstate_info = { 0 }; 356 uint32_t val; 357 358 if (tegra186_system_powerdn_state == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) { 359 360 /* power off the entire system */ 361 mce_enter_ccplex_state(tegra186_system_powerdn_state); 362 363 } else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) { 364 365 /* Prepare for quasi power down */ 366 cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7; 367 cstate_info.system = TEGRA_ARI_SYSTEM_SC8; 368 cstate_info.system_state_force = 1; 369 cstate_info.update_wake_mask = 1; 370 mce_update_cstate_info(&cstate_info); 371 372 /* loop until other CPUs power down */ 373 do { 374 val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED, 375 TEGRA_ARI_CORE_C7, 376 MCE_CORE_SLEEP_TIME_INFINITE, 377 0); 378 } while (val == 0); 379 380 /* Enter quasi power down state */ 381 (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, 382 TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); 383 384 /* disable GICC */ 385 tegra_gic_cpuif_deactivate(); 386 387 /* power down core */ 388 prepare_cpu_pwr_dwn(); 389 390 /* flush L1/L2 data caches */ 391 dcsw_op_all(DCCISW); 392 393 } else { 394 ERROR("%s: unsupported power down state (%d)\n", __func__, 395 tegra186_system_powerdn_state); 396 } 397 398 wfi(); 399 400 /* wait for the system to power down */ 401 for (;;) { 402 ; 403 } 404 } 405 406 int tegra_soc_prepare_system_reset(void) 407 { 408 mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT); 409 410 return PSCI_E_SUCCESS; 411 } 412