refactor(cpus): register DSU errata with the errata framework's wrappers

The existing DSU errata workarounds hijack the errata framework's inner
workings to register with it. However, that is undesi

refactor(cpus): register DSU errata with the errata framework's wrappers

The existing DSU errata workarounds hijack the errata framework's inner
workings to register with it. However, that is undesirable as any change
to the framework may end up missing these workarounds. So convert the
checks and workarounds to macros and have them included with the
standard wrappers.

The only problem with this is the is_scu_present_in_dsu weak function.
Fortunately, it is only needed for 2 of the errata and only on 3 cores.
So drop it, assuming the default behaviour and have the callers handle
the exception.

Change-Id: Iefa36325804ea093e938f867b9a6f49a6984b8ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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perf(build): be clever about uppercasing

Most of the macros in build_macros.mk get lazily evaluated. That's
mostly fine, except for the fact that the `uppercase` macro needs to
spawn a subshell to g

perf(build): be clever about uppercasing

Most of the macros in build_macros.mk get lazily evaluated. That's
mostly fine, except for the fact that the `uppercase` macro needs to
spawn a subshell to get its output. And the target for every file
requires calling `uppercase` many, MANY, times, thrashing performance on
even the most trivial of make commands.

We can be a little clever and only call `uppercase` a handful of times
and then pass around the already uppercased strings.

The same is true about the verbosity augmentation variables. Simply
changing them to simply expanded variables allows for them to be
pre-processed and then used over and over again.

`make realclean` is a pretty good benchmark for this as it doesn't do
much else but must process all the rules, like every other make command.
On a clean checkout of TF-A on an Intel Xeon Gold 5218 (i.e. slow
single-core) workstation, that command used to take about 7 seconds.
With this patch it takes about 0.5.

Change-Id: I632236a12a40f169e834974ecbc73ff80aac3462
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA

Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte*
store instruction. A related instruction is ST64BV0, which will replace
the lowest

feat(cpufeat): add ENABLE_FEAT_LS64_ACCDATA

Armv8.6 introduced the FEAT_LS64 extension, which provides a 64 *byte*
store instruction. A related instruction is ST64BV0, which will replace
the lowest 32 bits of the data with a value taken from the ACCDATA_EL1
system register (so that EL0 cannot alter them).
Using that ST64BV0 instruction and accessing the ACCDATA_EL1 system
register is guarded by two SCR_EL3 bits, which we should set to avoid a
trap into EL3, when lower ELs use one of those.

Add the required bits and pieces to make this feature usable:
- Add the ENABLE_FEAT_LS64_ACCDATA build option (defaulting to 0).
- Add the CPUID and SCR_EL3 bit definitions associated with FEAT_LS64.
- Add a feature check to check for the existing four variants of the
LS64 feature and detect future extensions.
- Add code to save and restore the ACCDATA_EL1 register on
secure/non-secure context switches.
- Enable the feature with runtime detection for FVP and Arm FPGA.

Please note that the *basic* FEAT_LS64 feature does not feature any trap
bits, it's only the addition of the ACCDATA_EL1 system register that
adds these traps and the SCR_EL3 bits.

Change-Id: Ie3e2ca2d9c4fbbd45c0cc6089accbb825579138a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fpga): enable new CPU features

Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.

Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any us

feat(fpga): enable new CPU features

Newer cores implemented in the FPGAs used by Arm Ltd. support more
ARMv9 features.

Enable TCR2, MTE, MTE2, SME and SME2 as "enable if available" (:=2), so
any users of those features in lower ELs will not trigger a trap into
BL31.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Id99ecb7c5d6a25b77f7cc5fcad63f60027a4fd5a

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fix(fpga): avoid stripping kernel trampoline

The Arm FPGA platform builds a final AXF file, which is an ELF file
containing some required trampolines and binaries, like the DTB. This is
more a "cont

fix(fpga): avoid stripping kernel trampoline

The Arm FPGA platform builds a final AXF file, which is an ELF file
containing some required trampolines and binaries, like the DTB. This is
more a "container with load addresses" than an object or executable
file, but it's still built with the linker tool.
Commit acf0076ae2e5 ("build(fpga): correctly handle gcc as linker for
LTO") pulled in ${TF_LDFLAGS} when building this AXF file, which
includes "--gc-sections". That strips the kernel trampoline off that
file, making the board hang when the kernel is loaded at 0x80200000
(the recommended load address for "newer" kernels).

Drop the usage of TF_LDFLAGS altogether, since we need none of the
options specified there for our special linker step. Instead collect
the needed options (like -nostdlib) in a separate variable, and just
account for the slight syntax differences between GCC and clang.
"--strip-debug" turns out to be redundant, since "-s" already strips
more symbols, so remove that from the list.

Change-Id: I1349d58fa93973ba3add8cab2272259abdea84e0
Fixes: acf0076ae2e5 ("build(fpga): correctly handle gcc as linker for LTO")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables

build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).

These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:

make --silent V=1

... results in a silent build.

In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.

When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed but not echoed'

When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed and echoed'

In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:

$(s)echo 'This command is executed but not echoed'
$(q)echo 'This command is executed but not echoed'

The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.

Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>

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chore: rename Blackhawk to Cortex-X925

Rename Blackhawk to Cortex-X925.

Change-Id: I51e40a7bc6b8871c53c40d1f341853b1fd7fdf71
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

chore: rename Chaberton to Cortex-A725

Rename Chaberton to Cortex-A725.

Change-Id: I981b22d3b37f1aa6e25ff1f35aa156fff9c30076
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

build(fpga): correctly handle gcc as linker for LTO

When LTO is enabled and gcc is used as a linker, then option for a
linker have to be provided with a -Wl prefix to gcc.

To build PLAT=arm_fpga wi

build(fpga): correctly handle gcc as linker for LTO

When LTO is enabled and gcc is used as a linker, then option for a
linker have to be provided with a -Wl prefix to gcc.

To build PLAT=arm_fpga with LTO enabled extra '-nostdlib' has to be
supplied to the linker at least, otherwise build fails with an error
about many undefined references in libc.
Since this option is defined as part of common TF_LDFLAGS already,
just use that variable with couple extra options.

Change-Id: Iaab72d894317c91af5b7d770652e4353b32aae88
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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Merge "build: use new toolchain variables for tools" into integration

build: use new toolchain variables for tools

This change migrates the values of `CC`, `CPP`, `AS` and other toolchain
variables to the new `$(toolchain)-$(tool)` variables, which were
introduced by

build: use new toolchain variables for tools

This change migrates the values of `CC`, `CPP`, `AS` and other toolchain
variables to the new `$(toolchain)-$(tool)` variables, which were
introduced by the toolchain refactor patch. These variables should be
equivalent to the values that they're replacing.

Change-Id: I644fe4ce82ef1894bed129ddb4b6ab94fb04985d
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(arm_fpga): halve number of PEs per core

When creating the Arm FPGA platform, we had plenty of memory available,
so assigned a generous four PEs per core for the potential CPU topology.
In realit

fix(arm_fpga): halve number of PEs per core

When creating the Arm FPGA platform, we had plenty of memory available,
so assigned a generous four PEs per core for the potential CPU topology.
In reality we barely see implementations with two PEs per core, and
didn't have four at all so far.

With some design changes we now include more data per CPU type, and
since the Arm FPGA build supports many cores (and determines the correct
one at runtime), we run out of memory with certain build options.

Since we don't really need four PEs per core, just halve that number, to
reduce our memory footprint without sacrificing functionality.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ieb37ccc9f362b10ff0ce038f72efca21512a71cb

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fix(build): disable ENABLE_FEAT_MPAM for Aarch32

Disable FEAT_MPAM support for Aarch32 as it is not supported, following
[1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in
arch_features.mk,

fix(build): disable ENABLE_FEAT_MPAM for Aarch32

Disable FEAT_MPAM support for Aarch32 as it is not supported, following
[1]. ENABLE_FEAT_MPAM is set to 2 by default for Aarch64 in
arch_features.mk, eliminating the need for duplication in the platform
makefile.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/23710

Change-Id: I1c8b6844254e00e6372900f1c87f995f292ae65c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(mpam): refine MPAM initialization and enablement process

Restricts MPAM to only NS world and enables trap to EL3 for access of
MPAM registers from lower ELs of Secure and Realm world.

This patc

fix(mpam): refine MPAM initialization and enablement process

Restricts MPAM to only NS world and enables trap to EL3 for access of
MPAM registers from lower ELs of Secure and Realm world.

This patch removes MPAM enablement from global context and adds it to
EL3 State context which enables/disables MPAM during world switches.
Renamed ENABLE_MPAM_FOR_LOWER_ELS to ENABLE_FEAT_MPAM and
removed mpam_init_el3() as RESET behaviour is trapping.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I131f9dba5df236a71959b2d425ee11af7f3c38c4

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