1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 35# progbits limit. We need a way to build all useful configurations while waiting 36# on the fvp to increase its SRAM size. The problem is twofild: 37# 1. the cleanup that introduced these enables cleaned up tf-a a little too 38# well and things that previously (incorrectly) were enabled, no longer are. 39# A bunch of CI configs build subtly incorrectly and this combo makes it 40# necessary to forcefully and unconditionally enable them here. 41# 2. the progbits limit is exceeded only when the tsp is involved. However, 42# there are tsp CI configs that run on very high architecture revisions so 43# disabling everything isn't an option. 44# The fix is to enable everything, as before. When the tsp is included, though, 45# we need to slim the size down. In that case, disable all optional features, 46# that will not be present in CI when the tsp is. 47# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 48# for it. 49# TODO: make all of this unconditional (or only base the condition on 50# ARM_ARCH_* when the makefile supports it). 51ifneq (${DRTM_SUPPORT}, 1) 52ifneq (${SPD}, tspd) 53 ENABLE_FEAT_AMU := 2 54 ENABLE_FEAT_AMUv1p1 := 2 55 ENABLE_FEAT_HCX := 2 56 ENABLE_FEAT_MPAM := 2 57 ENABLE_FEAT_RNG := 2 58 ENABLE_FEAT_TWED := 2 59 ENABLE_FEAT_GCS := 2 60 ENABLE_FEAT_RAS := 2 61ifeq (${ARCH}, aarch64) 62ifneq (${SPD}, spmd) 63ifeq (${SPM_MM}, 0) 64ifeq (${CTX_INCLUDE_FPREGS}, 0) 65 ENABLE_SME_FOR_NS := 2 66 ENABLE_SME2_FOR_NS := 2 67endif 68endif 69endif 70endif 71endif 72 73# enable unconditionally for all builds 74ifeq (${ARCH}, aarch64) 75ifeq (${ENABLE_RME},0) 76 ENABLE_BRBE_FOR_NS := 2 77endif 78endif 79ENABLE_TRBE_FOR_NS := 2 80ENABLE_SYS_REG_TRACE_FOR_NS := 2 81ENABLE_FEAT_CSV2_2 := 2 82ENABLE_FEAT_DIT := 2 83ENABLE_FEAT_PAN := 2 84ENABLE_FEAT_MTE_PERM := 2 85ENABLE_FEAT_VHE := 2 86CTX_INCLUDE_NEVE_REGS := 2 87ENABLE_FEAT_SEL2 := 2 88ENABLE_TRF_FOR_NS := 2 89ENABLE_FEAT_ECV := 2 90ENABLE_FEAT_FGT := 2 91ENABLE_FEAT_TCR2 := 2 92ENABLE_FEAT_S2PIE := 2 93ENABLE_FEAT_S1PIE := 2 94ENABLE_FEAT_S2POE := 2 95ENABLE_FEAT_S1POE := 2 96endif 97 98# The FVP platform depends on this macro to build with correct GIC driver. 99$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 100 101# Pass FVP_CLUSTER_COUNT to the build system. 102$(eval $(call add_define,FVP_CLUSTER_COUNT)) 103 104# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 105$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 106 107# Pass FVP_MAX_PE_PER_CPU to the build system. 108$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 109 110# Pass FVP_GICR_REGION_PROTECTION to the build system. 111$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 112 113# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 114$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 115 116# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 117# choose the CCI driver , else the CCN driver 118ifeq ($(FVP_CLUSTER_COUNT), 0) 119$(error "Incorrect cluster count specified for FVP port") 120else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 121FVP_INTERCONNECT_DRIVER := FVP_CCI 122else 123FVP_INTERCONNECT_DRIVER := FVP_CCN 124endif 125 126$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 127 128# Choose the GIC sources depending upon the how the FVP will be invoked 129ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 130 131# The GIC model (GIC-600 or GIC-500) will be detected at runtime 132GICV3_SUPPORT_GIC600 := 1 133GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 134 135# Include GICv3 driver files 136include drivers/arm/gic/v3/gicv3.mk 137 138FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 139 plat/common/plat_gicv3.c \ 140 plat/arm/common/arm_gicv3.c 141 142 ifeq ($(filter 1,${RESET_TO_BL2} \ 143 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 144 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 145 endif 146 147else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 148 149# No GICv4 extension 150GIC_ENABLE_V4_EXTN := 0 151$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 152 153# Include GICv2 driver files 154include drivers/arm/gic/v2/gicv2.mk 155 156FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 157 plat/common/plat_gicv2.c \ 158 plat/arm/common/arm_gicv2.c 159 160FVP_DT_PREFIX := fvp-base-gicv2-psci 161else 162$(error "Incorrect GIC driver chosen on FVP port") 163endif 164 165ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 166FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 167else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 168FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 169 plat/arm/common/arm_ccn.c 170else 171$(error "Incorrect CCN driver chosen on FVP port") 172endif 173 174FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 175 plat/arm/board/fvp/fvp_security.c \ 176 plat/arm/common/arm_tzc400.c 177 178 179PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 180 -Iinclude/lib/psa 181 182 183PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 184 185FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 186 187ifeq (${ARCH}, aarch64) 188 189# select a different set of CPU files, depending on whether we compile for 190# hardware assisted coherency cores or not 191ifeq (${HW_ASSISTED_COHERENCY}, 0) 192# Cores used without DSU 193 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 194 lib/cpus/aarch64/cortex_a53.S \ 195 lib/cpus/aarch64/cortex_a57.S \ 196 lib/cpus/aarch64/cortex_a72.S \ 197 lib/cpus/aarch64/cortex_a73.S 198else 199# Cores used with DSU only 200 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 201 # AArch64-only cores 202 # TODO: add all cores to the appropriate lists 203 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 204 lib/cpus/aarch64/cortex_a65ae.S \ 205 lib/cpus/aarch64/cortex_a76.S \ 206 lib/cpus/aarch64/cortex_a76ae.S \ 207 lib/cpus/aarch64/cortex_a77.S \ 208 lib/cpus/aarch64/cortex_a78.S \ 209 lib/cpus/aarch64/cortex_a78_ae.S \ 210 lib/cpus/aarch64/cortex_a78c.S \ 211 lib/cpus/aarch64/cortex_a710.S \ 212 lib/cpus/aarch64/neoverse_n_common.S \ 213 lib/cpus/aarch64/neoverse_n1.S \ 214 lib/cpus/aarch64/neoverse_n2.S \ 215 lib/cpus/aarch64/neoverse_v1.S \ 216 lib/cpus/aarch64/neoverse_e1.S \ 217 lib/cpus/aarch64/cortex_x2.S \ 218 lib/cpus/aarch64/cortex_gelas.S \ 219 lib/cpus/aarch64/nevis.S 220 endif 221 # AArch64/AArch32 cores 222 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 223 lib/cpus/aarch64/cortex_a75.S 224endif 225 226else 227FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 228 lib/cpus/aarch32/cortex_a57.S \ 229 lib/cpus/aarch32/cortex_a53.S 230endif 231 232BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 233 drivers/arm/sp805/sp805.c \ 234 drivers/delay_timer/delay_timer.c \ 235 drivers/io/io_semihosting.c \ 236 lib/semihosting/semihosting.c \ 237 lib/semihosting/${ARCH}/semihosting_call.S \ 238 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 239 plat/arm/board/fvp/fvp_bl1_setup.c \ 240 plat/arm/board/fvp/fvp_err.c \ 241 plat/arm/board/fvp/fvp_io_storage.c \ 242 ${FVP_CPU_LIBS} \ 243 ${FVP_INTERCONNECT_SOURCES} 244 245ifeq (${USE_SP804_TIMER},1) 246BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 247else 248BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 249endif 250 251 252BL2_SOURCES += drivers/arm/sp805/sp805.c \ 253 drivers/io/io_semihosting.c \ 254 lib/utils/mem_region.c \ 255 lib/semihosting/semihosting.c \ 256 lib/semihosting/${ARCH}/semihosting_call.S \ 257 plat/arm/board/fvp/fvp_bl2_setup.c \ 258 plat/arm/board/fvp/fvp_err.c \ 259 plat/arm/board/fvp/fvp_io_storage.c \ 260 plat/arm/common/arm_nor_psci_mem_protect.c \ 261 ${FVP_SECURITY_SOURCES} 262 263 264ifeq (${COT_DESC_IN_DTB},1) 265BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 266endif 267 268ifeq (${ENABLE_RME},1) 269BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 270 271BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 272 plat/arm/board/fvp/fvp_realm_attest_key.c 273 274# FVP platform does not support RSS, but it can leverage RSS APIs to 275# provide hardcoded token/key on request. 276BL31_SOURCES += lib/psa/delegated_attestation.c 277 278endif 279 280ifeq (${ENABLE_FEAT_RNG_TRAP},1) 281BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 282endif 283 284ifeq (${RESET_TO_BL2},1) 285BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 286 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 287 ${FVP_CPU_LIBS} \ 288 ${FVP_INTERCONNECT_SOURCES} 289endif 290 291ifeq (${USE_SP804_TIMER},1) 292BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 293endif 294 295BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 296 ${FVP_SECURITY_SOURCES} 297 298ifeq (${USE_SP804_TIMER},1) 299BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 300endif 301 302BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 303 drivers/arm/smmu/smmu_v3.c \ 304 drivers/delay_timer/delay_timer.c \ 305 drivers/cfi/v2m/v2m_flash.c \ 306 lib/utils/mem_region.c \ 307 plat/arm/board/fvp/fvp_bl31_setup.c \ 308 plat/arm/board/fvp/fvp_console.c \ 309 plat/arm/board/fvp/fvp_pm.c \ 310 plat/arm/board/fvp/fvp_topology.c \ 311 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 312 plat/arm/common/arm_nor_psci_mem_protect.c \ 313 ${FVP_CPU_LIBS} \ 314 ${FVP_GIC_SOURCES} \ 315 ${FVP_INTERCONNECT_SOURCES} \ 316 ${FVP_SECURITY_SOURCES} 317 318# Support for fconf in BL31 319# Added separately from the above list for better readability 320ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 321BL31_SOURCES += lib/fconf/fconf.c \ 322 lib/fconf/fconf_dyn_cfg_getter.c \ 323 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 324 325BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 326 327ifeq (${SEC_INT_DESC_IN_FCONF},1) 328BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 329endif 330 331endif 332 333ifeq (${USE_SP804_TIMER},1) 334BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 335else 336BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 337endif 338 339# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 340ifdef UNIX_MK 341FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 342FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 343 ${PLAT}_fw_config.dts \ 344 ${PLAT}_tb_fw_config.dts \ 345 ${PLAT}_soc_fw_config.dts \ 346 ${PLAT}_nt_fw_config.dts \ 347 ) 348 349FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 350FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 351FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 352FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 353 354ifeq (${SPD},tspd) 355FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 356FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 357 358# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 359$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 360endif 361 362ifeq (${SPD},spmd) 363 364ifeq ($(ARM_SPMC_MANIFEST_DTS),) 365ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 366endif 367 368FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 369FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 370 371# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 372$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 373endif 374 375# Add the FW_CONFIG to FIP and specify the same to certtool 376$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 377# Add the TB_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 379# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 380$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 381# Add the NT_FW_CONFIG to FIP and specify the same to certtool 382$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 383 384FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 385$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 386 387# Add the HW_CONFIG to FIP and specify the same to certtool 388$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 389endif 390 391# Enable dynamic mitigation support by default 392DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 393 394ifneq (${ENABLE_FEAT_AMU},0) 395BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 396 lib/cpus/aarch64/cpuamu_helpers.S 397 398ifeq (${HW_ASSISTED_COHERENCY}, 1) 399BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 400 lib/cpus/aarch64/neoverse_n1_pubsub.c 401endif 402endif 403 404ifeq (${RAS_FFH_SUPPORT},1) 405BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 406endif 407 408ifneq (${ENABLE_STACK_PROTECTOR},0) 409PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 410endif 411 412# Enable the dynamic translation tables library. 413ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 414 ifeq (${ARCH},aarch32) 415 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 416 else # AArch64 417 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 418 endif 419endif 420 421ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 422 ifeq (${ARCH},aarch32) 423 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 424 else # AArch64 425 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 426 ifeq (${SPD},tspd) 427 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 428 endif 429 endif 430endif 431 432ifeq (${USE_DEBUGFS},1) 433 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 434endif 435 436# Add support for platform supplied linker script for BL31 build 437$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 438 439ifneq (${RESET_TO_BL2}, 0) 440 override BL1_SOURCES = 441endif 442 443# RSS is not supported on FVP right now. Thus, we use the mocked version 444# of the provided PSA APIs. They return with success and hard-coded token/key. 445PLAT_RSS_NOT_SUPPORTED := 1 446 447# Include Measured Boot makefile before any Crypto library makefile. 448# Crypto library makefile may need default definitions of Measured Boot build 449# flags present in Measured Boot makefile. 450ifeq (${MEASURED_BOOT},1) 451 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 452 $(info Including ${RSS_MEASURED_BOOT_MK}) 453 include ${RSS_MEASURED_BOOT_MK} 454 455 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 456 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 457 endif 458 459 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 460 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 461endif 462 463include plat/arm/board/common/board_common.mk 464include plat/arm/common/arm_common.mk 465 466ifeq (${MEASURED_BOOT},1) 467BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 468 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 469 lib/psa/measured_boot.c 470 471BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 472 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 473 lib/psa/measured_boot.c 474 475# Even though RSS is not supported on FVP (see above), we support overriding 476# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 477# the code to detect any build regressions. The resulting firmware will not be 478# functional. 479ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 480 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 481 include drivers/arm/rss/rss_comms.mk 482 BL1_SOURCES += ${RSS_COMMS_SOURCES} 483 BL2_SOURCES += ${RSS_COMMS_SOURCES} 484 BL31_SOURCES += ${RSS_COMMS_SOURCES} 485 486 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 487 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 488 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 489endif 490 491endif 492 493ifeq (${DRTM_SUPPORT}, 1) 494BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 495 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 496 plat/arm/board/fvp/fvp_drtm_err.c \ 497 plat/arm/board/fvp/fvp_drtm_measurement.c \ 498 plat/arm/board/fvp/fvp_drtm_stub.c \ 499 plat/arm/common/arm_dyn_cfg.c \ 500 plat/arm/board/fvp/fvp_err.c 501endif 502 503ifeq (${TRUSTED_BOARD_BOOT}, 1) 504BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 505BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 506 507# FVP being a development platform, enable capability to disable Authentication 508# dynamically if TRUSTED_BOARD_BOOT is set. 509DYN_DISABLE_AUTH := 1 510endif 511 512ifeq (${SPMC_AT_EL3}, 1) 513PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 514endif 515 516PSCI_OS_INIT_MODE := 1 517 518ifeq (${SPD},spmd) 519BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 520endif 521 522# Test specific macros, keep them at bottom of this file 523$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 524ifeq (${PLATFORM_TEST_EA_FFH}, 1) 525 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 526 $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 527 endif 528BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 529endif 530 531$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 532ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 533 ifeq (${RAS_EXTENSION}, 0) 534 $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") 535 endif 536endif 537 538ifeq (${ERRATA_ABI_SUPPORT}, 1) 539include plat/arm/board/fvp/fvp_cpu_errata.mk 540endif 541 542# Build macro necessary for running SPM tests on FVP platform 543$(eval $(call add_define,PLAT_TEST_SPM)) 544