feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKEDThe FEAT_LSE enablement predates the FEAT_STATE framework and has neverbeen converted. Since the introduction of USE_SPINLOCK_CAS we've
feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKEDThe FEAT_LSE enablement predates the FEAT_STATE framework and has neverbeen converted. Since the introduction of USE_SPINLOCK_CAS we've gainedlots of quality of life features that allow for better featureenablement. This patch converts USE_SPINLOCK_CAS to tri-state and addsit to FEATURE_DETECTION to align with all other features.Instead of introducing the assembly checking for tri-state, this patchtranslates all locking routines to C inline assembly and uses thestandard C helpers. The main benefit is that this gives greatervisibility to the compiler about what the functions are doing and letsit optimise better. Namely, it is able to allocate registers itself andinline the functions when LTO is enabled.An unsuccessful attempt was made to use the instructions directly andhave even flow control in C. This, however, made code very complicatedand less efficient in the tight loops of the spinlock.The last use of ARM_ARCH_AT_LEAST goes away with this change and so thismacro is removed. It has now been fully superseded by the FEAT_STATEframework.This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requiresUSE_SPINLOCK_CAS. This patch does not address this in any way but makesthe relationship explicit.Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56aeSigned-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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fix(locks): mark spin_trylock as a public functionThis patch updates spinlock.S to make the spin_trylock helperfunction as public. This will allow other parts of the TF-Ato use this function.Ch
fix(locks): mark spin_trylock as a public functionThis patch updates spinlock.S to make the spin_trylock helperfunction as public. This will allow other parts of the TF-Ato use this function.Change-Id: Id264a36490707a9377a221ed2b5bd27ca90bf459Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
feat(locks): add non-blocking spinlock_try() APIAdd a non-blocking `spin_trylock()` function to the existing spinlockimplementation. This API attempts to acquire the lock and returns `1`on succes
feat(locks): add non-blocking spinlock_try() APIAdd a non-blocking `spin_trylock()` function to the existing spinlockimplementation. This API attempts to acquire the lock and returns `1`on success or `0` if the lock is already held. It enables conditionallocking scenarios where blocking is undesirable.Change-Id: I9483206952d1a34dc245ebf69e80c3645b658946Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
chore: update to use Arm word across TF-AAlign entire TF-A to use Arm in copyright header.Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244Signed-off-by: Govindraj Raja <govindraj.raja@arm.co
chore: update to use Arm word across TF-AAlign entire TF-A to use Arm in copyright header.Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
ARMv7 does not support STL instructionAlso need to add a SEV instruction in ARMv7 spin_unlock whichis implicit in ARMv8.Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Use SPDX license identifiersTo make software license auditing simpler, use SPDX[0] licenseidentifiers instead of duplicating the license text in every file.NOTE: Files that have been imported by
Use SPDX license identifiersTo make software license auditing simpler, use SPDX[0] licenseidentifiers instead of duplicating the license text in every file.NOTE: Files that have been imported by FreeBSD have not been modified.[0]: https://spdx.org/Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761aSigned-off-by: dp-arm <dimitris.papastamos@arm.com>
AArch32: Add support in TF librariesThis patch adds AArch32 support to cpu ops, context management,per-cpu data and spinlock libraries. The `entrypoint_info`structure is modified to add support f
AArch32: Add support in TF librariesThis patch adds AArch32 support to cpu ops, context management,per-cpu data and spinlock libraries. The `entrypoint_info`structure is modified to add support for AArch32 registerarguments. The CPU operations for AEM generic cpu in AArch32mode is also added.Change-Id: I1e52e79f498661d8f31f1e7b3a29e222bc7a4483