1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 #include <plat_arm.h> 22 23 #include <plat_fdt.h> 24 #include <plat_private.h> 25 #include <plat_startup.h> 26 #include <pm_api_sys.h> 27 #include <pm_client.h> 28 #include <pm_ipi.h> 29 #include <versal_net_def.h> 30 31 static entry_point_info_t bl32_image_ep_info; 32 static entry_point_info_t bl33_image_ep_info; 33 34 /* 35 * Return a pointer to the 'entry_point_info' structure of the next image for 36 * the security state specified. BL33 corresponds to the non-secure image type 37 * while BL32 corresponds to the secure image type. A NULL pointer is returned 38 * if the image does not exist. 39 */ 40 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 41 { 42 assert(sec_state_is_valid(type)); 43 44 if (type == NON_SECURE) { 45 return &bl33_image_ep_info; 46 } 47 48 return &bl32_image_ep_info; 49 } 50 51 /* 52 * Set the build time defaults,if we can't find any config data. 53 */ 54 static inline void bl31_set_default_config(void) 55 { 56 bl32_image_ep_info.pc = BL32_BASE; 57 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 58 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 59 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 60 DISABLE_ALL_EXCEPTIONS); 61 } 62 63 /* 64 * Perform any BL31 specific platform actions. Here is an opportunity to copy 65 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 66 * are lost (potentially). This needs to be done before the MMU is initialized 67 * so that the memory layout can be used while creating page tables. 68 */ 69 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 70 u_register_t arg2, u_register_t arg3) 71 { 72 uint32_t uart_clock; 73 int32_t rc; 74 #if !(TFA_NO_PM) 75 uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0}; 76 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 77 enum pm_ret_status ret_status; 78 #endif /* !(TFA_NO_PM) */ 79 80 board_detection(); 81 82 switch (platform_id) { 83 case VERSAL_NET_SPP: 84 cpu_clock = 1000000; 85 uart_clock = 1000000; 86 break; 87 case VERSAL_NET_EMU: 88 cpu_clock = 3660000; 89 uart_clock = 25000000; 90 break; 91 case VERSAL_NET_QEMU: 92 /* Random values now */ 93 cpu_clock = 100000000; 94 uart_clock = 25000000; 95 break; 96 case VERSAL_NET_SILICON: 97 cpu_clock = 100000000; 98 uart_clock = 100000000; 99 break; 100 default: 101 panic(); 102 } 103 104 if (VERSAL_NET_CONSOLE_IS(pl011_0) || VERSAL_NET_CONSOLE_IS(pl011_1)) { 105 static console_t versal_net_runtime_console; 106 107 /* Initialize the console to provide early debug support */ 108 rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock, 109 VERSAL_NET_UART_BAUDRATE, 110 &versal_net_runtime_console); 111 if (rc == 0) { 112 panic(); 113 } 114 115 console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT | 116 CONSOLE_FLAG_RUNTIME); 117 } else if (VERSAL_NET_CONSOLE_IS(dcc)) { 118 /* Initialize the dcc console for debug. 119 * dcc is over jtag and does not configures uart0 or uart1. 120 */ 121 rc = console_dcc_register(); 122 if (rc == 0) { 123 panic(); 124 } 125 } 126 127 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 128 platform_version / 10U, platform_version % 10U); 129 130 /* Initialize the platform config for future decision making */ 131 versal_net_config_setup(); 132 133 /* 134 * Do initial security configuration to allow DRAM/device access. On 135 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but 136 * other platforms might have more programmable security devices 137 * present. 138 */ 139 140 /* Populate common information for BL32 and BL33 */ 141 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 142 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 143 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 144 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 145 #if !(TFA_NO_PM) 146 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 147 (uintptr_t)buff >> 32U, (uintptr_t)buff, max_size); 148 149 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 150 if (ret_status == PM_RET_SUCCESS) { 151 enum xbl_handoff xbl_ret; 152 153 tfa_handoff_addr = (uintptr_t)&buff; 154 155 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, 156 tfa_handoff_addr); 157 if (xbl_ret != XBL_HANDOFF_SUCCESS) { 158 ERROR("BL31: PLM to TF-A handover failed %u\n", xbl_ret); 159 panic(); 160 } 161 162 INFO("BL31: PLM to TF-A handover success\n"); 163 } else { 164 INFO("BL31: setting up default configs\n"); 165 166 bl31_set_default_config(); 167 } 168 #else 169 bl31_set_default_config(); 170 #endif /* !(TFA_NO_PM) */ 171 172 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 173 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 174 } 175 176 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 177 178 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 179 { 180 static uint32_t index; 181 uint32_t i; 182 183 /* Validate 'handler' and 'id' parameters */ 184 if (handler == NULL || index >= MAX_INTR_EL3) { 185 return -EINVAL; 186 } 187 188 /* Check if a handler has already been registered */ 189 for (i = 0; i < index; i++) { 190 if (id == type_el3_interrupt_table[i].id) { 191 return -EALREADY; 192 } 193 } 194 195 type_el3_interrupt_table[index].id = id; 196 type_el3_interrupt_table[index].handler = handler; 197 198 index++; 199 200 return 0; 201 } 202 203 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 204 void *handle, void *cookie) 205 { 206 uint32_t intr_id; 207 uint32_t i; 208 interrupt_type_handler_t handler = NULL; 209 210 intr_id = plat_ic_get_pending_interrupt_id(); 211 212 for (i = 0; i < MAX_INTR_EL3; i++) { 213 if (intr_id == type_el3_interrupt_table[i].id) { 214 handler = type_el3_interrupt_table[i].handler; 215 } 216 } 217 218 if (handler != NULL) { 219 handler(intr_id, flags, handle, cookie); 220 } 221 222 return 0; 223 } 224 225 void bl31_platform_setup(void) 226 { 227 prepare_dtb(); 228 229 /* Initialize the gic cpu and distributor interfaces */ 230 plat_versal_net_gic_driver_init(); 231 plat_versal_net_gic_init(); 232 } 233 234 void bl31_plat_runtime_setup(void) 235 { 236 uint64_t flags = 0; 237 int32_t rc; 238 239 set_interrupt_rm_flag(flags, NON_SECURE); 240 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 241 rdo_el3_interrupt_handler, flags); 242 if (rc != 0) { 243 panic(); 244 } 245 } 246 247 /* 248 * Perform the very early platform specific architectural setup here. 249 */ 250 void bl31_plat_arch_setup(void) 251 { 252 const mmap_region_t bl_regions[] = { 253 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 254 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 255 MT_MEMORY | MT_RW | MT_NS), 256 #endif 257 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 258 MT_MEMORY | MT_RW | MT_SECURE), 259 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 260 MT_CODE | MT_SECURE), 261 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 262 MT_RO_DATA | MT_SECURE), 263 {0} 264 }; 265 266 setup_page_tables(bl_regions, plat_versal_net_get_mmap()); 267 enable_mmu(0); 268 } 269