1 /* 2 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <dram.h> 25 #include <gpc.h> 26 #include <imx_aipstz.h> 27 #include <imx_uart.h> 28 #include <imx_rdc.h> 29 #include <imx8m_caam.h> 30 #include <imx8m_ccm.h> 31 #include <imx8m_csu.h> 32 #include <plat_imx8.h> 33 34 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 35 36 /* 37 * Note: DRAM region is mapped with entire size available and uses MT_RW 38 * attributes. 39 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section 40 * for explanation of this mapping scheme. 41 */ 42 static const mmap_region_t imx_mmap[] = { 43 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), 44 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 45 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */ 46 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */ 47 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */ 48 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */ 49 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */ 50 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM code */ 51 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* DRAM */ 52 {0}, 53 }; 54 55 static const struct aipstz_cfg aipstz[] = { 56 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 57 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 58 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 59 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 60 {0}, 61 }; 62 63 static const struct imx_rdc_cfg rdc[] = { 64 /* Master domain assignment */ 65 RDC_MDAn(RDC_MDA_M4, DID1), 66 67 /* peripherals domain permission */ 68 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 69 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 70 71 /* memory region */ 72 73 /* Sentinel */ 74 {0}, 75 }; 76 77 static const struct imx_csu_cfg csu_cfg[] = { 78 /* peripherals csl setting */ 79 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED), 80 81 /* master HP0~1 */ 82 83 /* SA setting */ 84 85 /* HP control setting */ 86 87 /* Sentinel */ 88 {0} 89 }; 90 91 static entry_point_info_t bl32_image_ep_info; 92 static entry_point_info_t bl33_image_ep_info; 93 94 /* get SPSR for BL33 entry */ 95 static uint32_t get_spsr_for_bl33_entry(void) 96 { 97 unsigned long el_status; 98 unsigned long mode; 99 uint32_t spsr; 100 101 /* figure out what mode we enter the non-secure world */ 102 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 103 el_status &= ID_AA64PFR0_ELX_MASK; 104 105 mode = (el_status) ? MODE_EL2 : MODE_EL1; 106 107 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 108 return spsr; 109 } 110 111 void bl31_tzc380_setup(void) 112 { 113 unsigned int val; 114 115 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 116 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 117 return; 118 119 tzc380_init(IMX_TZASC_BASE); 120 121 /* 122 * Need to substact offset 0x40000000 from CPU address when 123 * programming tzasc region for i.mx8mm. 124 */ 125 126 /* Enable 1G-5G S/NS RW */ 127 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 128 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 129 } 130 131 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 132 u_register_t arg2, u_register_t arg3) 133 { 134 unsigned int console_base = IMX_BOOT_UART_BASE; 135 static console_t console; 136 int i; 137 138 /* Enable CSU NS access permission */ 139 for (i = 0; i < 64; i++) { 140 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 141 } 142 143 imx_aipstz_init(aipstz); 144 145 imx_rdc_init(rdc); 146 147 imx_csu_init(csu_cfg); 148 149 if (console_base == 0U) { 150 console_base = imx8m_uart_get_base(); 151 } 152 153 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 154 IMX_CONSOLE_BAUDRATE, &console); 155 /* This console is only used for boot stage */ 156 console_set_scope(&console, CONSOLE_FLAG_BOOT); 157 158 imx8m_caam_init(); 159 160 /* 161 * tell BL3-1 where the non-secure software image is located 162 * and the entry state information. 163 */ 164 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 165 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 166 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 167 168 #if defined(SPD_opteed) || defined(SPD_trusty) 169 /* Populate entry point information for BL32 */ 170 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 171 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 172 bl32_image_ep_info.pc = BL32_BASE; 173 bl32_image_ep_info.spsr = 0; 174 175 /* Pass TEE base and size to bl33 */ 176 bl33_image_ep_info.args.arg1 = BL32_BASE; 177 bl33_image_ep_info.args.arg2 = BL32_SIZE; 178 179 #ifdef SPD_trusty 180 bl32_image_ep_info.args.arg0 = BL32_SIZE; 181 bl32_image_ep_info.args.arg1 = BL32_BASE; 182 #else 183 /* Make sure memory is clean */ 184 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 185 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 186 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 187 #endif 188 #endif 189 190 bl31_tzc380_setup(); 191 } 192 193 #define MAP_BL31_TOTAL \ 194 MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE) 195 #define MAP_BL31_RO \ 196 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 197 #define MAP_COHERENT_MEM \ 198 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ 199 MT_DEVICE | MT_RW | MT_SECURE) 200 #define MAP_BL32_TOTAL \ 201 MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 202 203 void bl31_plat_arch_setup(void) 204 { 205 const mmap_region_t bl_regions[] = { 206 MAP_BL31_TOTAL, 207 MAP_BL31_RO, 208 #if USE_COHERENT_MEM 209 MAP_COHERENT_MEM, 210 #endif 211 /* Map TEE memory */ 212 MAP_BL32_TOTAL, 213 {0} 214 }; 215 216 setup_page_tables(bl_regions, imx_mmap); 217 enable_mmu_el3(0); 218 } 219 220 void bl31_platform_setup(void) 221 { 222 generic_delay_timer_init(); 223 224 /* select the CKIL source to 32K OSC */ 225 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 226 227 /* Init the dram info */ 228 dram_info_init(SAVED_DRAM_TIMING_BASE); 229 230 plat_gic_driver_init(); 231 plat_gic_init(); 232 233 imx_gpc_init(); 234 } 235 236 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 237 { 238 if (type == NON_SECURE) 239 return &bl33_image_ep_info; 240 if (type == SECURE) 241 return &bl32_image_ep_info; 242 243 return NULL; 244 } 245 246 unsigned int plat_get_syscnt_freq2(void) 247 { 248 return COUNTER_FREQUENCY; 249 } 250 251 #ifdef SPD_trusty 252 void plat_trusty_set_boot_args(aapcs64_params_t *args) 253 { 254 args->arg0 = BL32_SIZE; 255 args->arg1 = BL32_BASE; 256 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 257 } 258 #endif 259