1/* 2 * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 sysreg_bit_clear sctlr_el3, SCTLR_C_BIT 19 isb 20 ret 21endfunc cortex_a73_disable_dcache 22 23 /* --------------------------------------------- 24 * Disable intra-cluster coherency 25 * --------------------------------------------- 26 */ 27func cortex_a73_disable_smp 28 sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 29 isb 30 dsb sy 31 ret 32endfunc cortex_a73_disable_smp 33 34func check_smccc_arch_workaround_3 35 mov x0, #ERRATA_APPLIES 36 ret 37endfunc check_smccc_arch_workaround_3 38 39workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 40 sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12) 41workaround_reset_end cortex_a73, ERRATUM(852427) 42 43check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) 44 45workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 46 sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7) 47workaround_reset_end cortex_a73, ERRATUM(855423) 48 49check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) 50 51workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 52#if IMAGE_BL31 53 override_vector_table wa_cve_2017_5715_bpiall_vbar 54#endif /* IMAGE_BL31 */ 55workaround_reset_end cortex_a73, CVE(2017, 5715) 56 57check_erratum_custom_start cortex_a73, CVE(2017, 5715) 58 cpu_check_csv2 x0, 1f 59#if WORKAROUND_CVE_2017_5715 60 mov x0, #ERRATA_APPLIES 61#else 62 mov x0, #ERRATA_MISSING 63#endif 64 ret 651: 66 mov x0, #ERRATA_NOT_APPLIES 67 ret 68check_erratum_custom_end cortex_a73, CVE(2017, 5715) 69 70workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 71 sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 72workaround_reset_end cortex_a73, CVE(2018, 3639) 73 74check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 75 76workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 77#if IMAGE_BL31 78 /* Skip installing vector table again for CVE_2022_23960 */ 79 override_vector_table wa_cve_2017_5715_bpiall_vbar 80 cmp x0, x1 81 b.eq 1f 82 msr vbar_el3, x0 831: 84#endif /* IMAGE_BL31 */ 85workaround_reset_end cortex_a73, CVE(2022, 23960) 86 87check_erratum_custom_start cortex_a73, CVE(2022, 23960) 88#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 89 cpu_check_csv2 x0, 1f 90 mov x0, #ERRATA_APPLIES 91 ret 92 1: 93#if WORKAROUND_CVE_2022_23960 94 mov x0, #ERRATA_APPLIES 95#else 96 mov x0, #ERRATA_MISSING 97#endif /* WORKAROUND_CVE_2022_23960 */ 98 ret 99#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 100 mov x0, #ERRATA_MISSING 101 ret 102check_erratum_custom_end cortex_a73, CVE(2022, 23960) 103 104 /* ------------------------------------------------- 105 * The CPU Ops reset function for Cortex-A73. 106 * ------------------------------------------------- 107 */ 108 109cpu_reset_func_start cortex_a73 110 /* --------------------------------------------- 111 * Enable the SMP bit. 112 * Clobbers : x0 113 * --------------------------------------------- 114 */ 115 sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT 116cpu_reset_func_end cortex_a73 117 118func cortex_a73_core_pwr_dwn 119 mov x18, x30 120 121 /* --------------------------------------------- 122 * Turn off caches. 123 * --------------------------------------------- 124 */ 125 bl cortex_a73_disable_dcache 126 127 /* --------------------------------------------- 128 * Flush L1 caches. 129 * --------------------------------------------- 130 */ 131 mov x0, #DCCISW 132 bl dcsw_op_level1 133 134 /* --------------------------------------------- 135 * Come out of intra cluster coherency 136 * --------------------------------------------- 137 */ 138 mov x30, x18 139 b cortex_a73_disable_smp 140endfunc cortex_a73_core_pwr_dwn 141 142func cortex_a73_cluster_pwr_dwn 143 mov x18, x30 144 145 /* --------------------------------------------- 146 * Turn off caches. 147 * --------------------------------------------- 148 */ 149 bl cortex_a73_disable_dcache 150 151 /* --------------------------------------------- 152 * Flush L1 caches. 153 * --------------------------------------------- 154 */ 155 mov x0, #DCCISW 156 bl dcsw_op_level1 157 158 /* --------------------------------------------- 159 * Disable the optional ACP. 160 * --------------------------------------------- 161 */ 162 bl plat_disable_acp 163 164 /* --------------------------------------------- 165 * Flush L2 caches. 166 * --------------------------------------------- 167 */ 168 mov x0, #DCCISW 169 bl dcsw_op_level2 170 171 /* --------------------------------------------- 172 * Come out of intra cluster coherency 173 * --------------------------------------------- 174 */ 175 mov x30, x18 176 b cortex_a73_disable_smp 177endfunc cortex_a73_cluster_pwr_dwn 178 179 180errata_report_shim cortex_a73 181 182 /* --------------------------------------------- 183 * This function provides cortex_a73 specific 184 * register information for crash reporting. 185 * It needs to return with x6 pointing to 186 * a list of register names in ascii and 187 * x8 - x15 having values of registers to be 188 * reported. 189 * --------------------------------------------- 190 */ 191.section .rodata.cortex_a73_regs, "aS" 192cortex_a73_regs: /* The ascii list of register names to be reported */ 193 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 194 195func cortex_a73_cpu_reg_dump 196 adr x6, cortex_a73_regs 197 mrs x8, CORTEX_A73_CPUECTLR_EL1 198 mrs x9, CORTEX_A73_L2MERRSR_EL1 199 ret 200endfunc cortex_a73_cpu_reg_dump 201 202declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 203 cortex_a73_reset_func, \ 204 check_erratum_cortex_a73_5715, \ 205 CPU_NO_EXTRA2_FUNC, \ 206 check_smccc_arch_workaround_3, \ 207 cortex_a73_core_pwr_dwn, \ 208 cortex_a73_cluster_pwr_dwn 209