1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <lib/el3_runtime/pubsub_events.h> 16 #include <plat/common/platform.h> 17 18 #include "psci_private.h" 19 20 /* 21 * Helper functions for the CPU level spinlocks 22 */ 23 static inline void psci_spin_lock_cpu(unsigned int idx) 24 { 25 spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock); 26 } 27 28 static inline void psci_spin_unlock_cpu(unsigned int idx) 29 { 30 spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock); 31 } 32 33 /******************************************************************************* 34 * This function checks whether a cpu which has been requested to be turned on 35 * is OFF to begin with. 36 ******************************************************************************/ 37 static int cpu_on_validate_state(aff_info_state_t aff_state) 38 { 39 if (aff_state == AFF_STATE_ON) 40 return PSCI_E_ALREADY_ON; 41 42 if (aff_state == AFF_STATE_ON_PENDING) 43 return PSCI_E_ON_PENDING; 44 45 assert(aff_state == AFF_STATE_OFF); 46 return PSCI_E_SUCCESS; 47 } 48 49 /******************************************************************************* 50 * Generic handler which is called to physically power on a cpu identified by 51 * its mpidr. It performs the generic, architectural, platform setup and state 52 * management to power on the target cpu e.g. it will ensure that 53 * enough information is stashed for it to resume execution in the non-secure 54 * security state. 55 * 56 * The state of all the relevant power domains are changed after calling the 57 * platform handler as it can return error. 58 ******************************************************************************/ 59 int psci_cpu_on_start(u_register_t target_cpu, 60 const entry_point_info_t *ep) 61 { 62 int rc; 63 aff_info_state_t target_aff_state; 64 int ret = plat_core_pos_by_mpidr(target_cpu); 65 unsigned int target_idx; 66 67 /* Calling function must supply valid input arguments */ 68 assert(ret >= 0); 69 assert((unsigned int)ret < PLATFORM_CORE_COUNT); 70 assert(ep != NULL); 71 72 target_idx = (unsigned int)ret; 73 74 /* 75 * This function must only be called on platforms where the 76 * CPU_ON platform hooks have been implemented. 77 */ 78 assert((psci_plat_pm_ops->pwr_domain_on != NULL) && 79 (psci_plat_pm_ops->pwr_domain_on_finish != NULL)); 80 81 /* Protect against multiple CPUs trying to turn ON the same target CPU */ 82 psci_spin_lock_cpu(target_idx); 83 84 /* 85 * Generic management: Ensure that the cpu is off to be 86 * turned on. 87 * Perform cache maintanence ahead of reading the target CPU state to 88 * ensure that the data is not stale. 89 * There is a theoretical edge case where the cache may contain stale 90 * data for the target CPU data - this can occur under the following 91 * conditions: 92 * - the target CPU is in another cluster from the current 93 * - the target CPU was the last CPU to shutdown on its cluster 94 * - the cluster was removed from coherency as part of the CPU shutdown 95 * 96 * In this case the cache maintenace that was performed as part of the 97 * target CPUs shutdown was not seen by the current CPU's cluster. And 98 * so the cache may contain stale data for the target CPU. 99 */ 100 flush_cpu_data_by_index(target_idx, 101 psci_svc_cpu_data.aff_info_state); 102 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); 103 if (rc != PSCI_E_SUCCESS) 104 goto exit; 105 106 /* 107 * Call the cpu on handler registered by the Secure Payload Dispatcher 108 * to let it do any bookeeping. If the handler encounters an error, it's 109 * expected to assert within 110 */ 111 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL)) 112 psci_spd_pm->svc_on(target_cpu); 113 114 /* 115 * Set the Affinity info state of the target cpu to ON_PENDING. 116 * Flush aff_info_state as it will be accessed with caches 117 * turned OFF. 118 */ 119 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 120 flush_cpu_data_by_index(target_idx, 121 psci_svc_cpu_data.aff_info_state); 122 123 /* 124 * The cache line invalidation by the target CPU after setting the 125 * state to OFF (see psci_do_cpu_off()), could cause the update to 126 * aff_info_state to be invalidated. Retry the update if the target 127 * CPU aff_info_state is not ON_PENDING. 128 */ 129 target_aff_state = psci_get_aff_info_state_by_idx(target_idx); 130 if (target_aff_state != AFF_STATE_ON_PENDING) { 131 assert(target_aff_state == AFF_STATE_OFF); 132 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 133 flush_cpu_data_by_index(target_idx, 134 psci_svc_cpu_data.aff_info_state); 135 136 assert(psci_get_aff_info_state_by_idx(target_idx) == 137 AFF_STATE_ON_PENDING); 138 } 139 140 /* 141 * Perform generic, architecture and platform specific handling. 142 */ 143 /* 144 * Plat. management: Give the platform the current state 145 * of the target cpu to allow it to perform the necessary 146 * steps to power on. 147 */ 148 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); 149 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); 150 151 if (rc == PSCI_E_SUCCESS) 152 /* Store the re-entry information for the non-secure world. */ 153 cm_init_context_by_index(target_idx, ep); 154 else { 155 /* Restore the state on error. */ 156 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); 157 flush_cpu_data_by_index(target_idx, 158 psci_svc_cpu_data.aff_info_state); 159 } 160 161 exit: 162 psci_spin_unlock_cpu(target_idx); 163 return rc; 164 } 165 166 /******************************************************************************* 167 * The following function finish an earlier power on request. They 168 * are called by the common finisher routine in psci_common.c. The `state_info` 169 * is the psci_power_state from which this CPU has woken up from. 170 ******************************************************************************/ 171 void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info) 172 { 173 /* 174 * Plat. management: Perform the platform specific actions 175 * for this cpu e.g. enabling the gic or zeroing the mailbox 176 * register. The actual state of this cpu has already been 177 * changed. 178 */ 179 psci_plat_pm_ops->pwr_domain_on_finish(state_info); 180 181 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 182 /* 183 * Arch. management: Enable data cache and manage stack memory 184 */ 185 psci_do_pwrup_cache_maintenance(); 186 #endif 187 188 /* 189 * Plat. management: Perform any platform specific actions which 190 * can only be done with the cpu and the cluster guaranteed to 191 * be coherent. 192 */ 193 if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) 194 psci_plat_pm_ops->pwr_domain_on_finish_late(state_info); 195 196 /* 197 * All the platform specific actions for turning this cpu 198 * on have completed. Perform enough arch.initialization 199 * to run in the non-secure address space. 200 */ 201 psci_arch_setup(); 202 203 /* 204 * Lock the CPU spin lock to make sure that the context initialization 205 * is done. Since the lock is only used in this function to create 206 * a synchronization point with cpu_on_start(), it can be released 207 * immediately. 208 */ 209 psci_spin_lock_cpu(cpu_idx); 210 psci_spin_unlock_cpu(cpu_idx); 211 212 /* Ensure we have been explicitly woken up by another cpu */ 213 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); 214 215 /* 216 * Call the cpu on finish handler registered by the Secure Payload 217 * Dispatcher to let it do any bookeeping. If the handler encounters an 218 * error, it's expected to assert within 219 */ 220 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL)) 221 psci_spd_pm->svc_on_finish(0); 222 223 PUBLISH_EVENT(psci_cpu_on_finish); 224 225 /* Populate the mpidr field within the cpu node array */ 226 /* This needs to be done only once */ 227 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; 228 } 229