1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * Copyright (C) 2017-2023 Nuvoton Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <drivers/ti/uart/uart_16550.h> 18 #include <lib/debugfs.h> 19 #include <lib/extensions/ras.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 #include <npcm845x_clock.h> 23 #include <npcm845x_gcr.h> 24 #include <npcm845x_lpuart.h> 25 #include <plat/arm/common/plat_arm.h> 26 #include <plat/common/platform.h> 27 #include <plat_npcm845x.h> 28 #include <platform_def.h> 29 30 /* 31 * Placeholder variables for copying the arguments that have been passed to 32 * BL31 from BL2. 33 */ 34 static entry_point_info_t bl32_image_ep_info; 35 static entry_point_info_t bl33_image_ep_info; 36 37 #if !RESET_TO_BL31 38 /* 39 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 40 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 41 */ 42 /* CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); */ 43 #endif /* !RESET_TO_BL31 */ 44 45 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 46 BL31_START, \ 47 BL31_END - BL31_START, \ 48 MT_MEMORY | MT_RW | EL3_PAS) 49 50 #if RECLAIM_INIT_CODE 51 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 52 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 53 54 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 55 ~(PAGE_SIZE - 1)) 56 57 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 58 BL_INIT_CODE_BASE, \ 59 BL_INIT_CODE_END - \ 60 BL_INIT_CODE_BASE, \ 61 MT_CODE | MT_SECURE) 62 #endif /* RECLAIM_INIT_CODE */ 63 64 #if SEPARATE_NOBITS_REGION 65 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 66 BL31_NOBITS_BASE, \ 67 BL31_NOBITS_LIMIT - \ 68 BL31_NOBITS_BASE, \ 69 MT_MEMORY | MT_RW | EL3_PAS) 70 71 #endif /* SEPARATE_NOBITS_REGION */ 72 73 /****************************************************************************** 74 * Return a pointer to the 'entry_point_info' structure of the next image 75 * for the security state specified. BL33 corresponds to the non-secure 76 * image type while BL32 corresponds to the secure image type. 77 * A NULL pointer is returned if the image does not exist. 78 *****************************************************************************/ 79 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 80 { 81 entry_point_info_t *next_image_info; 82 83 assert(sec_state_is_valid(type)); 84 next_image_info = (type == NON_SECURE) 85 ? &bl33_image_ep_info : &bl32_image_ep_info; 86 /* 87 * None of the images on the ARM development platforms can have 0x0 88 * as the entrypoint 89 */ 90 if (next_image_info->pc) { 91 return next_image_info; 92 } else { 93 return NULL; 94 } 95 } 96 97 int board_uart_init(void) 98 { 99 unsigned long UART_BASE_ADDR; 100 static console_t console; 101 102 #ifdef CONFIG_TARGET_ARBEL_PALLADIUM 103 UART_Init(UART0_DEV, UART_MUX_MODE1, 104 UART_BAUDRATE_115200); 105 UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV); 106 #else 107 UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV); 108 #endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ 109 110 /* 111 * Register UART w/o initialization - 112 * A clock rate of zero means to skip the initialisation. 113 */ 114 console_16550_register((uintptr_t)UART_BASE_ADDR, 0, 0, &console); 115 116 return 0; 117 } 118 119 unsigned int plat_get_syscnt_freq2(void) 120 { 121 return (unsigned int)COUNTER_FREQUENCY; 122 } 123 124 /****************************************************************************** 125 * Perform any BL31 early platform setup common to ARM standard platforms. 126 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 127 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 128 * done before the MMU is initialized so that the memory layout can be used 129 * while creating page tables. BL2 has flushed this information to memory, 130 * so we are guaranteed to pick up good data. 131 *****************************************************************************/ 132 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 133 u_register_t arg2, u_register_t arg3) 134 { 135 #if RESET_TO_BL31 136 void *from_bl2 = (void *)arg0; 137 void *plat_params_from_bl2 = (void *)arg3; 138 139 if (from_bl2 != NULL) { 140 assert(from_bl2 == NULL); 141 } 142 143 if (plat_params_from_bl2 != NULL) { 144 assert(plat_params_from_bl2 == NULL); 145 } 146 #endif /* RESET_TO_BL31 */ 147 148 /* Initialize Delay timer */ 149 generic_delay_timer_init(); 150 151 /* Do Specific Board/Chip initializations */ 152 board_uart_init(); 153 154 #if RESET_TO_BL31 155 /* There are no parameters from BL2 if BL31 is a reset vector */ 156 assert(from_bl2 == NULL); 157 assert(plat_params_from_bl2 == NULL); 158 159 #ifdef BL32_BASE 160 /* Populate entry point information for BL32 */ 161 SET_PARAM_HEAD(&bl32_image_ep_info, 162 PARAM_EP, 163 VERSION_1, 164 0); 165 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 166 bl32_image_ep_info.pc = BL32_BASE; 167 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 168 169 #if defined(SPD_spmd) 170 /* 171 * SPM (hafnium in secure world) expects SPM Core manifest base address 172 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 173 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 174 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 175 * keep it in the last page. 176 */ 177 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 178 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 179 #endif /* SPD_spmd */ 180 #endif /* BL32_BASE */ 181 182 /* Populate entry point information for BL33 */ 183 SET_PARAM_HEAD(&bl33_image_ep_info, 184 PARAM_EP, 185 VERSION_1, 186 0); 187 188 /* 189 * Tell BL31 where the non-trusted software image 190 * is located and the entry state information 191 */ 192 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 193 /* Generic ARM code will switch to EL2, revert to EL1 */ 194 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 195 bl33_image_ep_info.spsr &= ~0x8; 196 bl33_image_ep_info.spsr |= 0x4; 197 198 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, (uint32_t)NON_SECURE); 199 200 #if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33) 201 /* 202 * Hafnium in normal world expects its manifest address in x0, 203 * which is loaded at base of DRAM. 204 */ 205 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; 206 #endif /* SPD_spmd && !ARM_LINUX_KERNEL_AS_BL33 */ 207 208 #if ARM_LINUX_KERNEL_AS_BL33 209 /* 210 * According to the file ``Documentation/arm64/booting.txt`` of the 211 * Linux kernel tree, Linux expects the physical address of the device 212 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 213 * must be 0. 214 */ 215 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 216 bl33_image_ep_info.args.arg1 = 0U; 217 bl33_image_ep_info.args.arg2 = 0U; 218 bl33_image_ep_info.args.arg3 = 0U; 219 #endif /* ARM_LINUX_KERNEL_AS_BL33 */ 220 221 #else /* RESET_TO_BL31 */ 222 /* 223 * In debug builds, we pass a special value in 'plat_params_from_bl2' 224 * to verify platform parameters from BL2 to BL31. 225 * In release builds, it's not used. 226 */ 227 assert(((unsigned long long)plat_params_from_bl2) == 228 ARM_BL31_PLAT_PARAM_VAL); 229 230 /* 231 * Check params passed from BL2 should not be NULL, 232 */ 233 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 234 235 assert(params_from_bl2 != NULL); 236 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 237 assert(params_from_bl2->h.version >= VERSION_2); 238 239 bl_params_node_t *bl_params = params_from_bl2->head; 240 241 /* 242 * Copy BL33 and BL32 (if present), entry point information. 243 * They are stored in Secure RAM, in BL2's address space. 244 */ 245 while (bl_params != NULL) { 246 if (bl_params->image_id == BL32_IMAGE_ID) { 247 bl32_image_ep_info = *bl_params->ep_info; 248 } 249 250 if (bl_params->image_id == BL33_IMAGE_ID) { 251 bl33_image_ep_info = *bl_params->ep_info; 252 } 253 254 bl_params = bl_params->next_params_info; 255 } 256 257 if (bl33_image_ep_info.pc == 0U) { 258 panic(); 259 } 260 #endif /* RESET_TO_BL31 */ 261 } 262 263 /******************************************************************************* 264 * Perform any BL31 platform setup common to ARM standard platforms 265 ******************************************************************************/ 266 void bl31_platform_setup(void) 267 { 268 /* Initialize the GIC driver, cpu and distributor interfaces */ 269 plat_gic_driver_init(); 270 plat_gic_init(); 271 272 #if RESET_TO_BL31 273 #if defined(PLAT_ARM_MEM_PROT_ADDR) 274 arm_nor_psci_do_dyn_mem_protect(); 275 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 276 #else 277 /* 278 * In this soluction, we also do the security initialzation 279 * even when BL31 is not in the reset vector 280 */ 281 npcm845x_security_setup(); 282 #endif /* RESET_TO_BL31 */ 283 284 /* Enable and initialize the System level generic timer */ 285 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 286 CNTCR_FCREQ(0U) | CNTCR_EN); 287 288 /* Initialize power controller before setting up topology */ 289 plat_arm_pwrc_setup(); 290 291 #if RAS_EXTENSION 292 ras_init(); 293 #endif 294 295 #if USE_DEBUGFS 296 debugfs_init(); 297 #endif /* USE_DEBUGFS */ 298 } 299 300 void arm_console_runtime_init(void) 301 { 302 /* Added in order to ignore the original weak function */ 303 } 304 305 void plat_arm_program_trusted_mailbox(uintptr_t address) 306 { 307 /* 308 * now we don't use ARM mailbox, 309 * so that function added to ignore the weak one 310 */ 311 } 312 313 void __init bl31_plat_arch_setup(void) 314 { 315 npcm845x_bl31_plat_arch_setup(); 316 } 317 318 void __init plat_arm_pwrc_setup(void) 319 { 320 /* NPCM850 is always powered so no need for power control */ 321 } 322 323 void __init npcm845x_bl31_plat_arch_setup(void) 324 { 325 const mmap_region_t bl_regions[] = { 326 MAP_BL31_TOTAL, 327 #if RECLAIM_INIT_CODE 328 MAP_BL_INIT_CODE, 329 #endif /* RECLAIM_INIT_CODE */ 330 #if SEPARATE_NOBITS_REGION 331 MAP_BL31_NOBITS, 332 #endif /* SEPARATE_NOBITS_REGION */ 333 ARM_MAP_BL_RO, 334 #if USE_ROMLIB 335 ARM_MAP_ROMLIB_CODE, 336 ARM_MAP_ROMLIB_DATA, 337 #endif /* USE_ROMLIB */ 338 #if USE_COHERENT_MEM 339 ARM_MAP_BL_COHERENT_RAM, 340 #endif /* USE_COHERENT_MEM */ 341 ARM_MAP_SHARED_RAM, 342 #ifdef SECONDARY_BRINGUP 343 ARM_MAP_NS_DRAM1, 344 #ifdef BL32_BASE 345 ARM_MAP_BL32_CORE_MEM 346 #endif /* BL32_BASE */ 347 #endif /* SECONDARY_BRINGUP */ 348 {0} 349 }; 350 setup_page_tables(bl_regions, plat_arm_get_mmap()); 351 enable_mmu_el3(0U); 352 } 353