1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36.. _arm_cpu_macros_errata_workarounds: 37 38CPU Errata Workarounds 39---------------------- 40 41TF-A exports a series of build flags which control the errata workarounds that 42are applied to each CPU by the reset handler. The errata details can be found 43in the CPU specific errata documents published by Arm: 44 45- `Cortex-A53 MPCore Software Developers Errata Notice`_ 46- `Cortex-A57 MPCore Software Developers Errata Notice`_ 47- `Cortex-A72 MPCore Software Developers Errata Notice`_ 48 49The errata workarounds are implemented for a particular revision or a set of 50processor revisions. This is checked by the reset handler at runtime. Each 51errata workaround is identified by its ``ID`` as specified in the processor's 52errata notice document. The format of the define used to enable/disable the 53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 54is for example ``A57`` for the ``Cortex_A57`` CPU. 55 56Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to 57write errata workaround functions. 58 59All workarounds are disabled by default. The platform is responsible for 60enabling these workarounds according to its requirement by defining the 61errata workaround build flags in the platform specific makefile. In case 62these workarounds are enabled for the wrong CPU revision then the errata 63workaround is not applied. In the DEBUG build, this is indicated by 64printing a warning to the crash console. 65 66In the current implementation, a platform which has more than 1 variant 67with different revisions of a processor has no runtime mechanism available 68for it to specify which errata workarounds should be enabled or not. 69 70The value of the build flags is 0 by default, that is, disabled. A value of 1 71will enable it. 72 73For Cortex-A9, the following errata build flags are defined : 74 75- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 76 CPU. This needs to be enabled for all revisions of the CPU. 77 78For Cortex-A15, the following errata build flags are defined : 79 80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 82 83- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 85 86For Cortex-A17, the following errata build flags are defined : 87 88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 90 91- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 93 94For Cortex-A35, the following errata build flags are defined : 95 96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 98 99For Cortex-A53, the following errata build flags are defined : 100 101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 103 104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 106 107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 109 110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 115 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 116 sections. 117 118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 120 r0p4 and onwards, this errata is enabled by default in hardware. 121 122- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 123 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 124 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 125 which are 4kB aligned. 126 127- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 128 CPUs. Though the erratum is present in every revision of the CPU, 129 this workaround is only applied to CPUs from r0p3 onwards, which feature 130 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 131 Earlier revisions of the CPU have other errata which require the same 132 workaround in software, so they should be covered anyway. 133 134- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 135 revisions of Cortex-A53 CPU. 136 137For Cortex-A55, the following errata build flags are defined : 138 139- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 140 CPU. This needs to be enabled only for revision r0p0 of the CPU. 141 142- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 143 CPU. This needs to be enabled only for revision r0p0 of the CPU. 144 145- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 146 CPU. This needs to be enabled only for revision r0p0 of the CPU. 147 148- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 149 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 150 151- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 152 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 153 154- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 155 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 156 157- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 158 revisions of Cortex-A55 CPU. 159 160For Cortex-A57, the following errata build flags are defined : 161 162- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 163 CPU. This needs to be enabled only for revision r0p0 of the CPU. 164 165- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 166 CPU. This needs to be enabled only for revision r0p0 of the CPU. 167 168- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 169 CPU. This needs to be enabled only for revision r0p0 of the CPU. 170 171- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 172 CPU. This needs to be enabled only for revision r0p0 of the CPU. 173 174- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 175 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 176 177- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 178 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 179 180- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 181 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 182 183- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 184 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 185 186- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 187 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 188 189- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 190 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 191 192- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 193 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 194 195- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 196 revisions of Cortex-A57 CPU. 197 198For Cortex-A72, the following errata build flags are defined : 199 200- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 201 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 202 203- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 204 revisions of Cortex-A72 CPU. 205 206For Cortex-A73, the following errata build flags are defined : 207 208- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 209 CPU. This needs to be enabled only for revision r0p0 of the CPU. 210 211- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 212 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 213 214For Cortex-A75, the following errata build flags are defined : 215 216- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 217 CPU. This needs to be enabled only for revision r0p0 of the CPU. 218 219- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 220 CPU. This needs to be enabled only for revision r0p0 of the CPU. 221 222For Cortex-A76, the following errata build flags are defined : 223 224- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 225 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 226 227- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 228 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 229 230- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 231 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 232 233- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 234 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 235 236- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 237 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 238 239- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 240 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 241 242- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 243 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 244 245- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 246 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 247 248- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 249 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 250 limitation of errata framework this errata is applied to all revisions 251 of Cortex-A76 CPU. 252 253- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 254 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 255 256- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 257 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 258 259- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 260 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 261 still open. 262 263For Cortex-A77, the following errata build flags are defined : 264 265- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 266 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 267 268- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 269 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 270 271- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 272 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 273 274- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 275 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 276 277- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 278 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 279 280 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 281 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 282 283 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 284 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 285 286For Cortex-A78, the following errata build flags are defined : 287 288- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 289 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 290 291- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 292 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 293 294- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 295 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 296 issue but there is no workaround for that revision. 297 298- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 299 CPU. This needs to be enabled for revisions r0p0 and r1p0. 300 301- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 302 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 303 304- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 305 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It 306 is still open. 307 308- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 309 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 310 is present in r0p0 but there is no workaround. It is still open. 311 312- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 313 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 314 it is still open. 315 316- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 317 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 318 it is still open. 319 320- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78 321 CPU, this erratum affects system configurations that do not use an ARM 322 interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1 323 and r1p2 and it is still open. 324 325- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78 326 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 327 it is still open. 328 329- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78 330 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 331 it is still open. 332 333- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 334 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and 335 it is still open. 336 337For Cortex-A78 AE, the following errata build flags are defined : 338 339- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 340 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 341 This erratum is still open. 342 343- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 344 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 345 erratum is still open. 346 347- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 348 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 349 erratum is still open. 350 351- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 352 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 353 erratum is still open. 354 355- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to 356 Cortex-A78 AE CPU. This erratum affects system configurations that do not use 357 an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and 358 r0p2. This erratum is still open. 359 360For Cortex-A78C, the following errata build flags are defined : 361 362- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to 363 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 364 fixed in r0p1. 365 366- ``ERRATA_A78C_1827440`` : This applies errata 1827440 workaround to 367 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is 368 fixed in r0p1. 369 370- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to 371 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 372 it is still open. 373 374- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 375 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 376 it is still open. 377 378- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 379 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 380 erratum is still open. 381 382- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 383 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 384 erratum is still open. 385 386- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to 387 Cortex-A78C CPU, this erratum affects system configurations that do not use 388 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 389 and is still open. 390 391- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to 392 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 393 This erratum is still open. 394 395- ``ERRATA_A78C_2779484`` : This applies errata 2779484 workaround to 396 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. 397 This erratum is still open. 398 399For Cortex-X1 CPU, the following errata build flags are defined: 400 401- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 402 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 403 404- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 405 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 406 407- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 408 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 409 410For Neoverse N1, the following errata build flags are defined : 411 412- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 413 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 414 415- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 416 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 417 418- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 419 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 420 421- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 422 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 423 424- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 425 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 426 427- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 428 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 429 430- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 431 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 432 433- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 434 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 435 436- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 437 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 438 439- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 440 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 441 442- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 443 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 444 445- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 446 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 447 448- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 449 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 450 revisions r0p0, r1p0, and r2p0 there is no workaround. 451 452- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 453 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 454 still open. 455 456For Neoverse V1, the following errata build flags are defined : 457 458- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 459 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 460 r1p0. 461 462- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 463 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 464 in r1p1. 465 466- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 467 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 468 in r1p1. 469 470- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 471 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 472 in r1p1. 473 474- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 475 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 476 477- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 478 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 479 CPU. 480 481- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 482 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 483 issue is present in r0p0 as well but there is no workaround for that 484 revision. It is still open. 485 486- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 487 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 488 CPU. It is still open. 489 490- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 491 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 492 It is still open. 493 494- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 495 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 496 issue is present in r0p0 as well but there is no workaround for that 497 revision. It is still open. 498 499- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 500 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 501 502- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 503 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 504 It is still open. 505 506- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1 507 CPU, this erratum affects system configurations that do not use an ARM 508 interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1. 509 It has been fixed in r1p2. 510 511- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1 512 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the 513 CPU. It is still open. 514 515- ``ERRATA_V1_2743233``: This applies erratum 2743233 workaround to Neoverse-V1 516 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the 517 CPU. It is still open. 518 519- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1 520 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the 521 CPU. It is still open. 522 523For Neoverse V2, the following errata build flags are defined : 524 525- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 526 CPU, this affects system configurations that do not use and ARM interconnect 527 IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed 528 in r0p2. 529 530- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 531 CPU, this affects all configurations. This needs to be enabled for revisions 532 r0p0 and r0p1. It has been fixed in r0p2. 533 534For Cortex-A710, the following errata build flags are defined : 535 536- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 537 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 538 r2p0 of the CPU. It is still open. 539 540- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 541 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 542 r2p0 of the CPU. It is still open. 543 544- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 545 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 546 and is still open. 547 548- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 549 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 550 of the CPU and is still open. 551 552- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 553 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 554 is still open. 555 556- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to 557 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 558 of the CPU and is still open. 559 560- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 561 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 562 of the CPU and is fixed in r2p1. 563 564- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 565 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 566 of the CPU and is fixed in r2p1. 567 568- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 569 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 570 and is fixed in r2p1. 571 572- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 573 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 574 of the CPU and is fixed in r2p1. 575 576- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 577 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 578 r2p1 of the CPU and is still open. 579 580- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 581 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 582 of the CPU and is fixed in r2p1. 583 584- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 585 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 586 of the CPU and is fixed in r2p1. 587 588- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 589 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 590 of the CPU and is fixed in r2p1. 591 592- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710 593 CPU, and applies to system configurations that do not use and ARM 594 interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and 595 is still open. 596 597- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 598 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 599 r2p1 of the CPU and is still open. 600 601For Neoverse N2, the following errata build flags are defined : 602 603- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 604 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 605 606- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 607 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 608 609- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 610 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 611 612- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 613 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 614 615- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 616 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 617 618- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 619 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. 620 621- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 622 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 623 624- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 625 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 626 627- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 628 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 629 630- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 631 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. 632 633- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 634 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 635 r0p1. 636 637- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 638 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. 639 640- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 641 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 642 r0p1. 643 644- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 645 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 646 in r0p3. 647 648- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 649 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 650 in r0p3. 651 652- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2 653 CPU, this erratum affects system configurations that do not use and ARM 654 interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. 655 It is fixed in r0p3. 656 657- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 658 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed 659 in r0p3. 660 661For Cortex-X2, the following errata build flags are defined : 662 663- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 664 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 665 it is still open. 666 667- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 668 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 669 it is still open. 670 671- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 672 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. 673 674- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2 675 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 676 CPU, it is fixed in r2p1. 677 678- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2 679 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 680 CPU, it is fixed in r2p1. 681 682- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2 683 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the 684 CPU, it is fixed in r2p1. 685 686- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2 687 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed 688 in r2p1. 689 690- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2 691 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 692 CPU and is still open. 693 694- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2 695 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU 696 and is fixed in r2p1. 697 698- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2 699 CPU and affects system configurations that do not use an ARM interconnect IP. 700 This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is 701 still open. 702 703- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 704 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the 705 CPU and is still open. 706 707For Cortex-X3, the following errata build flags are defined : 708 709- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 710 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 711 of the CPU, it is fixed in r1p1. 712 713- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 714 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 715 CPU, it is still open. 716 717For Cortex-A510, the following errata build flags are defined : 718 719- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to 720 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is 721 fixed in r0p1. 722 723- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 724 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 725 r0p2, r0p3 and r1p0, it is fixed in r1p1. 726 727- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 728 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 729 r0p2, it is fixed in r0p3. 730 731- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 732 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 733 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 734 workaround for those revisions. 735 736- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 737 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 738 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 739 ENABLE_MPMM=1. 740 741- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 742 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 743 r0p3 and r1p0, it is fixed in r1p1. 744 745- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 746 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 747 r0p3 and r1p0, it is fixed in r1p1. 748 749- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 750 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 751 r0p3, r1p0 and r1p1. It is fixed in r1p2. 752 753- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 754 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 755 r0p3, r1p0, r1p1, and is fixed in r1p2. 756 757- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 758 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 759 r0p3, r1p0, r1p1. It is fixed in r1p2. 760 761- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to 762 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2, 763 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3. 764 765For Cortex-A715, the following errata build flags are defined : 766 767- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715 768 CPU and affects system configurations that do not use an ARM interconnect 769 IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed 770 in r1p2. 771 772DSU Errata Workarounds 773---------------------- 774 775Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 776Shared Unit) errata. The DSU errata details can be found in the respective Arm 777documentation: 778 779- `Arm DSU Software Developers Errata Notice`_. 780 781Each erratum is identified by an ``ID``, as defined in the DSU errata notice 782document. Thus, the build flags which enable/disable the errata workarounds 783have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 784of DSU errata workarounds are similar to `CPU errata workarounds`_. 785 786For DSU errata, the following build flags are defined: 787 788- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 789 affected DSU configurations. This errata applies only for those DSUs that 790 revision is r0p0 (on r0p1 it is fixed). However, please note that this 791 workaround results in increased DSU power consumption on idle. 792 793- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 794 affected DSU configurations. This errata applies only for those DSUs that 795 contain the ACP interface **and** the DSU revision is older than r2p0 (on 796 r2p0 it is fixed). However, please note that this workaround results in 797 increased DSU power consumption on idle. 798 799- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 800 affected DSU configurations. This errata applies for those DSUs with 801 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 802 please note that this workaround results in increased DSU power consumption 803 on idle. 804 805CPU Specific optimizations 806-------------------------- 807 808This section describes some of the optimizations allowed by the CPU micro 809architecture that can be enabled by the platform as desired. 810 811- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 812 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 813 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 814 of the L2 by set/way flushes any dirty lines from the L1 as well. This 815 is a known safe deviation from the Cortex-A57 TRM defined power down 816 sequence. Each Cortex-A57 based platform must make its own decision on 817 whether to use the optimization. 818 819- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 820 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 821 in a way most programmers expect, and will most probably result in a 822 significant speed degradation to any code that employs them. The Armv8-A 823 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 824 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 825 flag enforces this behaviour. This needs to be enabled only for revisions 826 <= r0p3 of the CPU and is enabled by default. 827 828- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 829 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 830 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 831 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 832 `Cortex-A57 Software Optimization Guide`_. 833 834- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 835 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 836 this bit only if their memory system meets the requirement that cache 837 line fill requests from the Cortex-A57 processor are atomic. Each 838 Cortex-A57 based platform must make its own decision on whether to use 839 the optimization. This flag is disabled by default. 840 841- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 842 level cache(LLC) is present in the system, and that the DataSource field 843 on the master CHI interface indicates when data is returned from the LLC. 844 This is used to control how the LL_CACHE* PMU events count. 845 Default value is 0 (Disabled). 846 847GIC Errata Workarounds 848---------------------- 849- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 850 workaround for the affected GIC600 and GIC600-AE implementations. It applies 851 to implementations of GIC600 and GIC600-AE with revisions less than or equal 852 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 853 then this flag is enabled; otherwise, it is 0 (Disabled). 854 855-------------- 856 857*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.* 858 859.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 860.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 861.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 862.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 863.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 864.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 865.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 866.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 867